diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2169-drm-amd-pp-fix-dpm-randomly-failed-on-Vega10.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2169-drm-amd-pp-fix-dpm-randomly-failed-on-Vega10.patch | 90 |
1 files changed, 90 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2169-drm-amd-pp-fix-dpm-randomly-failed-on-Vega10.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2169-drm-amd-pp-fix-dpm-randomly-failed-on-Vega10.patch new file mode 100644 index 00000000..91a17c63 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2169-drm-amd-pp-fix-dpm-randomly-failed-on-Vega10.patch @@ -0,0 +1,90 @@ +From 0f388a8563d5e79ad2e52fc1b5690a46864c9052 Mon Sep 17 00:00:00 2001 +From: Rex Zhu <Rex.Zhu@amd.com> +Date: Wed, 15 Nov 2017 16:36:30 +0800 +Subject: [PATCH 2169/4131] drm/amd/pp: fix dpm randomly failed on Vega10 + +Change-Id: Ie0a30f16fdd8c665e603a281898901717ec0d901 +Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> +Acked-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 29 +++++++++++----------- + drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h | 1 + + 2 files changed, 16 insertions(+), 14 deletions(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +index 99c488c..5a8eb28 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +@@ -753,6 +753,7 @@ static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr) + uint32_t config_telemetry = 0; + struct pp_atomfwctrl_voltage_table vol_table; + struct cgs_system_info sys_info = {0}; ++ uint32_t reg; + + data = kzalloc(sizeof(struct vega10_hwmgr), GFP_KERNEL); + if (data == NULL) +@@ -859,6 +860,16 @@ static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr) + advanceFanControlParameters.usFanPWMMinLimit * + hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100; + ++ reg = soc15_get_register_offset(DF_HWID, 0, ++ mmDF_CS_AON0_DramBaseAddress0_BASE_IDX, ++ mmDF_CS_AON0_DramBaseAddress0); ++ data->mem_channels = (cgs_read_register(hwmgr->device, reg) & ++ DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK) >> ++ DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT; ++ PP_ASSERT_WITH_CODE(data->mem_channels < ARRAY_SIZE(channel_number), ++ "Mem Channel Index Exceeded maximum!", ++ return -EINVAL); ++ + return result; + } + +@@ -1777,7 +1788,7 @@ static int vega10_populate_all_memory_levels(struct pp_hwmgr *hwmgr) + struct vega10_single_dpm_table *dpm_table = + &(data->dpm_table.mem_table); + int result = 0; +- uint32_t i, j, reg, mem_channels; ++ uint32_t i, j; + + for (i = 0; i < dpm_table->count; i++) { + result = vega10_populate_single_memory_level(hwmgr, +@@ -1801,20 +1812,10 @@ static int vega10_populate_all_memory_levels(struct pp_hwmgr *hwmgr) + i++; + } + +- reg = soc15_get_register_offset(DF_HWID, 0, +- mmDF_CS_AON0_DramBaseAddress0_BASE_IDX, +- mmDF_CS_AON0_DramBaseAddress0); +- mem_channels = (cgs_read_register(hwmgr->device, reg) & +- DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK) >> +- DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT; +- PP_ASSERT_WITH_CODE(mem_channels < ARRAY_SIZE(channel_number), +- "Mem Channel Index Exceeded maximum!", +- return -1); +- +- pp_table->NumMemoryChannels = cpu_to_le16(mem_channels); ++ pp_table->NumMemoryChannels = (uint16_t)(data->mem_channels); + pp_table->MemoryChannelWidth = +- cpu_to_le16(HBM_MEMORY_CHANNEL_WIDTH * +- channel_number[mem_channels]); ++ (uint16_t)(HBM_MEMORY_CHANNEL_WIDTH * ++ channel_number[data->mem_channels]); + + pp_table->LowestUclkReservedForUlv = + (uint8_t)(data->lowest_uclk_reserved_for_ulv); +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h +index b4b461c3..8f7358c 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h +@@ -389,6 +389,7 @@ struct vega10_hwmgr { + uint32_t config_telemetry; + uint32_t smu_version; + uint32_t acg_loop_state; ++ uint32_t mem_channels; + }; + + #define VEGA10_DPM2_NEAR_TDP_DEC 10 +-- +2.7.4 + |