diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2152-drm-amdgpu-use-multipipe-compute-policy-on-non-PL11-.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2152-drm-amdgpu-use-multipipe-compute-policy-on-non-PL11-.patch | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2152-drm-amdgpu-use-multipipe-compute-policy-on-non-PL11-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2152-drm-amdgpu-use-multipipe-compute-policy-on-non-PL11-.patch new file mode 100644 index 00000000..5e5ff0bd --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2152-drm-amdgpu-use-multipipe-compute-policy-on-non-PL11-.patch @@ -0,0 +1,58 @@ +From 82707f5fabe3df8b2119303554a5d5c0d6ba0ba1 Mon Sep 17 00:00:00 2001 +From: Andres Rodriguez <andresx7@gmail.com> +Date: Tue, 26 Sep 2017 12:22:45 -0400 +Subject: [PATCH 2152/4131] drm/amdgpu: use multipipe compute policy on non + PL11 asics + +A performance regression for OpenCL tests on Polaris11 had this feature +disabled for all asics. + +Instead, disable it selectively on the affected asics. + +Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> +Signed-off-by: Andres Rodriguez <andresx7@gmail.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 16 +++++++++++++--- + 1 file changed, 13 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +index 1a8dc93..ad6314c 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +@@ -109,9 +109,20 @@ void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, unsigned max_s + } + } + ++static bool amdgpu_gfx_is_multipipe_capable(struct amdgpu_device *adev) ++{ ++ /* FIXME: spreading the queues across pipes causes perf regressions ++ * on POLARIS11 compute workloads */ ++ if (adev->asic_type == CHIP_POLARIS11) ++ return false; ++ ++ return adev->gfx.mec.num_mec > 1; ++} ++ + void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev) + { + int i, queue, pipe, mec; ++ bool multipipe_policy = amdgpu_gfx_is_multipipe_capable(adev); + + /* policy for amdgpu compute queue ownership */ + for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) { +@@ -124,9 +135,8 @@ void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev) + /* we've run out of HW */ + if (mec >= adev->gfx.mec.num_mec) + break; +- +- /* FIXME: spreading the queues across pipes causes perf regressions */ +- if (0) { ++ ++ if (multipipe_policy) { + /* policy: amdgpu owns the first two queues of the first MEC */ + if (mec == 0 && queue < 2) + set_bit(i, adev->gfx.mec.queue_bitmap); +-- +2.7.4 + |