diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2047-drm-amd-powerplay-retrieve-the-real-time-coreClock-v.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2047-drm-amd-powerplay-retrieve-the-real-time-coreClock-v.patch | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2047-drm-amd-powerplay-retrieve-the-real-time-coreClock-v.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2047-drm-amd-powerplay-retrieve-the-real-time-coreClock-v.patch new file mode 100644 index 00000000..1ae82fc8 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2047-drm-amd-powerplay-retrieve-the-real-time-coreClock-v.patch @@ -0,0 +1,67 @@ +From e15d974a1dc0eda755ff22365dbc97e5267005d0 Mon Sep 17 00:00:00 2001 +From: Evan Quan <evan.quan@amd.com> +Date: Fri, 20 Oct 2017 15:42:34 +0800 +Subject: [PATCH 2047/4131] drm/amd/powerplay: retrieve the real-time coreClock + values + + - Currently, the coreClock value for min/max performance level on raven + is hard-coded. Use the real-time value retrieved by GetGfxMinFreqLimit + and GetGfxMaxFreqLimit PPSMC messages + +Change-Id: Ic581d8f7acc4ba7b545a611c071815a5c53f8bb5 +Signed-off-by: Evan Quan <evan.quan@amd.com> +Acked-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 28 ++++++-------------------- + 1 file changed, 6 insertions(+), 22 deletions(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c +index 40d3d2a..9703ffc 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c +@@ -673,36 +673,20 @@ static int rv_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_p + PHM_PerformanceLevelDesignation designation, uint32_t index, + PHM_PerformanceLevel *level) + { +- const struct rv_power_state *ps; + struct rv_hwmgr *data; +- uint32_t level_index; +- uint32_t i; +- uint32_t vol_dep_record_index = 0; + + if (level == NULL || hwmgr == NULL || state == NULL) + return -EINVAL; + + data = (struct rv_hwmgr *)(hwmgr->backend); +- ps = cast_const_rv_ps(state); +- +- level_index = index > ps->level - 1 ? ps->level - 1 : index; +- level->coreClock = 30000; + +- if (designation == PHM_PerformanceLevelDesignation_PowerContainment) { +- for (i = 1; i < ps->level; i++) { +- if (ps->levels[i].engine_clock > data->dce_slow_sclk_threshold) { +- level->coreClock = 30000; +- break; +- } +- } +- } +- +- if (level_index == 0) { +- vol_dep_record_index = data->clock_vol_info.vdd_dep_on_fclk->count - 1; +- level->memory_clock = +- data->clock_vol_info.vdd_dep_on_fclk->entries[vol_dep_record_index].clk; +- } else { ++ if (index == 0) { + level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk; ++ level->coreClock = data->gfx_min_freq_limit; ++ } else { ++ level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[ ++ data->clock_vol_info.vdd_dep_on_fclk->count - 1].clk; ++ level->coreClock = data->gfx_max_freq_limit; + } + + level->nonLocalMemoryFreq = 0; +-- +2.7.4 + |