diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1965-drm-amdgpu-Set-the-correct-value-for-PDEs-PTEs-of-AT.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1965-drm-amdgpu-Set-the-correct-value-for-PDEs-PTEs-of-AT.patch | 81 |
1 files changed, 81 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1965-drm-amdgpu-Set-the-correct-value-for-PDEs-PTEs-of-AT.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1965-drm-amdgpu-Set-the-correct-value-for-PDEs-PTEs-of-AT.patch new file mode 100644 index 00000000..4dcb176b --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1965-drm-amdgpu-Set-the-correct-value-for-PDEs-PTEs-of-AT.patch @@ -0,0 +1,81 @@ +From 00528e5955bd337b47cb98c363e390e2fe7e6be2 Mon Sep 17 00:00:00 2001 +From: Yong Zhao <Yong.Zhao@amd.com> +Date: Thu, 31 Aug 2017 15:55:00 -0400 +Subject: [PATCH 1965/4131] drm/amdgpu: Set the correct value for PDEs/PTEs of + ATC memory on Raven +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Without the additional bits set in PDEs/PTEs, the ATC memory access +would have failed on Raven. + +Change-Id: I28429ef6d39cdb01dc6f17fea4264ee22d7121d4 +Signed-off-by: Yong Zhao <yong.zhao@amd.com> +Acked-by: Alex Deucher <alexander.deucher@amd.com> +Reviewed-by: Christian König <christian.koenig@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 9 ++++++--- + drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 10 ++++++++++ + 2 files changed, 16 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +index e4a2a09..8517a6b 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +@@ -337,9 +337,10 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev, + AMDGPU_GEM_CREATE_SHADOW); + + if (vm->pte_support_ats) { +- init_value = AMDGPU_PTE_SYSTEM; ++ init_value = AMDGPU_PTE_DEFAULT_ATC; + if (level != adev->vm_manager.num_level - 1) + init_value |= AMDGPU_PDE_PTE; ++ + } + + /* walk over the address space and allocate the page tables */ +@@ -2043,7 +2044,7 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev, + list_del(&mapping->list); + + if (vm->pte_support_ats) +- init_pte_value = AMDGPU_PTE_SYSTEM; ++ init_pte_value = AMDGPU_PTE_DEFAULT_ATC; + + r = amdgpu_vm_bo_update_mapping(adev, NULL, NULL, vm, + mapping->start, mapping->last, +@@ -2657,7 +2658,9 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, + + if (adev->asic_type == CHIP_RAVEN) { + vm->pte_support_ats = true; +- init_pde_value = AMDGPU_PTE_SYSTEM | AMDGPU_PDE_PTE; ++ init_pde_value = AMDGPU_PTE_DEFAULT_ATC ++ | AMDGPU_PDE_PTE; ++ + } + } else + vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +index 1a41459..fb7de5a 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +@@ -73,6 +73,16 @@ struct amdgpu_bo_list_entry; + #define AMDGPU_PTE_MTYPE(a) ((uint64_t)a << 57) + #define AMDGPU_PTE_MTYPE_MASK AMDGPU_PTE_MTYPE(3ULL) + ++/* For Raven */ ++#define AMDGPU_MTYPE_CC 2 ++ ++#define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \ ++ | AMDGPU_PTE_SNOOPED \ ++ | AMDGPU_PTE_EXECUTABLE \ ++ | AMDGPU_PTE_READABLE \ ++ | AMDGPU_PTE_WRITEABLE \ ++ | AMDGPU_PTE_MTYPE(AMDGPU_MTYPE_CC)) ++ + /* How to programm VM fault handling */ + #define AMDGPU_VM_FAULT_STOP_NEVER 0 + #define AMDGPU_VM_FAULT_STOP_FIRST 1 +-- +2.7.4 + |