diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1948-drm-amdgpu-add-new-uvd-enc-ring-methods.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1948-drm-amdgpu-add-new-uvd-enc-ring-methods.patch | 183 |
1 files changed, 183 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1948-drm-amdgpu-add-new-uvd-enc-ring-methods.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1948-drm-amdgpu-add-new-uvd-enc-ring-methods.patch new file mode 100644 index 00000000..c5638e2b --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1948-drm-amdgpu-add-new-uvd-enc-ring-methods.patch @@ -0,0 +1,183 @@ +From 9769ffb595c46043ba3811102f734ac03d75e65c Mon Sep 17 00:00:00 2001 +From: James Zhu <James.Zhu@amd.com> +Date: Fri, 29 Sep 2017 16:14:26 -0400 +Subject: [PATCH 1948/4131] drm/amdgpu: add new uvd enc ring methods +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add new UVD encode ring methods get/set/emit/flush/sync to support uvd6.3 HEVC encoding + +Signed-off-by: James Zhu <James.Zhu@amd.com> +Reviewed-and-Tested-by: Leo Liu <leo.liu@amd.com> +Reviewed-by: Christian König <christian.koenig@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 117 ++++++++++++++++++++++++++++++++++ + 1 file changed, 117 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +index 62cd16a..86f669c 100644 +--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +@@ -62,6 +62,22 @@ static uint64_t uvd_v6_0_ring_get_rptr(struct amdgpu_ring *ring) + } + + /** ++ * uvd_v6_0_enc_ring_get_rptr - get enc read pointer ++ * ++ * @ring: amdgpu_ring pointer ++ * ++ * Returns the current hardware enc read pointer ++ */ ++static uint64_t uvd_v6_0_enc_ring_get_rptr(struct amdgpu_ring *ring) ++{ ++ struct amdgpu_device *adev = ring->adev; ++ ++ if (ring == &adev->uvd.ring_enc[0]) ++ return RREG32(mmUVD_RB_RPTR); ++ else ++ return RREG32(mmUVD_RB_RPTR2); ++} ++/** + * uvd_v6_0_ring_get_wptr - get write pointer + * + * @ring: amdgpu_ring pointer +@@ -76,6 +92,23 @@ static uint64_t uvd_v6_0_ring_get_wptr(struct amdgpu_ring *ring) + } + + /** ++ * uvd_v6_0_enc_ring_get_wptr - get enc write pointer ++ * ++ * @ring: amdgpu_ring pointer ++ * ++ * Returns the current hardware enc write pointer ++ */ ++static uint64_t uvd_v6_0_enc_ring_get_wptr(struct amdgpu_ring *ring) ++{ ++ struct amdgpu_device *adev = ring->adev; ++ ++ if (ring == &adev->uvd.ring_enc[0]) ++ return RREG32(mmUVD_RB_WPTR); ++ else ++ return RREG32(mmUVD_RB_WPTR2); ++} ++ ++/** + * uvd_v6_0_ring_set_wptr - set write pointer + * + * @ring: amdgpu_ring pointer +@@ -89,6 +122,25 @@ static void uvd_v6_0_ring_set_wptr(struct amdgpu_ring *ring) + WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); + } + ++/** ++ * uvd_v6_0_enc_ring_set_wptr - set enc write pointer ++ * ++ * @ring: amdgpu_ring pointer ++ * ++ * Commits the enc write pointer to the hardware ++ */ ++static void uvd_v6_0_enc_ring_set_wptr(struct amdgpu_ring *ring) ++{ ++ struct amdgpu_device *adev = ring->adev; ++ ++ if (ring == &adev->uvd.ring_enc[0]) ++ WREG32(mmUVD_RB_WPTR, ++ lower_32_bits(ring->wptr)); ++ else ++ WREG32(mmUVD_RB_WPTR2, ++ lower_32_bits(ring->wptr)); ++} ++ + static int uvd_v6_0_early_init(void *handle) + { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; +@@ -575,6 +627,26 @@ static void uvd_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq + } + + /** ++ * uvd_v6_0_enc_ring_emit_fence - emit an enc fence & trap command ++ * ++ * @ring: amdgpu_ring pointer ++ * @fence: fence to emit ++ * ++ * Write enc a fence and a trap command to the ring. ++ */ ++static void uvd_v6_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, ++ u64 seq, unsigned flags) ++{ ++ WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); ++ ++ amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE); ++ amdgpu_ring_write(ring, addr); ++ amdgpu_ring_write(ring, upper_32_bits(addr)); ++ amdgpu_ring_write(ring, seq); ++ amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP); ++} ++ ++/** + * uvd_v6_0_ring_emit_hdp_flush - emit an hdp flush + * + * @ring: amdgpu_ring pointer +@@ -665,6 +737,24 @@ static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring, + amdgpu_ring_write(ring, ib->length_dw); + } + ++/** ++ * uvd_v6_0_enc_ring_emit_ib - enc execute indirect buffer ++ * ++ * @ring: amdgpu_ring pointer ++ * @ib: indirect buffer to execute ++ * ++ * Write enc ring commands to execute the indirect buffer ++ */ ++static void uvd_v6_0_enc_ring_emit_ib(struct amdgpu_ring *ring, ++ struct amdgpu_ib *ib, unsigned int vm_id, bool ctx_switch) ++{ ++ amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM); ++ amdgpu_ring_write(ring, vm_id); ++ amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); ++ amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); ++ amdgpu_ring_write(ring, ib->length_dw); ++} ++ + static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, + unsigned vm_id, uint64_t pd_addr) + { +@@ -716,6 +806,33 @@ static void uvd_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) + amdgpu_ring_write(ring, 0xE); + } + ++static void uvd_v6_0_enc_ring_emit_pipeline_sync(struct amdgpu_ring *ring) ++{ ++ uint32_t seq = ring->fence_drv.sync_seq; ++ uint64_t addr = ring->fence_drv.gpu_addr; ++ ++ amdgpu_ring_write(ring, HEVC_ENC_CMD_WAIT_GE); ++ amdgpu_ring_write(ring, lower_32_bits(addr)); ++ amdgpu_ring_write(ring, upper_32_bits(addr)); ++ amdgpu_ring_write(ring, seq); ++} ++ ++static void uvd_v6_0_enc_ring_insert_end(struct amdgpu_ring *ring) ++{ ++ amdgpu_ring_write(ring, HEVC_ENC_CMD_END); ++} ++ ++static void uvd_v6_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, ++ unsigned int vm_id, uint64_t pd_addr) ++{ ++ amdgpu_ring_write(ring, HEVC_ENC_CMD_UPDATE_PTB); ++ amdgpu_ring_write(ring, vm_id); ++ amdgpu_ring_write(ring, pd_addr >> 12); ++ ++ amdgpu_ring_write(ring, HEVC_ENC_CMD_FLUSH_TLB); ++ amdgpu_ring_write(ring, vm_id); ++} ++ + static bool uvd_v6_0_is_idle(void *handle) + { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; +-- +2.7.4 + |