diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1937-amdgpu-pp-use-array_size-to-size-the-pwrvirus-tables.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1937-amdgpu-pp-use-array_size-to-size-the-pwrvirus-tables.patch | 76 |
1 files changed, 76 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1937-amdgpu-pp-use-array_size-to-size-the-pwrvirus-tables.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1937-amdgpu-pp-use-array_size-to-size-the-pwrvirus-tables.patch new file mode 100644 index 00000000..87df7627 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1937-amdgpu-pp-use-array_size-to-size-the-pwrvirus-tables.patch @@ -0,0 +1,76 @@ +From bdae1794fb65fe0ea88aa2a8d053cfc473b4e9bb Mon Sep 17 00:00:00 2001 +From: Dave Airlie <airlied@redhat.com> +Date: Fri, 29 Sep 2017 11:12:30 +1000 +Subject: [PATCH 1937/4131] amdgpu/pp: use array_size to size the pwrvirus + tables. + +This avoids fragile hardcoding of array size. + +Signed-off-by: Dave Airlie <airlied@redhat.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h | 3 +-- + drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h | 5 +---- + drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 2 +- + drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c | 2 +- + 4 files changed, 4 insertions(+), 8 deletions(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h b/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h +index 243de29..e202e56 100644 +--- a/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h ++++ b/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h +@@ -35,8 +35,7 @@ struct PWR_Command_Table + }; + typedef struct PWR_Command_Table PWR_Command_Table; + +-#define PWR_VIRUS_TABLE_SIZE 10243 +-static const PWR_Command_Table PwrVirusTable[PWR_VIRUS_TABLE_SIZE] = ++static const PWR_Command_Table PwrVirusTable[] = + { + { 0x100100b6, mmPCIE_INDEX }, + { 0x00000000, mmPCIE_DATA }, +diff --git a/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h b/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h +index 7603986..8edd3e7 100644 +--- a/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h ++++ b/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h +@@ -36,10 +36,7 @@ struct PWR_Command_Table { + + typedef struct PWR_Command_Table PWR_Command_Table; + +- +-#define PWR_VIRUS_TABLE_SIZE 10031 +- +-static const PWR_Command_Table pwr_virus_table[PWR_VIRUS_TABLE_SIZE] = { ++static const PWR_Command_Table pwr_virus_table[] = { + { 0x00000000, mmRLC_CNTL }, + { 0x00000002, mmRLC_SRM_CNTL }, + { 0x15000000, mmCP_ME_CNTL }, +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c +index 3820fe8..289006b 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c +@@ -167,7 +167,7 @@ static int fiji_setup_pwr_virus(struct pp_hwmgr *hwmgr) + + const PWR_Command_Table *pvirus = PwrVirusTable; + +- for (i = 0; i < PWR_VIRUS_TABLE_SIZE; i++) { ++ for (i = 0; i < ARRAY_SIZE(PwrVirusTable); i++) { + reg = pvirus->reg; + data = pvirus->data; + if (reg != 0xffffffff) +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c +index b73b2b4..f039320 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c +@@ -68,7 +68,7 @@ static int polaris10_setup_pwr_virus(struct pp_hwmgr *hwmgr) + + const PWR_Command_Table *pvirus = pwr_virus_table; + +- for (i = 0; i < PWR_VIRUS_TABLE_SIZE; i++) { ++ for (i = 0; i < ARRAY_SIZE(pwr_virus_table); i++) { + reg = pvirus->reg; + data = pvirus->data; + if (reg != 0xffffffff) { +-- +2.7.4 + |