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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1931-drm-amd-powerplay-move-set_clockgating_by_smu-to-pp-.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1931-drm-amd-powerplay-move-set_clockgating_by_smu-to-pp-.patch286
1 files changed, 286 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1931-drm-amd-powerplay-move-set_clockgating_by_smu-to-pp-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1931-drm-amd-powerplay-move-set_clockgating_by_smu-to-pp-.patch
new file mode 100644
index 00000000..6165cbac
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1931-drm-amd-powerplay-move-set_clockgating_by_smu-to-pp-.patch
@@ -0,0 +1,286 @@
+From 9aae4a55acd8791cb7d8ef4fbb0c834241d79477 Mon Sep 17 00:00:00 2001
+From: Rex Zhu <Rex.Zhu@amd.com>
+Date: Tue, 26 Sep 2017 13:39:38 +0800
+Subject: [PATCH 1931/4131] drm/amd/powerplay: move set_clockgating_by_smu to
+ pp func table
+
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 4 +++
+ drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 23 +++++++-----
+ drivers/gpu/drm/amd/amdgpu/vi.c | 22 +++++++-----
+ drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 44 +++++++++++------------
+ drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h | 1 -
+ 5 files changed, 54 insertions(+), 40 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+index 12a4a78..24a89bf 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+@@ -356,6 +356,10 @@ enum amdgpu_pcie_gen {
+ ((adev)->powerplay.pp_funcs->switch_power_profile(\
+ (adev)->powerplay.pp_handle, type))
+
++#define amdgpu_dpm_set_clockgating_by_smu(adev, msg_id) \
++ ((adev)->powerplay.pp_funcs->set_clockgating_by_smu(\
++ (adev)->powerplay.pp_handle, msg_id))
++
+ struct amdgpu_dpm {
+ struct amdgpu_ps *ps;
+ /* number of valid power states */
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+index d29a27b..b5e7049 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+@@ -5987,7 +5987,6 @@ static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev,
+ {
+ uint32_t msg_id, pp_state = 0;
+ uint32_t pp_support_state = 0;
+- void *pp_handle = adev->powerplay.pp_handle;
+
+ if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {
+ if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
+@@ -6005,7 +6004,8 @@ static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev,
+ PP_BLOCK_GFX_CG,
+ pp_support_state,
+ pp_state);
+- amd_set_clockgating_by_smu(pp_handle, msg_id);
++ if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
++ amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
+ }
+
+ if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {
+@@ -6026,7 +6026,8 @@ static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev,
+ PP_BLOCK_GFX_MG,
+ pp_support_state,
+ pp_state);
+- amd_set_clockgating_by_smu(pp_handle, msg_id);
++ if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
++ amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
+ }
+
+ return 0;
+@@ -6038,7 +6039,6 @@ static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
+
+ uint32_t msg_id, pp_state = 0;
+ uint32_t pp_support_state = 0;
+- void *pp_handle = adev->powerplay.pp_handle;
+
+ if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {
+ if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
+@@ -6056,7 +6056,8 @@ static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
+ PP_BLOCK_GFX_CG,
+ pp_support_state,
+ pp_state);
+- amd_set_clockgating_by_smu(pp_handle, msg_id);
++ if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
++ amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
+ }
+
+ if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)) {
+@@ -6075,7 +6076,8 @@ static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
+ PP_BLOCK_GFX_3D,
+ pp_support_state,
+ pp_state);
+- amd_set_clockgating_by_smu(pp_handle, msg_id);
++ if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
++ amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
+ }
+
+ if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {
+@@ -6096,7 +6098,8 @@ static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
+ PP_BLOCK_GFX_MG,
+ pp_support_state,
+ pp_state);
+- amd_set_clockgating_by_smu(pp_handle, msg_id);
++ if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
++ amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
+ }
+
+ if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
+@@ -6111,7 +6114,8 @@ static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
+ PP_BLOCK_GFX_RLC,
+ pp_support_state,
+ pp_state);
+- amd_set_clockgating_by_smu(pp_handle, msg_id);
++ if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
++ amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
+ }
+
+ if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
+@@ -6125,7 +6129,8 @@ static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
+ PP_BLOCK_GFX_CP,
+ pp_support_state,
+ pp_state);
+- amd_set_clockgating_by_smu(pp_handle, msg_id);
++ if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
++ amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
+ }
+
+ return 0;
+diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
+index e131eb3..91778e4 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vi.c
++++ b/drivers/gpu/drm/amd/amdgpu/vi.c
+@@ -1303,7 +1303,6 @@ static int vi_common_set_clockgating_state_by_smu(void *handle,
+ uint32_t msg_id, pp_state = 0;
+ uint32_t pp_support_state = 0;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+- void *pp_handle = adev->powerplay.pp_handle;
+
+ if (adev->cg_flags & (AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_MC_MGCG)) {
+ if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) {
+@@ -1320,7 +1319,8 @@ static int vi_common_set_clockgating_state_by_smu(void *handle,
+ PP_BLOCK_SYS_MC,
+ pp_support_state,
+ pp_state);
+- amd_set_clockgating_by_smu(pp_handle, msg_id);
++ if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
++ amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
+ }
+
+ if (adev->cg_flags & (AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_SDMA_MGCG)) {
+@@ -1338,7 +1338,8 @@ static int vi_common_set_clockgating_state_by_smu(void *handle,
+ PP_BLOCK_SYS_SDMA,
+ pp_support_state,
+ pp_state);
+- amd_set_clockgating_by_smu(pp_handle, msg_id);
++ if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
++ amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
+ }
+
+ if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_MGCG)) {
+@@ -1356,7 +1357,8 @@ static int vi_common_set_clockgating_state_by_smu(void *handle,
+ PP_BLOCK_SYS_HDP,
+ pp_support_state,
+ pp_state);
+- amd_set_clockgating_by_smu(pp_handle, msg_id);
++ if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
++ amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
+ }
+
+
+@@ -1370,7 +1372,8 @@ static int vi_common_set_clockgating_state_by_smu(void *handle,
+ PP_BLOCK_SYS_BIF,
+ PP_STATE_SUPPORT_LS,
+ pp_state);
+- amd_set_clockgating_by_smu(pp_handle, msg_id);
++ if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
++ amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
+ }
+ if (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG) {
+ if (state == AMD_CG_STATE_UNGATE)
+@@ -1382,7 +1385,8 @@ static int vi_common_set_clockgating_state_by_smu(void *handle,
+ PP_BLOCK_SYS_BIF,
+ PP_STATE_SUPPORT_CG,
+ pp_state);
+- amd_set_clockgating_by_smu(pp_handle, msg_id);
++ if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
++ amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
+ }
+
+ if (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS) {
+@@ -1396,7 +1400,8 @@ static int vi_common_set_clockgating_state_by_smu(void *handle,
+ PP_BLOCK_SYS_DRM,
+ PP_STATE_SUPPORT_LS,
+ pp_state);
+- amd_set_clockgating_by_smu(pp_handle, msg_id);
++ if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
++ amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
+ }
+
+ if (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG) {
+@@ -1410,7 +1415,8 @@ static int vi_common_set_clockgating_state_by_smu(void *handle,
+ PP_BLOCK_SYS_ROM,
+ PP_STATE_SUPPORT_CG,
+ pp_state);
+- amd_set_clockgating_by_smu(pp_handle, msg_id);
++ if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
++ amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
+ }
+ return 0;
+ }
+diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+index c041946..22c3c98 100644
+--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
++++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+@@ -223,28 +223,6 @@ static int pp_sw_reset(void *handle)
+ return 0;
+ }
+
+-
+-int amd_set_clockgating_by_smu(void *handle, uint32_t msg_id)
+-{
+- struct pp_hwmgr *hwmgr;
+- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+- int ret = 0;
+-
+- ret = pp_check(pp_handle);
+-
+- if (!ret)
+- return ret;
+-
+- hwmgr = pp_handle->hwmgr;
+-
+- if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
+- pr_info("%s was not implemented.\n", __func__);
+- return 0;
+- }
+-
+- return hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
+-}
+-
+ static int pp_set_powergating_state(void *handle,
+ enum amd_powergating_state state)
+ {
+@@ -336,6 +314,27 @@ static int pp_dpm_fw_loading_complete(void *handle)
+ return 0;
+ }
+
++static int pp_set_clockgating_by_smu(void *handle, uint32_t msg_id)
++{
++ struct pp_hwmgr *hwmgr;
++ struct pp_instance *pp_handle = (struct pp_instance *)handle;
++ int ret = 0;
++
++ ret = pp_check(pp_handle);
++
++ if (ret)
++ return ret;
++
++ hwmgr = pp_handle->hwmgr;
++
++ if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
++ pr_info("%s was not implemented.\n", __func__);
++ return 0;
++ }
++
++ return hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
++}
++
+ static void pp_dpm_en_umd_pstate(struct pp_hwmgr *hwmgr,
+ enum amd_dpm_forced_level *level)
+ {
+@@ -1178,6 +1177,7 @@ const struct amd_pm_funcs pp_dpm_funcs = {
+ .get_power_profile_state = pp_dpm_get_power_profile_state,
+ .set_power_profile_state = pp_dpm_set_power_profile_state,
+ .switch_power_profile = pp_dpm_switch_power_profile,
++ .set_clockgating_by_smu = pp_set_clockgating_by_smu,
+ };
+
+ int amd_powerplay_reset(void *handle)
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
+index e52adc8..95932cc 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
+@@ -304,6 +304,5 @@ int amd_powerplay_display_clock_voltage_request(void *handle,
+ int amd_powerplay_get_display_mode_validation_clocks(void *handle,
+ struct amd_pp_simple_clock_info *output);
+
+-int amd_set_clockgating_by_smu(void *handle, uint32_t msg_id);
+
+ #endif /* _AMD_POWERPLAY_H_ */
+--
+2.7.4
+