diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1885-drm-amd-powerplay-delete-SMUM_WRITE_FIELD.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1885-drm-amd-powerplay-delete-SMUM_WRITE_FIELD.patch | 114 |
1 files changed, 114 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1885-drm-amd-powerplay-delete-SMUM_WRITE_FIELD.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1885-drm-amd-powerplay-delete-SMUM_WRITE_FIELD.patch new file mode 100644 index 00000000..21fc14d4 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1885-drm-amd-powerplay-delete-SMUM_WRITE_FIELD.patch @@ -0,0 +1,114 @@ +From e20bf130ed1369102977d43c45ccab40cb53a6a3 Mon Sep 17 00:00:00 2001 +From: Rex Zhu <Rex.Zhu@amd.com> +Date: Wed, 20 Sep 2017 17:18:16 +0800 +Subject: [PATCH 1885/4131] drm/amd/powerplay: delete SMUM_WRITE_FIELD + +the macro is as same as PHM_WRITE_FIELD + +Change-Id: I67fb21b34970c5b714969e03b5078bc762d32d30 +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> +--- + drivers/gpu/drm/amd/powerplay/inc/smumgr.h | 3 --- + drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c | 6 +++--- + drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c | 4 ++-- + drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 6 +++--- + 4 files changed, 8 insertions(+), 11 deletions(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h +index 10d7457..4433e00 100644 +--- a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h ++++ b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h +@@ -185,9 +185,6 @@ extern bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr); + SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ + reg, field) + +-#define SMUM_WRITE_FIELD(device, reg, field, fieldval) \ +- cgs_write_register(device, mm##reg, \ +- SMUM_SET_FIELD(cgs_read_register(device, mm##reg), reg, field, fieldval)) + + #define SMUM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval) \ + cgs_write_ind_register(device, port, ix##reg, \ +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c +index bbb85ad..eeb530b 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c +@@ -104,7 +104,7 @@ static int ci_set_smc_sram_address(struct pp_hwmgr *hwmgr, + } + + cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, smc_addr); +- SMUM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0); ++ PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0); + return 0; + } + +@@ -2321,14 +2321,14 @@ static int ci_load_smc_ucode(struct pp_hwmgr *hwmgr) + } + + cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, start_addr); +- SMUM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1); ++ PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1); + + for (; byte_count >= 4; byte_count -= 4) { + data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3]; + cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data); + src += 4; + } +- SMUM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0); ++ PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0); + + if (0 != byte_count) { + pr_err("SMC size must be dividable by 4\n"); +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c +index fe57335..b729a39 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c +@@ -97,7 +97,7 @@ static int iceland_upload_smc_firmware_data(struct pp_hwmgr *hwmgr, + PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -EINVAL); + + cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, start_addr); +- SMUM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1); ++ PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1); + + while (byte_count >= 4) { + data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3]; +@@ -106,7 +106,7 @@ static int iceland_upload_smc_firmware_data(struct pp_hwmgr *hwmgr, + byte_count -= 4; + } + +- SMUM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0); ++ PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0); + + PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be dividable by 4.", return -EINVAL); + +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c +index 0f23e23..af5c4d3 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c +@@ -40,7 +40,7 @@ static int smu7_set_smc_sram_address(struct pp_hwmgr *hwmgr, uint32_t smc_addr, + PP_ASSERT_WITH_CODE((limit > (smc_addr + 3)), "SMC addr is beyond the SMC RAM area.", return -EINVAL); + + cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_11, smc_addr); +- SMUM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0); /* on ci, SMC_IND_ACCESS_CNTL is different */ ++ PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0); /* on ci, SMC_IND_ACCESS_CNTL is different */ + return 0; + } + +@@ -506,12 +506,12 @@ static int smu7_upload_smc_firmware_data(struct pp_hwmgr *hwmgr, uint32_t length + PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -EINVAL); + + cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_11, 0x20000); +- SMUM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 1); ++ PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 1); + + for (; byte_count >= 4; byte_count -= 4) + cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, *src++); + +- SMUM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0); ++ PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0); + + PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be dividable by 4.", return -EINVAL); + +-- +2.7.4 + |