diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1883-drm-amd-powerplay-move-macros-to-hwmgr.h.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1883-drm-amd-powerplay-move-macros-to-hwmgr.h.patch | 160 |
1 files changed, 160 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1883-drm-amd-powerplay-move-macros-to-hwmgr.h.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1883-drm-amd-powerplay-move-macros-to-hwmgr.h.patch new file mode 100644 index 00000000..611fffdf --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1883-drm-amd-powerplay-move-macros-to-hwmgr.h.patch @@ -0,0 +1,160 @@ +From 0d63486c04d986736897c48265bd80bdeaec5473 Mon Sep 17 00:00:00 2001 +From: Rex Zhu <Rex.Zhu@amd.com> +Date: Wed, 20 Sep 2017 17:29:23 +0800 +Subject: [PATCH 1883/4131] drm/amd/powerplay: move macros to hwmgr.h + +the macro is not relevant to SMU, +so rename SMU_WAIT_FIELD_UNEQUAL to +PHM_WAIT_FIELD_UNEQUAL and move to hwmgr.h + +Change-Id: Ib0b09233daa31f243d83396c1147e3333976dcd1 +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> +--- + drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 14 ++++++++++++++ + drivers/gpu/drm/amd/powerplay/inc/smumgr.h | 14 -------------- + drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c | 2 +- + drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c | 4 ++-- + drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 2 +- + drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 8 ++++---- + 6 files changed, 22 insertions(+), 22 deletions(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h +index 2ac8d7b..126b44d 100644 +--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h ++++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h +@@ -929,4 +929,18 @@ extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_t + (fieldval) << PHM_FIELD_SHIFT(reg, field), \ + PHM_FIELD_MASK(reg, field)) + ++#define PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \ ++ index, value, mask) \ ++ phm_wait_for_register_unequal(hwmgr, \ ++ index, value, mask) ++ ++#define PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, value, mask) \ ++ PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \ ++ mm##reg, value, mask) ++ ++#define PHM_WAIT_FIELD_UNEQUAL(hwmgr, reg, field, fieldval) \ ++ PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, \ ++ (fieldval) << PHM_FIELD_SHIFT(reg, field), \ ++ PHM_FIELD_MASK(reg, field)) ++ + #endif /* _HWMGR_H_ */ +diff --git a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h +index 099758d..75ba6eb 100644 +--- a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h ++++ b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h +@@ -163,20 +163,6 @@ extern bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr); + SMUM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) << SMUM_FIELD_SHIFT(reg, field), \ + SMUM_FIELD_MASK(reg, field) ) + +-#define SMUM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \ +- index, value, mask) \ +- smum_wait_for_register_unequal(hwmgr, \ +- index, value, mask) +- +-#define SMUM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, value, mask) \ +- SMUM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \ +- mm##reg, value, mask) +- +-#define SMUM_WAIT_FIELD_UNEQUAL(hwmgr, reg, field, fieldval) \ +- SMUM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, \ +- (fieldval) << SMUM_FIELD_SHIFT(reg, field), \ +- SMUM_FIELD_MASK(reg, field)) +- + #define SMUM_GET_FIELD(value, reg, field) \ + (((value) & SMUM_FIELD_MASK(reg, field)) \ + >> SMUM_FIELD_SHIFT(reg, field)) +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c +index b28e4e9..5ae9a6e 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c +@@ -217,7 +217,7 @@ int ci_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg) + + cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, msg); + +- SMUM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0); ++ PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0); + + ret = SMUM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP); + +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c +index 8aee9c8..9628e03 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c +@@ -68,7 +68,7 @@ static int cz_send_msg_to_smc_async(struct pp_hwmgr *hwmgr, uint16_t msg) + if (hwmgr == NULL || hwmgr->device == NULL) + return -EINVAL; + +- result = SMUM_WAIT_FIELD_UNEQUAL(hwmgr, ++ result = PHM_WAIT_FIELD_UNEQUAL(hwmgr, + SMU_MP1_SRBM2P_RESP_0, CONTENT, 0); + if (result != 0) { + pr_err("cz_send_msg_to_smc_async (0x%04x) failed\n", msg); +@@ -90,7 +90,7 @@ static int cz_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg) + if (result != 0) + return result; + +- return SMUM_WAIT_FIELD_UNEQUAL(hwmgr, ++ return PHM_WAIT_FIELD_UNEQUAL(hwmgr, + SMU_MP1_SRBM2P_RESP_0, CONTENT, 0); + } + +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c +index 75ed7c3..0b7cb3b 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c +@@ -101,7 +101,7 @@ static int fiji_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr) + + cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, 0x20000); + cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test); +- SMUM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0); ++ PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0); + + /* Wait for done bit to be set */ + PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c +index a360c3c..0f23e23 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c +@@ -170,7 +170,7 @@ int smu7_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg) + return -EINVAL; + + +- SMUM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0); ++ PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0); + + ret = SMUM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP); + +@@ -179,7 +179,7 @@ int smu7_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg) + + cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, msg); + +- SMUM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0); ++ PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0); + + ret = SMUM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP); + +@@ -202,7 +202,7 @@ int smu7_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, uint16_t msg, ui + return -EINVAL; + } + +- SMUM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0); ++ PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0); + + cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, parameter); + +@@ -222,7 +222,7 @@ int smu7_send_msg_to_smc_offset(struct pp_hwmgr *hwmgr) + + cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test); + +- SMUM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0); ++ PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0); + + if (1 != SMUM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP)) + pr_info("Failed to send Message.\n"); +-- +2.7.4 + |