diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1877-drm-amd-powerplay-refine-powerplay-code.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1877-drm-amd-powerplay-refine-powerplay-code.patch | 2697 |
1 files changed, 2697 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1877-drm-amd-powerplay-refine-powerplay-code.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1877-drm-amd-powerplay-refine-powerplay-code.patch new file mode 100644 index 00000000..3f5a98be --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1877-drm-amd-powerplay-refine-powerplay-code.patch @@ -0,0 +1,2697 @@ +From 9f31463f0c3809b86bffb6b0ba6a55c4f3bd1a4a Mon Sep 17 00:00:00 2001 +From: Rex Zhu <Rex.Zhu@amd.com> +Date: Wed, 20 Sep 2017 14:44:55 +0800 +Subject: [PATCH 1877/4131] drm/amd/powerplay: refine powerplay code. + +delete struct smumgr, put smu backend function table +in struct hwmgr + +Change-Id: I7b73ef062b147b4e7199105a3c101f6c8038cc57 +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> +--- + drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 62 ++++----- + drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 19 ++- + drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 4 +- + .../gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c | 2 +- + drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 40 ++++++ + drivers/gpu/drm/amd/powerplay/inc/pp_instance.h | 2 - + drivers/gpu/drm/amd/powerplay/inc/smumgr.h | 62 +-------- + drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c | 56 ++++---- + drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c | 6 +- + drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c | 38 +++--- + drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c | 54 ++++---- + drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 10 +- + drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c | 50 +++---- + .../gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c | 2 +- + .../gpu/drm/amd/powerplay/smumgr/polaris10_smc.c | 67 +++++----- + .../drm/amd/powerplay/smumgr/polaris10_smumgr.c | 10 +- + drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c | 20 +-- + drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 22 +-- + drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c | 148 ++++++--------------- + drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c | 64 ++++----- + .../gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c | 2 +- + .../gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c | 22 +-- + 22 files changed, 338 insertions(+), 424 deletions(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c +index 1250b63..98f57f2 100644 +--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c ++++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c +@@ -35,13 +35,13 @@ static inline int pp_check(struct pp_instance *handle) + if (handle == NULL || handle->pp_valid != PP_VALID) + return -EINVAL; + +- if (handle->smu_mgr == NULL || handle->smu_mgr->smumgr_funcs == NULL) ++ if (handle->hwmgr == NULL || handle->hwmgr->smumgr_funcs == NULL) + return -EINVAL; + + if (handle->pm_en == 0) + return PP_DPM_DISABLED; + +- if (handle->hwmgr == NULL || handle->hwmgr->hwmgr_func == NULL) ++ if (handle->hwmgr->hwmgr_func == NULL) + return PP_DPM_DISABLED; + + return 0; +@@ -52,38 +52,32 @@ static int pp_early_init(void *handle) + int ret; + struct pp_instance *pp_handle = (struct pp_instance *)handle; + +- ret = smum_early_init(pp_handle); ++ ret = hwmgr_early_init(pp_handle); + if (ret) +- return ret; ++ return -EINVAL; + + if ((pp_handle->pm_en == 0) + || cgs_is_virtualization_enabled(pp_handle->device)) + return PP_DPM_DISABLED; + +- ret = hwmgr_early_init(pp_handle); +- if (ret) { +- pp_handle->pm_en = 0; +- return PP_DPM_DISABLED; +- } +- + return 0; + } + + static int pp_sw_init(void *handle) + { +- struct pp_smumgr *smumgr; ++ struct pp_hwmgr *hwmgr; + int ret = 0; + struct pp_instance *pp_handle = (struct pp_instance *)handle; + + ret = pp_check(pp_handle); + + if (ret == 0 || ret == PP_DPM_DISABLED) { +- smumgr = pp_handle->smu_mgr; ++ hwmgr = pp_handle->hwmgr; + +- if (smumgr->smumgr_funcs->smu_init == NULL) ++ if (hwmgr->smumgr_funcs->smu_init == NULL) + return -EINVAL; + +- ret = smumgr->smumgr_funcs->smu_init(pp_handle->hwmgr); ++ ret = hwmgr->smumgr_funcs->smu_init(hwmgr); + + pr_info("amdgpu: powerplay sw initialized\n"); + } +@@ -92,39 +86,39 @@ static int pp_sw_init(void *handle) + + static int pp_sw_fini(void *handle) + { +- struct pp_smumgr *smumgr; ++ struct pp_hwmgr *hwmgr; + int ret = 0; + struct pp_instance *pp_handle = (struct pp_instance *)handle; + + ret = pp_check(pp_handle); + if (ret == 0 || ret == PP_DPM_DISABLED) { +- smumgr = pp_handle->smu_mgr; ++ hwmgr = pp_handle->hwmgr; + +- if (smumgr->smumgr_funcs->smu_fini == NULL) ++ if (hwmgr->smumgr_funcs->smu_fini == NULL) + return -EINVAL; + +- ret = smumgr->smumgr_funcs->smu_fini(pp_handle->hwmgr); ++ ret = hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr); + } + return ret; + } + + static int pp_hw_init(void *handle) + { +- struct pp_smumgr *smumgr; + int ret = 0; + struct pp_instance *pp_handle = (struct pp_instance *)handle; ++ struct pp_hwmgr *hwmgr; + + ret = pp_check(pp_handle); + + if (ret == 0 || ret == PP_DPM_DISABLED) { +- smumgr = pp_handle->smu_mgr; ++ hwmgr = pp_handle->hwmgr; + +- if (smumgr->smumgr_funcs->start_smu == NULL) ++ if (hwmgr->smumgr_funcs->start_smu == NULL) + return -EINVAL; + +- if(smumgr->smumgr_funcs->start_smu(pp_handle->hwmgr)) { ++ if(hwmgr->smumgr_funcs->start_smu(pp_handle->hwmgr)) { + pr_err("smc start failed\n"); +- smumgr->smumgr_funcs->smu_fini(pp_handle->hwmgr); ++ hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr); + return -EINVAL;; + } + if (ret == PP_DPM_DISABLED) +@@ -137,8 +131,6 @@ static int pp_hw_init(void *handle) + return 0; + err: + pp_handle->pm_en = 0; +- kfree(pp_handle->hwmgr); +- pp_handle->hwmgr = NULL; + return PP_DPM_DISABLED; + } + +@@ -232,7 +224,7 @@ static int pp_suspend(void *handle) + + static int pp_resume(void *handle) + { +- struct pp_smumgr *smumgr; ++ struct pp_hwmgr *hwmgr; + int ret, ret1; + struct pp_instance *pp_handle = (struct pp_instance *)handle; + +@@ -241,15 +233,15 @@ static int pp_resume(void *handle) + if (ret1 != 0 && ret1 != PP_DPM_DISABLED) + return ret1; + +- smumgr = pp_handle->smu_mgr; ++ hwmgr = pp_handle->hwmgr; + +- if (smumgr->smumgr_funcs->start_smu == NULL) ++ if (hwmgr->smumgr_funcs->start_smu == NULL) + return -EINVAL; + +- ret = smumgr->smumgr_funcs->start_smu(pp_handle->hwmgr); ++ ret = hwmgr->smumgr_funcs->start_smu(pp_handle->hwmgr); + if (ret) { + pr_err("smc start failed\n"); +- smumgr->smumgr_funcs->smu_fini(pp_handle->hwmgr); ++ hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr); + return ret; + } + +@@ -1157,13 +1149,9 @@ int amd_powerplay_destroy(void *handle) + { + struct pp_instance *instance = (struct pp_instance *)handle; + +- if (instance->pm_en) { +- kfree(instance->hwmgr); +- instance->hwmgr = NULL; +- } ++ kfree(instance->hwmgr); ++ instance->hwmgr = NULL; + +- kfree(instance->smu_mgr); +- instance->smu_mgr = NULL; + kfree(instance); + instance = NULL; + return 0; +@@ -1174,7 +1162,7 @@ int amd_powerplay_reset(void *handle) + struct pp_instance *instance = (struct pp_instance *)handle; + int ret; + +- if (cgs_is_virtualization_enabled(instance->smu_mgr->device)) ++ if (cgs_is_virtualization_enabled(instance->hwmgr->device)) + return PP_DPM_DISABLED; + + ret = pp_check(instance); +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c +index 484f71c..0ad5037 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c +@@ -37,6 +37,15 @@ + #include "amd_acpi.h" + #include "pp_psm.h" + ++extern const struct pp_smumgr_func ci_smu_funcs; ++extern const struct pp_smumgr_func cz_smu_funcs; ++extern const struct pp_smumgr_func iceland_smu_funcs; ++extern const struct pp_smumgr_func tonga_smu_funcs; ++extern const struct pp_smumgr_func fiji_smu_funcs; ++extern const struct pp_smumgr_func polaris10_smu_funcs; ++extern const struct pp_smumgr_func vega10_smu_funcs; ++extern const struct pp_smumgr_func rv_smu_funcs; ++ + extern int cz_init_function_pointers(struct pp_hwmgr *hwmgr); + static int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr); + static void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr); +@@ -132,7 +141,6 @@ int hwmgr_early_init(struct pp_instance *handle) + return -ENOMEM; + + handle->hwmgr = hwmgr; +- hwmgr->smumgr = handle->smu_mgr; + hwmgr->device = handle->device; + hwmgr->chip_family = handle->chip_family; + hwmgr->chip_id = handle->chip_id; +@@ -144,9 +152,11 @@ int hwmgr_early_init(struct pp_instance *handle) + hwmgr_init_default_caps(hwmgr); + hwmgr_set_user_specify_caps(hwmgr); + hwmgr->fan_ctrl_is_in_default_mode = true; ++ hwmgr->reload_fw = 1; + + switch (hwmgr->chip_family) { + case AMDGPU_FAMILY_CI: ++ hwmgr->smumgr_funcs = &ci_smu_funcs; + ci_set_asic_special_caps(hwmgr); + hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK | + PP_ENABLE_GFX_CG_THRU_SMU); +@@ -154,21 +164,25 @@ int hwmgr_early_init(struct pp_instance *handle) + smu7_init_function_pointers(hwmgr); + break; + case AMDGPU_FAMILY_CZ: ++ hwmgr->smumgr_funcs = &ci_smu_funcs; + cz_init_function_pointers(hwmgr); + break; + case AMDGPU_FAMILY_VI: + switch (hwmgr->chip_id) { + case CHIP_TOPAZ: ++ hwmgr->smumgr_funcs = &iceland_smu_funcs; + topaz_set_asic_special_caps(hwmgr); + hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK | + PP_ENABLE_GFX_CG_THRU_SMU); + hwmgr->pp_table_version = PP_TABLE_V0; + break; + case CHIP_TONGA: ++ hwmgr->smumgr_funcs = &tonga_smu_funcs; + tonga_set_asic_special_caps(hwmgr); + hwmgr->feature_mask &= ~PP_VBI_TIME_SUPPORT_MASK; + break; + case CHIP_FIJI: ++ hwmgr->smumgr_funcs = &fiji_smu_funcs; + fiji_set_asic_special_caps(hwmgr); + hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK | + PP_ENABLE_GFX_CG_THRU_SMU); +@@ -176,6 +190,7 @@ int hwmgr_early_init(struct pp_instance *handle) + case CHIP_POLARIS11: + case CHIP_POLARIS10: + case CHIP_POLARIS12: ++ hwmgr->smumgr_funcs = &polaris10_smu_funcs; + polaris_set_asic_special_caps(hwmgr); + hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK); + break; +@@ -187,6 +202,7 @@ int hwmgr_early_init(struct pp_instance *handle) + case AMDGPU_FAMILY_AI: + switch (hwmgr->chip_id) { + case CHIP_VEGA10: ++ hwmgr->smumgr_funcs = &vega10_smu_funcs; + vega10_hwmgr_init(hwmgr); + break; + default: +@@ -196,6 +212,7 @@ int hwmgr_early_init(struct pp_instance *handle) + case AMDGPU_FAMILY_RV: + switch (hwmgr->chip_id) { + case CHIP_RAVEN: ++ hwmgr->smumgr_funcs = &rv_smu_funcs; + rv_init_function_pointers(hwmgr); + break; + default: +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +index e7ba451..30921b5 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +@@ -1382,7 +1382,7 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr) + data->force_pcie_gen = PP_PCIEGenInvalid; + data->ulv_supported = hwmgr->feature_mask & PP_ULV_MASK ? true : false; + +- if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->smumgr->is_kicker) { ++ if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->is_kicker) { + uint8_t tmp1, tmp2; + uint16_t tmp3 = 0; + atomctrl_get_svi2_info(hwmgr, VOLTAGE_TYPE_VDDC, &tmp1, &tmp2, +@@ -4616,7 +4616,7 @@ static int smu7_set_power_profile_state(struct pp_hwmgr *hwmgr, + + static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable) + { +- struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend); ++ struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend); + + if (smu_data == NULL) + return -EINVAL; +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c +index e7c7662..ac80fc3 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c +@@ -806,7 +806,7 @@ int smu7_enable_didt_config(struct pp_hwmgr *hwmgr) + } else if (hwmgr->chip_id == CHIP_POLARIS11) { + result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_Polaris11); + PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result); +- if (hwmgr->smumgr->is_kicker) ++ if (hwmgr->is_kicker) + result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris11_Kicker); + else + result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris11); +diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h +index 1b212b5..859cca4 100644 +--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h ++++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h +@@ -235,6 +235,39 @@ struct phm_vce_clock_voltage_dependency_table { + struct phm_vce_clock_voltage_dependency_record entries[1]; + }; + ++struct pp_smumgr_func { ++ int (*smu_init)(struct pp_hwmgr *hwmgr); ++ int (*smu_fini)(struct pp_hwmgr *hwmgr); ++ int (*start_smu)(struct pp_hwmgr *hwmgr); ++ int (*check_fw_load_finish)(struct pp_hwmgr *hwmgr, ++ uint32_t firmware); ++ int (*request_smu_load_fw)(struct pp_hwmgr *hwmgr); ++ int (*request_smu_load_specific_fw)(struct pp_hwmgr *hwmgr, ++ uint32_t firmware); ++ int (*get_argument)(struct pp_hwmgr *hwmgr); ++ int (*send_msg_to_smc)(struct pp_hwmgr *hwmgr, uint16_t msg); ++ int (*send_msg_to_smc_with_parameter)(struct pp_hwmgr *hwmgr, ++ uint16_t msg, uint32_t parameter); ++ int (*download_pptable_settings)(struct pp_hwmgr *hwmgr, ++ void **table); ++ int (*upload_pptable_settings)(struct pp_hwmgr *hwmgr); ++ int (*update_smc_table)(struct pp_hwmgr *hwmgr, uint32_t type); ++ int (*process_firmware_header)(struct pp_hwmgr *hwmgr); ++ int (*update_sclk_threshold)(struct pp_hwmgr *hwmgr); ++ int (*thermal_setup_fan_table)(struct pp_hwmgr *hwmgr); ++ int (*thermal_avfs_enable)(struct pp_hwmgr *hwmgr); ++ int (*init_smc_table)(struct pp_hwmgr *hwmgr); ++ int (*populate_all_graphic_levels)(struct pp_hwmgr *hwmgr); ++ int (*populate_all_memory_levels)(struct pp_hwmgr *hwmgr); ++ int (*initialize_mc_reg_table)(struct pp_hwmgr *hwmgr); ++ uint32_t (*get_offsetof)(uint32_t type, uint32_t member); ++ uint32_t (*get_mac_definition)(uint32_t value); ++ bool (*is_dpm_running)(struct pp_hwmgr *hwmgr); ++ int (*populate_requested_graphic_levels)(struct pp_hwmgr *hwmgr, ++ struct amd_pp_profile *request); ++ bool (*is_hw_avfs_present)(struct pp_hwmgr *hwmgr); ++}; ++ + struct pp_hwmgr_func { + int (*backend_init)(struct pp_hwmgr *hw_mgr); + int (*backend_fini)(struct pp_hwmgr *hw_mgr); +@@ -706,10 +739,17 @@ struct pp_hwmgr { + void *pptable; + struct phm_platform_descriptor platform_descriptor; + void *backend; ++ ++ void *smu_backend; ++ const struct pp_smumgr_func *smumgr_funcs; ++ bool is_kicker; ++ bool reload_fw; ++ + enum PP_DAL_POWERLEVEL dal_power_level; + struct phm_dynamic_state_info dyn_state; + const struct pp_hwmgr_func *hwmgr_func; + const struct pp_table_func *pptable_func; ++ + struct pp_power_state *ps; + enum pp_power_source power_source; + uint32_t num_ps; +diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h b/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h +index 5bf2ee4..25fb146 100644 +--- a/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h ++++ b/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h +@@ -23,7 +23,6 @@ + #ifndef _PP_INSTANCE_H_ + #define _PP_INSTANCE_H_ + +-#include "smumgr.h" + #include "hwmgr.h" + + #define PP_VALID 0x1F1F1F1F +@@ -35,7 +34,6 @@ struct pp_instance { + bool pm_en; + uint32_t feature_mask; + void *device; +- struct pp_smumgr *smu_mgr; + struct pp_hwmgr *hwmgr; + struct mutex pp_lock; + }; +diff --git a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h +index 58581e1..8bdffaa 100644 +--- a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h ++++ b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h +@@ -23,24 +23,13 @@ + #ifndef _SMUMGR_H_ + #define _SMUMGR_H_ + #include <linux/types.h> +-#include "pp_instance.h" + #include "amd_powerplay.h" +- +-struct pp_smumgr; +-struct pp_instance; +-struct pp_hwmgr; ++#include "hwmgr.h" + + #define smu_lower_32_bits(n) ((uint32_t)(n)) + #define smu_upper_32_bits(n) ((uint32_t)(((n)>>16)>>16)) + +-extern const struct pp_smumgr_func ci_smu_funcs; +-extern const struct pp_smumgr_func cz_smu_funcs; +-extern const struct pp_smumgr_func iceland_smu_funcs; +-extern const struct pp_smumgr_func tonga_smu_funcs; +-extern const struct pp_smumgr_func fiji_smu_funcs; +-extern const struct pp_smumgr_func polaris10_smu_funcs; +-extern const struct pp_smumgr_func vega10_smu_funcs; +-extern const struct pp_smumgr_func rv_smu_funcs; ++ + + enum AVFS_BTC_STATUS { + AVFS_BTC_BOOT = 0, +@@ -101,53 +90,6 @@ enum SMU_MAC_DEFINITION { + SMU_UVD_MCLK_HANDSHAKE_DISABLE, + }; + +- +-struct pp_smumgr_func { +- int (*smu_init)(struct pp_hwmgr *hwmgr); +- int (*smu_fini)(struct pp_hwmgr *hwmgr); +- int (*start_smu)(struct pp_hwmgr *hwmgr); +- int (*check_fw_load_finish)(struct pp_hwmgr *hwmgr, +- uint32_t firmware); +- int (*request_smu_load_fw)(struct pp_hwmgr *hwmgr); +- int (*request_smu_load_specific_fw)(struct pp_hwmgr *hwmgr, +- uint32_t firmware); +- int (*get_argument)(struct pp_hwmgr *hwmgr); +- int (*send_msg_to_smc)(struct pp_hwmgr *hwmgr, uint16_t msg); +- int (*send_msg_to_smc_with_parameter)(struct pp_hwmgr *hwmgr, +- uint16_t msg, uint32_t parameter); +- int (*download_pptable_settings)(struct pp_hwmgr *hwmgr, +- void **table); +- int (*upload_pptable_settings)(struct pp_hwmgr *hwmgr); +- int (*update_smc_table)(struct pp_hwmgr *hwmgr, uint32_t type); +- int (*process_firmware_header)(struct pp_hwmgr *hwmgr); +- int (*update_sclk_threshold)(struct pp_hwmgr *hwmgr); +- int (*thermal_setup_fan_table)(struct pp_hwmgr *hwmgr); +- int (*thermal_avfs_enable)(struct pp_hwmgr *hwmgr); +- int (*init_smc_table)(struct pp_hwmgr *hwmgr); +- int (*populate_all_graphic_levels)(struct pp_hwmgr *hwmgr); +- int (*populate_all_memory_levels)(struct pp_hwmgr *hwmgr); +- int (*initialize_mc_reg_table)(struct pp_hwmgr *hwmgr); +- uint32_t (*get_offsetof)(uint32_t type, uint32_t member); +- uint32_t (*get_mac_definition)(uint32_t value); +- bool (*is_dpm_running)(struct pp_hwmgr *hwmgr); +- int (*populate_requested_graphic_levels)(struct pp_hwmgr *hwmgr, +- struct amd_pp_profile *request); +- bool (*is_hw_avfs_present)(struct pp_hwmgr *hwmgr); +-}; +- +-struct pp_smumgr { +- uint32_t chip_family; +- uint32_t chip_id; +- void *device; +- void *backend; +- uint32_t usec_timeout; +- bool reload_fw; +- const struct pp_smumgr_func *smumgr_funcs; +- bool is_kicker; +-}; +- +-extern int smum_early_init(struct pp_instance *handle); +- + extern int smum_get_argument(struct pp_hwmgr *hwmgr); + + extern int smum_download_powerplay_table(struct pp_hwmgr *hwmgr, void **table); +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c +index 78de219..87c8d9e 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c +@@ -236,7 +236,7 @@ int ci_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, + + static void ci_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) + { +- struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); ++ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + struct cgs_system_info sys_info = {0}; + uint32_t dev_id; + +@@ -479,7 +479,7 @@ static int ci_populate_single_graphic_level(struct pp_hwmgr *hwmgr, + int ci_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) + { + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); +- struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); ++ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + struct smu7_dpm_table *dpm_table = &data->dpm_table; + int result = 0; + uint32_t array = smu_data->dpm_table_start + +@@ -520,7 +520,7 @@ int ci_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) + + static int ci_populate_svi_load_line(struct pp_hwmgr *hwmgr) + { +- struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); ++ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + const struct ci_pt_defaults *defaults = smu_data->power_tune_defaults; + + smu_data->power_tune_table.SviLoadLineEn = defaults->svi_load_line_en; +@@ -534,7 +534,7 @@ static int ci_populate_svi_load_line(struct pp_hwmgr *hwmgr) + static int ci_populate_tdc_limit(struct pp_hwmgr *hwmgr) + { + uint16_t tdc_limit; +- struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); ++ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + const struct ci_pt_defaults *defaults = smu_data->power_tune_defaults; + + tdc_limit = (uint16_t)(hwmgr->dyn_state.cac_dtp_table->usTDC * 256); +@@ -549,7 +549,7 @@ static int ci_populate_tdc_limit(struct pp_hwmgr *hwmgr) + + static int ci_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) + { +- struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); ++ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + const struct ci_pt_defaults *defaults = smu_data->power_tune_defaults; + uint32_t temp; + +@@ -569,7 +569,7 @@ static int ci_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) + static int ci_populate_fuzzy_fan(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) + { + uint16_t tmp; +- struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); ++ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + + if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15)) + || 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity) +@@ -584,7 +584,7 @@ static int ci_populate_fuzzy_fan(struct pp_hwmgr *hwmgr, uint32_t fuse_table_off + static int ci_populate_bapm_vddc_vid_sidd(struct pp_hwmgr *hwmgr) + { + int i; +- struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); ++ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + uint8_t *hi_vid = smu_data->power_tune_table.BapmVddCVidHiSidd; + uint8_t *lo_vid = smu_data->power_tune_table.BapmVddCVidLoSidd; + uint8_t *hi2_vid = smu_data->power_tune_table.BapmVddCVidHiSidd2; +@@ -613,7 +613,7 @@ static int ci_populate_bapm_vddc_vid_sidd(struct pp_hwmgr *hwmgr) + static int ci_populate_vddc_vid(struct pp_hwmgr *hwmgr) + { + int i; +- struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); ++ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + uint8_t *vid = smu_data->power_tune_table.VddCVid; + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + +@@ -629,7 +629,7 @@ static int ci_populate_vddc_vid(struct pp_hwmgr *hwmgr) + + static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct pp_hwmgr *hwmgr) + { +- struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); ++ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + u8 *hi_vid = smu_data->power_tune_table.BapmVddCVidHiSidd; + u8 *lo_vid = smu_data->power_tune_table.BapmVddCVidLoSidd; + int i, min, max; +@@ -661,7 +661,7 @@ static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct pp_hwmgr *hwmgr) + + static int ci_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr) + { +- struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); ++ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + uint16_t HiSidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd; + uint16_t LoSidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd; + struct phm_cac_tdp_table *cac_table = hwmgr->dyn_state.cac_dtp_table; +@@ -679,7 +679,7 @@ static int ci_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr) + + static int ci_populate_pm_fuses(struct pp_hwmgr *hwmgr) + { +- struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); ++ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + uint32_t pm_fuse_table_offset; + int ret = 0; + +@@ -721,7 +721,7 @@ static int ci_populate_pm_fuses(struct pp_hwmgr *hwmgr) + + static int ci_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr) + { +- struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); ++ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + const struct ci_pt_defaults *defaults = smu_data->power_tune_defaults; + SMU7_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); +@@ -996,7 +996,7 @@ static int ci_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU7_Discrete_DpmT + { + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + struct smu7_dpm_table *dpm_table = &data->dpm_table; +- struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); ++ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + uint32_t i; + + /* Index dpm_table->pcie_speed_table.count is reserved for PCIE boot level.*/ +@@ -1299,7 +1299,7 @@ static int ci_populate_single_memory_level( + int ci_populate_all_memory_levels(struct pp_hwmgr *hwmgr) + { + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); +- struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); ++ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + struct smu7_dpm_table *dpm_table = &data->dpm_table; + int result; + struct cgs_system_info sys_info = {0}; +@@ -1683,7 +1683,7 @@ static int ci_populate_memory_timing_parameters( + static int ci_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) + { + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); +- struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); ++ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + int result = 0; + SMU7_Discrete_MCArbDramTimingTable arb_regs; + uint32_t i, j; +@@ -1720,7 +1720,7 @@ static int ci_populate_smc_boot_level(struct pp_hwmgr *hwmgr, + { + int result = 0; + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); +- struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); ++ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + + table->GraphicsBootLevel = 0; + table->MemoryBootLevel = 0; +@@ -1758,7 +1758,7 @@ static int ci_populate_smc_boot_level(struct pp_hwmgr *hwmgr, + static int ci_populate_mc_reg_address(struct pp_hwmgr *hwmgr, + SMU7_Discrete_MCRegisters *mc_reg_table) + { +- const struct ci_smumgr *smu_data = (struct ci_smumgr *)hwmgr->smumgr->backend; ++ const struct ci_smumgr *smu_data = (struct ci_smumgr *)hwmgr->smu_backend; + + uint32_t i, j; + +@@ -1800,7 +1800,7 @@ static int ci_convert_mc_reg_table_entry_to_smc( + SMU7_Discrete_MCRegisterSet *mc_reg_table_data + ) + { +- struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); ++ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + uint32_t i = 0; + + for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) { +@@ -1844,7 +1844,7 @@ static int ci_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr, + + static int ci_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr) + { +- struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); ++ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + uint32_t address; + int32_t result; +@@ -1871,7 +1871,7 @@ static int ci_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr) + static int ci_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr) + { + int result; +- struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); ++ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + + memset(&smu_data->mc_regs, 0x00, sizeof(SMU7_Discrete_MCRegisters)); + result = ci_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs)); +@@ -1889,7 +1889,7 @@ static int ci_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr) + static int ci_populate_smc_initial_state(struct pp_hwmgr *hwmgr) + { + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); +- struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); ++ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + uint8_t count, level; + + count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->count); +@@ -1947,7 +1947,7 @@ int ci_init_smc_table(struct pp_hwmgr *hwmgr) + { + int result; + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); +- struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); ++ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + SMU7_Discrete_DpmTable *table = &(smu_data->smc_state_table); + struct pp_atomctrl_gpio_pin_assignment gpio_pin; + u32 i; +@@ -2126,7 +2126,7 @@ int ci_init_smc_table(struct pp_hwmgr *hwmgr) + + int ci_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) + { +- struct ci_smumgr *ci_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); ++ struct ci_smumgr *ci_data = (struct ci_smumgr *)(hwmgr->smu_backend); + SMU7_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE }; + uint32_t duty100; + uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2; +@@ -2213,7 +2213,7 @@ static int ci_program_mem_timing_parameters(struct pp_hwmgr *hwmgr) + int ci_update_sclk_threshold(struct pp_hwmgr *hwmgr) + { + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); +- struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); ++ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + + int result = 0; + uint32_t low_sclk_interrupt_threshold = 0; +@@ -2310,7 +2310,7 @@ static int ci_load_smc_ucode(struct pp_hwmgr *hwmgr) + + cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU, &info); + +- hwmgr->smumgr->is_kicker = info.is_kicker; ++ hwmgr->is_kicker = info.is_kicker; + byte_count = info.image_size; + src = (uint8_t *)info.kptr; + start_addr = info.ucode_start_address; +@@ -2357,7 +2357,7 @@ static int ci_upload_firmware(struct pp_hwmgr *hwmgr) + int ci_process_firmware_header(struct pp_hwmgr *hwmgr) + { + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); +- struct ci_smumgr *ci_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); ++ struct ci_smumgr *ci_data = (struct ci_smumgr *)(hwmgr->smu_backend); + + uint32_t tmp = 0; + int result; +@@ -2669,7 +2669,7 @@ static int ci_set_valid_flag(struct ci_mc_reg_table *table) + int ci_initialize_mc_reg_table(struct pp_hwmgr *hwmgr) + { + int result; +- struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); ++ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + pp_atomctrl_mc_reg_table *table; + struct ci_mc_reg_table *ni_table = &smu_data->mc_reg_table; + uint8_t module_index = ci_get_memory_modile_index(hwmgr); +@@ -2730,7 +2730,7 @@ int ci_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr, + struct amd_pp_profile *request) + { + struct ci_smumgr *smu_data = (struct ci_smumgr *) +- (hwmgr->smumgr->backend); ++ (hwmgr->smu_backend); + struct SMU7_Discrete_GraphicsLevel *levels = + smu_data->smc_state_table.GraphicsLevel; + uint32_t array = smu_data->dpm_table_start + +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c +index d2e24e3..f265f42 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c +@@ -43,15 +43,15 @@ static int ci_smu_init(struct pp_hwmgr *hwmgr) + for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) + ci_priv->activity_target[i] = 30; + +- hwmgr->smumgr->backend = ci_priv; ++ hwmgr->smu_backend = ci_priv; + + return 0; + } + + static int ci_smu_fini(struct pp_hwmgr *hwmgr) + { +- kfree(hwmgr->smumgr->backend); +- hwmgr->smumgr->backend = NULL; ++ kfree(hwmgr->smu_backend); ++ hwmgr->smu_backend = NULL; + cgs_rel_firmware(hwmgr->device, CGS_UCODE_ID_SMU); + return 0; + } +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c +index a6fa0e8..8aee9c8 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c +@@ -181,7 +181,7 @@ static int cz_load_mec_firmware(struct pp_hwmgr *hwmgr) + if (hwmgr == NULL || hwmgr->device == NULL) + return -EINVAL; + +- cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend; ++ cz_smu = (struct cz_smumgr *)hwmgr->smu_backend; + ret = cgs_get_firmware_info(hwmgr->device, + CGS_UCODE_ID_CP_MEC, &info); + +@@ -330,7 +330,7 @@ static int cz_smu_populate_single_scratch_task( + uint8_t type, bool is_last) + { + uint8_t i; +- struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend; ++ struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend; + struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr; + struct SMU_Task *task = &toc->tasks[cz_smu->toc_entry_used_count++]; + +@@ -367,7 +367,7 @@ static int cz_smu_populate_single_ucode_load_task( + bool is_last) + { + uint8_t i; +- struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend; ++ struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend; + struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr; + struct SMU_Task *task = &toc->tasks[cz_smu->toc_entry_used_count++]; + +@@ -393,7 +393,7 @@ static int cz_smu_populate_single_ucode_load_task( + + static int cz_smu_construct_toc_for_rlc_aram_save(struct pp_hwmgr *hwmgr) + { +- struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend; ++ struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend; + + cz_smu->toc_entry_aram = cz_smu->toc_entry_used_count; + cz_smu_populate_single_scratch_task(hwmgr, +@@ -406,7 +406,7 @@ static int cz_smu_construct_toc_for_rlc_aram_save(struct pp_hwmgr *hwmgr) + static int cz_smu_initialize_toc_empty_job_list(struct pp_hwmgr *hwmgr) + { + int i; +- struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend; ++ struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend; + struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr; + + for (i = 0; i < NUM_JOBLIST_ENTRIES; i++) +@@ -417,7 +417,7 @@ static int cz_smu_initialize_toc_empty_job_list(struct pp_hwmgr *hwmgr) + + static int cz_smu_construct_toc_for_vddgfx_enter(struct pp_hwmgr *hwmgr) + { +- struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend; ++ struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend; + struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr; + + toc->JobList[JOB_GFX_SAVE] = (uint8_t)cz_smu->toc_entry_used_count; +@@ -435,7 +435,7 @@ static int cz_smu_construct_toc_for_vddgfx_enter(struct pp_hwmgr *hwmgr) + + static int cz_smu_construct_toc_for_vddgfx_exit(struct pp_hwmgr *hwmgr) + { +- struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend; ++ struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend; + struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr; + + toc->JobList[JOB_GFX_RESTORE] = (uint8_t)cz_smu->toc_entry_used_count; +@@ -477,7 +477,7 @@ static int cz_smu_construct_toc_for_vddgfx_exit(struct pp_hwmgr *hwmgr) + + static int cz_smu_construct_toc_for_power_profiling(struct pp_hwmgr *hwmgr) + { +- struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend; ++ struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend; + + cz_smu->toc_entry_power_profiling_index = cz_smu->toc_entry_used_count; + +@@ -489,7 +489,7 @@ static int cz_smu_construct_toc_for_power_profiling(struct pp_hwmgr *hwmgr) + + static int cz_smu_construct_toc_for_bootup(struct pp_hwmgr *hwmgr) + { +- struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend; ++ struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend; + + cz_smu->toc_entry_initialize_index = cz_smu->toc_entry_used_count; + +@@ -517,7 +517,7 @@ static int cz_smu_construct_toc_for_bootup(struct pp_hwmgr *hwmgr) + + static int cz_smu_construct_toc_for_clock_table(struct pp_hwmgr *hwmgr) + { +- struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend; ++ struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend; + + cz_smu->toc_entry_clock_table = cz_smu->toc_entry_used_count; + +@@ -530,7 +530,7 @@ static int cz_smu_construct_toc_for_clock_table(struct pp_hwmgr *hwmgr) + + static int cz_smu_construct_toc(struct pp_hwmgr *hwmgr) + { +- struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend; ++ struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend; + + cz_smu->toc_entry_used_count = 0; + cz_smu_initialize_toc_empty_job_list(hwmgr); +@@ -546,7 +546,7 @@ static int cz_smu_construct_toc(struct pp_hwmgr *hwmgr) + + static int cz_smu_populate_firmware_entries(struct pp_hwmgr *hwmgr) + { +- struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend; ++ struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend; + uint32_t firmware_type; + uint32_t i; + int ret; +@@ -588,7 +588,7 @@ static int cz_smu_populate_single_scratch_entry( + uint32_t ulsize_byte, + struct cz_buffer_entry *entry) + { +- struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend; ++ struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend; + long long mc_addr = + ((long long)(cz_smu->smu_buffer.mc_addr_high) << 32) + | cz_smu->smu_buffer.mc_addr_low; +@@ -611,7 +611,7 @@ static int cz_smu_populate_single_scratch_entry( + + static int cz_download_pptable_settings(struct pp_hwmgr *hwmgr, void **table) + { +- struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend; ++ struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend; + unsigned long i; + + for (i = 0; i < cz_smu->scratch_buffer_length; i++) { +@@ -640,7 +640,7 @@ static int cz_download_pptable_settings(struct pp_hwmgr *hwmgr, void **table) + + static int cz_upload_pptable_settings(struct pp_hwmgr *hwmgr) + { +- struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend; ++ struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend; + unsigned long i; + + for (i = 0; i < cz_smu->scratch_buffer_length; i++) { +@@ -667,10 +667,10 @@ static int cz_upload_pptable_settings(struct pp_hwmgr *hwmgr) + + static int cz_request_smu_load_fw(struct pp_hwmgr *hwmgr) + { +- struct cz_smumgr *cz_smu = (struct cz_smumgr *)(hwmgr->smumgr->backend); ++ struct cz_smumgr *cz_smu = (struct cz_smumgr *)(hwmgr->smu_backend); + uint32_t smc_address; + +- if (!hwmgr->smumgr->reload_fw) { ++ if (!hwmgr->reload_fw) { + pr_info("skip reloading...\n"); + return 0; + } +@@ -745,7 +745,7 @@ static int cz_smu_init(struct pp_hwmgr *hwmgr) + if (cz_smu == NULL) + return -ENOMEM; + +- hwmgr->smumgr->backend = cz_smu; ++ hwmgr->smu_backend = cz_smu; + + cz_smu->toc_buffer.data_size = 4096; + cz_smu->smu_buffer.data_size = +@@ -830,7 +830,7 @@ static int cz_smu_fini(struct pp_hwmgr *hwmgr) + if (hwmgr == NULL || hwmgr->device == NULL) + return -EINVAL; + +- cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend; ++ cz_smu = (struct cz_smumgr *)hwmgr->smu_backend; + if (cz_smu) { + cgs_free_gpu_mem(hwmgr->device, + cz_smu->toc_buffer.handle); +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c +index 843ed7a..b1a66b5 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c +@@ -198,7 +198,7 @@ static void get_scl_sda_value(uint8_t line, uint8_t *scl, uint8_t *sda) + + static void fiji_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) + { +- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); ++ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + +@@ -216,7 +216,7 @@ static void fiji_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) + static int fiji_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr) + { + +- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); ++ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); + const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults; + + SMU73_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); +@@ -299,7 +299,7 @@ static int fiji_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr) + + static int fiji_populate_svi_load_line(struct pp_hwmgr *hwmgr) + { +- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); ++ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); + const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults; + + smu_data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn; +@@ -314,7 +314,7 @@ static int fiji_populate_svi_load_line(struct pp_hwmgr *hwmgr) + static int fiji_populate_tdc_limit(struct pp_hwmgr *hwmgr) + { + uint16_t tdc_limit; +- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); ++ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults; +@@ -334,7 +334,7 @@ static int fiji_populate_tdc_limit(struct pp_hwmgr *hwmgr) + + static int fiji_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) + { +- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); ++ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); + const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults; + uint32_t temp; + +@@ -359,7 +359,7 @@ static int fiji_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) + static int fiji_populate_temperature_scaler(struct pp_hwmgr *hwmgr) + { + int i; +- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); ++ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); + + /* Currently not used. Set all to zero. */ + for (i = 0; i < 16; i++) +@@ -370,7 +370,7 @@ static int fiji_populate_temperature_scaler(struct pp_hwmgr *hwmgr) + + static int fiji_populate_fuzzy_fan(struct pp_hwmgr *hwmgr) + { +- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); ++ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); + + if ((hwmgr->thermal_controller.advanceFanControlParameters. + usFanOutputSensitivity & (1 << 15)) || +@@ -389,7 +389,7 @@ static int fiji_populate_fuzzy_fan(struct pp_hwmgr *hwmgr) + static int fiji_populate_gnb_lpml(struct pp_hwmgr *hwmgr) + { + int i; +- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); ++ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); + + /* Currently not used. Set all to zero. */ + for (i = 0; i < 16; i++) +@@ -400,7 +400,7 @@ static int fiji_populate_gnb_lpml(struct pp_hwmgr *hwmgr) + + static int fiji_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr) + { +- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); ++ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + uint16_t HiSidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd; +@@ -421,7 +421,7 @@ static int fiji_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr) + static int fiji_populate_pm_fuses(struct pp_hwmgr *hwmgr) + { + uint32_t pm_fuse_table_offset; +- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); ++ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_PowerContainment)) { +@@ -575,7 +575,7 @@ static int fiji_populate_smc_link_level(struct pp_hwmgr *hwmgr, + { + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + struct smu7_dpm_table *dpm_table = &data->dpm_table; +- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); ++ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); + int i; + + /* Index (dpm_table->pcie_speed_table.count) +@@ -763,7 +763,7 @@ static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr, + int fiji_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) + { + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); +- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); ++ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); + + struct smu7_dpm_table *dpm_table = &data->dpm_table; + struct phm_ppt_v1_information *table_info = +@@ -989,7 +989,7 @@ static int fiji_populate_single_memory_level(struct pp_hwmgr *hwmgr, + int fiji_populate_all_memory_levels(struct pp_hwmgr *hwmgr) + { + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); +- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); ++ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); + struct smu7_dpm_table *dpm_table = &data->dpm_table; + int result; + /* populate MCLK dpm table to SMU7 */ +@@ -1341,7 +1341,7 @@ static int fiji_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr, + static int fiji_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) + { + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); +- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); ++ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); + struct SMU73_Discrete_MCArbDramTimingTable arb_regs; + uint32_t i, j; + int result = 0; +@@ -1449,7 +1449,7 @@ static int fiji_populate_smc_boot_level(struct pp_hwmgr *hwmgr, + static int fiji_populate_smc_initailial_state(struct pp_hwmgr *hwmgr) + { + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); +- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); ++ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + uint8_t count, level; +@@ -1480,7 +1480,7 @@ static int fiji_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr) + uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks, + volt_with_cks, value; + uint16_t clock_freq_u16; +- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); ++ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); + uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2, + volt_offset = 0; + struct phm_ppt_v1_information *table_info = +@@ -1685,7 +1685,7 @@ static int fiji_populate_vr_config(struct pp_hwmgr *hwmgr, + + static int fiji_init_arb_table_index(struct pp_hwmgr *hwmgr) + { +- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); ++ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); + uint32_t tmp; + int result; + +@@ -1712,7 +1712,7 @@ static int fiji_init_arb_table_index(struct pp_hwmgr *hwmgr) + + static int fiji_save_default_power_profile(struct pp_hwmgr *hwmgr) + { +- struct fiji_smumgr *data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); ++ struct fiji_smumgr *data = (struct fiji_smumgr *)(hwmgr->smu_backend); + struct SMU73_Discrete_GraphicsLevel *levels = + data->smc_state_table.GraphicsLevel; + unsigned min_level = 1; +@@ -1788,7 +1788,7 @@ int fiji_init_smc_table(struct pp_hwmgr *hwmgr) + { + int result; + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); +- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); ++ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + struct SMU73_Discrete_DpmTable *table = &(smu_data->smc_state_table); +@@ -2011,7 +2011,7 @@ int fiji_init_smc_table(struct pp_hwmgr *hwmgr) + */ + int fiji_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) + { +- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); ++ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); + + SMU73_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE }; + uint32_t duty100; +@@ -2122,7 +2122,7 @@ int fiji_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) + int fiji_thermal_avfs_enable(struct pp_hwmgr *hwmgr) + { + int ret; +- struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend); ++ struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend); + + if (smu_data->avfs.avfs_btc_status != AVFS_BTC_ENABLEAVFS) + return 0; +@@ -2150,7 +2150,7 @@ static int fiji_program_mem_timing_parameters(struct pp_hwmgr *hwmgr) + int fiji_update_sclk_threshold(struct pp_hwmgr *hwmgr) + { + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); +- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); ++ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); + + int result = 0; + uint32_t low_sclk_interrupt_threshold = 0; +@@ -2244,7 +2244,7 @@ uint32_t fiji_get_mac_definition(uint32_t value) + + static int fiji_update_uvd_smc_table(struct pp_hwmgr *hwmgr) + { +- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); ++ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); + uint32_t mm_boot_level_offset, mm_boot_level_value; + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); +@@ -2276,7 +2276,7 @@ static int fiji_update_uvd_smc_table(struct pp_hwmgr *hwmgr) + + static int fiji_update_vce_smc_table(struct pp_hwmgr *hwmgr) + { +- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); ++ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); + uint32_t mm_boot_level_offset, mm_boot_level_value; + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); +@@ -2308,7 +2308,7 @@ static int fiji_update_vce_smc_table(struct pp_hwmgr *hwmgr) + + static int fiji_update_samu_smc_table(struct pp_hwmgr *hwmgr) + { +- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); ++ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); + uint32_t mm_boot_level_offset, mm_boot_level_value; + + +@@ -2361,7 +2361,7 @@ int fiji_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type) + int fiji_process_firmware_header(struct pp_hwmgr *hwmgr) + { + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); +- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); ++ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); + uint32_t tmp; + int result; + bool error = false; +@@ -2464,7 +2464,7 @@ int fiji_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr, + struct amd_pp_profile *request) + { + struct fiji_smumgr *smu_data = (struct fiji_smumgr *) +- (hwmgr->smumgr->backend); ++ (hwmgr->smu_backend); + struct SMU73_Discrete_GraphicsLevel *levels = + smu_data->smc_state_table.GraphicsLevel; + uint32_t array = smu_data->smu7_data.dpm_table_start + +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c +index dfdcff5..eafac95 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c +@@ -166,7 +166,7 @@ static int fiji_setup_pwr_virus(struct pp_hwmgr *hwmgr) + uint32_t reg, data; + + const PWR_Command_Table *pvirus = PwrVirusTable; +- struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend); ++ struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend); + + for (i = 0; i < PWR_VIRUS_TABLE_SIZE; i++) { + switch (pvirus->command) { +@@ -195,7 +195,7 @@ static int fiji_setup_pwr_virus(struct pp_hwmgr *hwmgr) + static int fiji_start_avfs_btc(struct pp_hwmgr *hwmgr) + { + int result = 0; +- struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend); ++ struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend); + + if (0 != smu_data->avfs.avfs_btc_param) { + if (0 != smu7_send_msg_to_smc_with_parameter(hwmgr, +@@ -255,7 +255,7 @@ static int fiji_setup_graphics_level_structure(struct pp_hwmgr *hwmgr) + + static int fiji_avfs_event_mgr(struct pp_hwmgr *hwmgr, bool smu_started) + { +- struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend); ++ struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend); + + switch (smu_data->avfs.avfs_btc_status) { + case AVFS_BTC_COMPLETED_PREVIOUSLY: +@@ -296,7 +296,7 @@ static int fiji_avfs_event_mgr(struct pp_hwmgr *hwmgr, bool smu_started) + static int fiji_start_smu(struct pp_hwmgr *hwmgr) + { + int result = 0; +- struct fiji_smumgr *priv = (struct fiji_smumgr *)(hwmgr->smumgr->backend); ++ struct fiji_smumgr *priv = (struct fiji_smumgr *)(hwmgr->smu_backend); + + /* Only start SMC if SMC RAM is not running */ + if (!(smu7_is_smc_ram_running(hwmgr) +@@ -375,7 +375,7 @@ static int fiji_smu_init(struct pp_hwmgr *hwmgr) + if (fiji_priv == NULL) + return -ENOMEM; + +- hwmgr->smumgr->backend = fiji_priv; ++ hwmgr->smu_backend = fiji_priv; + + if (smu7_init(hwmgr)) + return -EINVAL; +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c +index 89d5a27..efb0fc0 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c +@@ -101,7 +101,7 @@ static const struct iceland_pt_defaults defaults_icelandpro = { + + static void iceland_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) + { +- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); ++ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); + struct cgs_system_info sys_info = {0}; + uint32_t dev_id; + +@@ -130,7 +130,7 @@ static void iceland_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) + + static int iceland_populate_svi_load_line(struct pp_hwmgr *hwmgr) + { +- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); ++ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); + const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults; + + smu_data->power_tune_table.SviLoadLineEn = defaults->svi_load_line_en; +@@ -144,7 +144,7 @@ static int iceland_populate_svi_load_line(struct pp_hwmgr *hwmgr) + static int iceland_populate_tdc_limit(struct pp_hwmgr *hwmgr) + { + uint16_t tdc_limit; +- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); ++ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); + const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults; + + tdc_limit = (uint16_t)(hwmgr->dyn_state.cac_dtp_table->usTDC * 256); +@@ -159,7 +159,7 @@ static int iceland_populate_tdc_limit(struct pp_hwmgr *hwmgr) + + static int iceland_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) + { +- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); ++ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); + const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults; + uint32_t temp; + +@@ -184,7 +184,7 @@ static int iceland_populate_temperature_scaler(struct pp_hwmgr *hwmgr) + static int iceland_populate_gnb_lpml(struct pp_hwmgr *hwmgr) + { + int i; +- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); ++ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); + + /* Currently not used. Set all to zero. */ + for (i = 0; i < 8; i++) +@@ -195,7 +195,7 @@ static int iceland_populate_gnb_lpml(struct pp_hwmgr *hwmgr) + + static int iceland_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr) + { +- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); ++ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); + uint16_t HiSidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd; + uint16_t LoSidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd; + struct phm_cac_tdp_table *cac_table = hwmgr->dyn_state.cac_dtp_table; +@@ -214,7 +214,7 @@ static int iceland_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr) + static int iceland_populate_bapm_vddc_vid_sidd(struct pp_hwmgr *hwmgr) + { + int i; +- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); ++ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); + uint8_t *hi_vid = smu_data->power_tune_table.BapmVddCVidHiSidd; + uint8_t *lo_vid = smu_data->power_tune_table.BapmVddCVidLoSidd; + +@@ -240,7 +240,7 @@ static int iceland_populate_bapm_vddc_vid_sidd(struct pp_hwmgr *hwmgr) + static int iceland_populate_vddc_vid(struct pp_hwmgr *hwmgr) + { + int i; +- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); ++ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); + uint8_t *vid = smu_data->power_tune_table.VddCVid; + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + +@@ -259,7 +259,7 @@ static int iceland_populate_vddc_vid(struct pp_hwmgr *hwmgr) + + static int iceland_populate_pm_fuses(struct pp_hwmgr *hwmgr) + { +- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); ++ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); + uint32_t pm_fuse_table_offset; + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, +@@ -590,7 +590,7 @@ static int iceland_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU71_Discret + { + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + struct smu7_dpm_table *dpm_table = &data->dpm_table; +- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); ++ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); + uint32_t i; + + /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */ +@@ -805,7 +805,7 @@ static int iceland_populate_single_graphic_level(struct pp_hwmgr *hwmgr, + int iceland_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) + { + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); +- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); ++ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); + struct smu7_dpm_table *dpm_table = &data->dpm_table; + uint32_t level_array_adress = smu_data->smu7_data.dpm_table_start + + offsetof(SMU71_Discrete_DpmTable, GraphicsLevel); +@@ -1207,7 +1207,7 @@ static int iceland_populate_single_memory_level( + int iceland_populate_all_memory_levels(struct pp_hwmgr *hwmgr) + { + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); +- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); ++ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); + struct smu7_dpm_table *dpm_table = &data->dpm_table; + int result; + +@@ -1485,7 +1485,7 @@ static int iceland_populate_memory_timing_parameters( + static int iceland_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) + { + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); +- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); ++ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); + int result = 0; + SMU71_Discrete_MCArbDramTimingTable arb_regs; + uint32_t i, j; +@@ -1523,7 +1523,7 @@ static int iceland_populate_smc_boot_level(struct pp_hwmgr *hwmgr, + { + int result = 0; + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); +- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); ++ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); + table->GraphicsBootLevel = 0; + table->MemoryBootLevel = 0; + +@@ -1564,7 +1564,7 @@ static int iceland_populate_smc_boot_level(struct pp_hwmgr *hwmgr, + static int iceland_populate_mc_reg_address(struct pp_hwmgr *hwmgr, + SMU71_Discrete_MCRegisters *mc_reg_table) + { +- const struct iceland_smumgr *smu_data = (struct iceland_smumgr *)hwmgr->smumgr->backend; ++ const struct iceland_smumgr *smu_data = (struct iceland_smumgr *)hwmgr->smu_backend; + + uint32_t i, j; + +@@ -1606,7 +1606,7 @@ static int iceland_convert_mc_reg_table_entry_to_smc(struct pp_hwmgr *hwmgr, + SMU71_Discrete_MCRegisterSet *mc_reg_table_data + ) + { +- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); ++ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); + uint32_t i = 0; + + for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) { +@@ -1650,7 +1650,7 @@ static int iceland_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr, + + static int iceland_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr) + { +- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); ++ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + uint32_t address; + int32_t result; +@@ -1678,7 +1678,7 @@ static int iceland_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr) + static int iceland_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr) + { + int result; +- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); ++ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); + + memset(&smu_data->mc_regs, 0x00, sizeof(SMU71_Discrete_MCRegisters)); + result = iceland_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs)); +@@ -1696,7 +1696,7 @@ static int iceland_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr) + static int iceland_populate_smc_initial_state(struct pp_hwmgr *hwmgr) + { + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); +- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); ++ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); + uint8_t count, level; + + count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->count); +@@ -1725,7 +1725,7 @@ static int iceland_populate_smc_initial_state(struct pp_hwmgr *hwmgr) + static int iceland_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr) + { + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); +- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); ++ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); + const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults; + SMU71_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); + struct phm_cac_tdp_table *cac_dtp_table = hwmgr->dyn_state.cac_dtp_table; +@@ -1813,7 +1813,7 @@ int iceland_init_smc_table(struct pp_hwmgr *hwmgr) + { + int result; + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); +- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); ++ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); + SMU71_Discrete_DpmTable *table = &(smu_data->smc_state_table); + + +@@ -1980,7 +1980,7 @@ int iceland_init_smc_table(struct pp_hwmgr *hwmgr) + */ + int iceland_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) + { +- struct smu7_smumgr *smu7_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend); ++ struct smu7_smumgr *smu7_data = (struct smu7_smumgr *)(hwmgr->smu_backend); + SMU71_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE }; + uint32_t duty100; + uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2; +@@ -2070,7 +2070,7 @@ static int iceland_program_mem_timing_parameters(struct pp_hwmgr *hwmgr) + int iceland_update_sclk_threshold(struct pp_hwmgr *hwmgr) + { + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); +- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); ++ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); + + int result = 0; + uint32_t low_sclk_interrupt_threshold = 0; +@@ -2168,7 +2168,7 @@ uint32_t iceland_get_mac_definition(uint32_t value) + int iceland_process_firmware_header(struct pp_hwmgr *hwmgr) + { + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); +- struct smu7_smumgr *smu7_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend); ++ struct smu7_smumgr *smu7_data = (struct smu7_smumgr *)(hwmgr->smu_backend); + + uint32_t tmp; + int result; +@@ -2508,7 +2508,7 @@ static int iceland_set_valid_flag(struct iceland_mc_reg_table *table) + int iceland_initialize_mc_reg_table(struct pp_hwmgr *hwmgr) + { + int result; +- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); ++ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); + pp_atomctrl_mc_reg_table *table; + struct iceland_mc_reg_table *ni_table = &smu_data->mc_reg_table; + uint8_t module_index = iceland_get_memory_modile_index(hwmgr); +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c +index d665272..fd63d28 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c +@@ -208,7 +208,7 @@ static int iceland_smu_init(struct pp_hwmgr *hwmgr) + if (iceland_priv == NULL) + return -ENOMEM; + +- hwmgr->smumgr->backend = iceland_priv; ++ hwmgr->smu_backend = iceland_priv; + + if (smu7_init(hwmgr)) + return -EINVAL; +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c +index 1183151..d0913a6 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c +@@ -148,7 +148,7 @@ static uint16_t scale_fan_gain_settings(uint16_t raw_setting) + + static int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr) + { +- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); ++ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); + + const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults; + SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); +@@ -196,7 +196,7 @@ static int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmg + + static int polaris10_populate_svi_load_line(struct pp_hwmgr *hwmgr) + { +- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); ++ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); + const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults; + + smu_data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn; +@@ -210,7 +210,7 @@ static int polaris10_populate_svi_load_line(struct pp_hwmgr *hwmgr) + static int polaris10_populate_tdc_limit(struct pp_hwmgr *hwmgr) + { + uint16_t tdc_limit; +- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); ++ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults; +@@ -227,7 +227,7 @@ static int polaris10_populate_tdc_limit(struct pp_hwmgr *hwmgr) + + static int polaris10_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) + { +- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); ++ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); + const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults; + uint32_t temp; + +@@ -252,7 +252,7 @@ static int polaris10_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_of + static int polaris10_populate_temperature_scaler(struct pp_hwmgr *hwmgr) + { + int i; +- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); ++ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); + + /* Currently not used. Set all to zero. */ + for (i = 0; i < 16; i++) +@@ -263,7 +263,7 @@ static int polaris10_populate_temperature_scaler(struct pp_hwmgr *hwmgr) + + static int polaris10_populate_fuzzy_fan(struct pp_hwmgr *hwmgr) + { +- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); ++ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); + + /* TO DO move to hwmgr */ + if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15)) +@@ -279,7 +279,7 @@ static int polaris10_populate_fuzzy_fan(struct pp_hwmgr *hwmgr) + static int polaris10_populate_gnb_lpml(struct pp_hwmgr *hwmgr) + { + int i; +- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); ++ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); + + /* Currently not used. Set all to zero. */ + for (i = 0; i < 16; i++) +@@ -290,7 +290,7 @@ static int polaris10_populate_gnb_lpml(struct pp_hwmgr *hwmgr) + + static int polaris10_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr) + { +- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); ++ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + uint16_t hi_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd; +@@ -310,7 +310,7 @@ static int polaris10_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr + + static int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr) + { +- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); ++ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); + uint32_t pm_fuse_table_offset; + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, +@@ -492,7 +492,7 @@ static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr, + state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset * + VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1); + +- if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->smumgr->is_kicker) ++ if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->is_kicker) + state->VddcPhase = data->vddc_phase_shed_control ^ 0x3; + else + state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1; +@@ -514,7 +514,7 @@ static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr, + struct SMU74_Discrete_DpmTable *table) + { + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); +- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); ++ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); + struct smu7_dpm_table *dpm_table = &data->dpm_table; + int i; + +@@ -545,7 +545,7 @@ static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr, + static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr, + SMU74_Discrete_DpmTable *table) + { +- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); ++ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); + uint32_t i, ref_clk; + + struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } }; +@@ -595,7 +595,7 @@ static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr, + static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr, + uint32_t clock, SMU_SclkSetting *sclk_setting) + { +- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); ++ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); + const SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); + struct pp_atomctrl_clock_dividers_ai dividers; + uint32_t ref_clock; +@@ -739,7 +739,7 @@ static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr, + int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) + { + struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); +- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); ++ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); + struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); +@@ -887,7 +887,7 @@ static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr, + int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr) + { + struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); +- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); ++ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); + struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; + int result; + /* populate MCLK dpm table to SMU7 */ +@@ -1187,7 +1187,7 @@ static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr, + static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) + { + struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); +- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); ++ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); + struct SMU74_Discrete_MCArbDramTimingTable arb_regs; + uint32_t i, j; + int result = 0; +@@ -1306,7 +1306,7 @@ static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr, + static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr) + { + struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); +- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); ++ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + uint8_t count, level; +@@ -1337,7 +1337,7 @@ static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr) + static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr) + { + uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min; +- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); ++ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); + + uint8_t i, stretch_amount, stretch_amount2, volt_offset = 0; + struct phm_ppt_v1_information *table_info = +@@ -1420,7 +1420,7 @@ static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr, + struct SMU74_Discrete_DpmTable *table) + { + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); +- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); ++ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); + uint16_t config; + + config = VR_MERGED_WITH_VDDC; +@@ -1464,7 +1464,7 @@ static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr, + static int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr) + { + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); +- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); ++ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); + + SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); + int result = 0; +@@ -1552,7 +1552,7 @@ static int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr) + */ + static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr) + { +- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); ++ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); + uint32_t tmp; + int result; + +@@ -1579,7 +1579,7 @@ static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr) + + static void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) + { +- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); ++ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + +@@ -1596,7 +1596,7 @@ static void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) + + static void polaris10_save_default_power_profile(struct pp_hwmgr *hwmgr) + { +- struct polaris10_smumgr *data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); ++ struct polaris10_smumgr *data = (struct polaris10_smumgr *)(hwmgr->smu_backend); + struct SMU74_Discrete_GraphicsLevel *levels = + data->smc_state_table.GraphicsLevel; + unsigned min_level = 1; +@@ -1640,7 +1640,8 @@ int polaris10_init_smc_table(struct pp_hwmgr *hwmgr) + { + int result; + struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); +- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); ++ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); ++ + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + struct SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); +@@ -1868,7 +1869,7 @@ static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr) + int polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr) + { + int ret; +- struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend); ++ struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend); + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + + if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED) +@@ -1898,7 +1899,7 @@ int polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr) + */ + int polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) + { +- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); ++ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); + SMU74_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE }; + uint32_t duty100; + uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2; +@@ -2006,7 +2007,7 @@ int polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) + + static int polaris10_update_uvd_smc_table(struct pp_hwmgr *hwmgr) + { +- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); ++ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); + uint32_t mm_boot_level_offset, mm_boot_level_value; + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); +@@ -2038,7 +2039,7 @@ static int polaris10_update_uvd_smc_table(struct pp_hwmgr *hwmgr) + + static int polaris10_update_vce_smc_table(struct pp_hwmgr *hwmgr) + { +- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); ++ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); + uint32_t mm_boot_level_offset, mm_boot_level_value; + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); +@@ -2070,7 +2071,7 @@ static int polaris10_update_vce_smc_table(struct pp_hwmgr *hwmgr) + + static int polaris10_update_samu_smc_table(struct pp_hwmgr *hwmgr) + { +- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); ++ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); + uint32_t mm_boot_level_offset, mm_boot_level_value; + + +@@ -2098,7 +2099,7 @@ static int polaris10_update_samu_smc_table(struct pp_hwmgr *hwmgr) + + static int polaris10_update_bif_smc_table(struct pp_hwmgr *hwmgr) + { +- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); ++ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table; +@@ -2136,7 +2137,7 @@ int polaris10_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type) + int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr) + { + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); +- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); ++ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); + + int result = 0; + uint32_t low_sclk_interrupt_threshold = 0; +@@ -2241,7 +2242,7 @@ uint32_t polaris10_get_mac_definition(uint32_t value) + */ + int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr) + { +- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); ++ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + uint32_t tmp; + int result; +@@ -2321,7 +2322,7 @@ int polaris10_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr, + struct amd_pp_profile *request) + { + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *) +- (hwmgr->smumgr->backend); ++ (hwmgr->smu_backend); + struct SMU74_Discrete_GraphicsLevel *levels = + smu_data->smc_state_table.GraphicsLevel; + uint32_t array = smu_data->smu7_data.dpm_table_start + +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c +index 55ba762..884ba2c 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c +@@ -67,7 +67,7 @@ static int polaris10_setup_pwr_virus(struct pp_hwmgr *hwmgr) + uint32_t reg, data; + + const PWR_Command_Table *pvirus = pwr_virus_table; +- struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend); ++ struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend); + + for (i = 0; i < PWR_VIRUS_TABLE_SIZE; i++) { + switch (pvirus->command) { +@@ -96,7 +96,7 @@ static int polaris10_setup_pwr_virus(struct pp_hwmgr *hwmgr) + static int polaris10_perform_btc(struct pp_hwmgr *hwmgr) + { + int result = 0; +- struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend); ++ struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend); + + if (0 != smu_data->avfs.avfs_btc_param) { + if (0 != smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) { +@@ -174,7 +174,7 @@ static int polaris10_setup_graphics_level_structure(struct pp_hwmgr *hwmgr) + static int + polaris10_avfs_event_mgr(struct pp_hwmgr *hwmgr, bool SMU_VFT_INTACT) + { +- struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend); ++ struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend); + + switch (smu_data->avfs.avfs_btc_status) { + case AVFS_BTC_COMPLETED_PREVIOUSLY: +@@ -310,7 +310,7 @@ static int polaris10_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr) + static int polaris10_start_smu(struct pp_hwmgr *hwmgr) + { + int result = 0; +- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); ++ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); + bool SMU_VFT_INTACT; + + /* Only start SMC if SMC RAM is not running */ +@@ -371,7 +371,7 @@ static int polaris10_smu_init(struct pp_hwmgr *hwmgr) + if (smu_data == NULL) + return -ENOMEM; + +- hwmgr->smumgr->backend = smu_data; ++ hwmgr->smu_backend = smu_data; + + if (smu7_init(hwmgr)) + return -EINVAL; +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c +index 54d3052..f9afe88 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c +@@ -159,7 +159,7 @@ int rv_copy_table_from_smc(struct pp_hwmgr *hwmgr, + uint8_t *table, int16_t table_id) + { + struct rv_smumgr *priv = +- (struct rv_smumgr *)(hwmgr->smumgr->backend); ++ (struct rv_smumgr *)(hwmgr->smu_backend); + + PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE, + "Invalid SMU Table ID!", return -EINVAL;); +@@ -192,7 +192,7 @@ int rv_copy_table_to_smc(struct pp_hwmgr *hwmgr, + uint8_t *table, int16_t table_id) + { + struct rv_smumgr *priv = +- (struct rv_smumgr *)(hwmgr->smumgr->backend); ++ (struct rv_smumgr *)(hwmgr->smu_backend); + + PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE, + "Invalid SMU Table ID!", return -EINVAL;); +@@ -287,7 +287,7 @@ static int rv_smc_disable_vcn(struct pp_hwmgr *hwmgr) + static int rv_smu_fini(struct pp_hwmgr *hwmgr) + { + struct rv_smumgr *priv = +- (struct rv_smumgr *)(hwmgr->smumgr->backend); ++ (struct rv_smumgr *)(hwmgr->smu_backend); + + if (priv) { + rv_smc_disable_sdma(hwmgr); +@@ -296,8 +296,8 @@ static int rv_smu_fini(struct pp_hwmgr *hwmgr) + priv->smu_tables.entry[WMTABLE].handle); + cgs_free_gpu_mem(hwmgr->device, + priv->smu_tables.entry[CLOCKTABLE].handle); +- kfree(hwmgr->smumgr->backend); +- hwmgr->smumgr->backend = NULL; ++ kfree(hwmgr->smu_backend); ++ hwmgr->smu_backend = NULL; + } + + return 0; +@@ -327,7 +327,7 @@ static int rv_smu_init(struct pp_hwmgr *hwmgr) + if (!priv) + return -ENOMEM; + +- hwmgr->smumgr->backend = priv; ++ hwmgr->smu_backend = priv; + + /* allocate space for watermarks table */ + smu_allocate_memory(hwmgr->device, +@@ -340,8 +340,8 @@ static int rv_smu_init(struct pp_hwmgr *hwmgr) + + PP_ASSERT_WITH_CODE(kaddr, + "[rv_smu_init] Out of memory for wmtable.", +- kfree(hwmgr->smumgr->backend); +- hwmgr->smumgr->backend = NULL; ++ kfree(hwmgr->smu_backend); ++ hwmgr->smu_backend = NULL; + return -EINVAL); + + priv->smu_tables.entry[WMTABLE].version = 0x01; +@@ -367,8 +367,8 @@ static int rv_smu_init(struct pp_hwmgr *hwmgr) + "[rv_smu_init] Out of memory for CLOCKTABLE.", + cgs_free_gpu_mem(hwmgr->device, + (cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle); +- kfree(hwmgr->smumgr->backend); +- hwmgr->smumgr->backend = NULL; ++ kfree(hwmgr->smu_backend); ++ hwmgr->smu_backend = NULL; + return -EINVAL); + + priv->smu_tables.entry[CLOCKTABLE].version = 0x01; +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c +index cd283e5..412cf6f 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c +@@ -391,12 +391,12 @@ static int smu7_populate_single_firmware_entry(struct pp_hwmgr *hwmgr, + + int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr) + { +- struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend); ++ struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend); + uint32_t fw_to_load; + int result = 0; + struct SMU_DRAMData_TOC *toc; + +- if (!hwmgr->smumgr->reload_fw) { ++ if (!hwmgr->reload_fw) { + pr_info("skip reloading...\n"); + return 0; + } +@@ -483,7 +483,7 @@ int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr) + /* Check if the FW has been loaded, SMU will not return if loading has not finished. */ + int smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr, uint32_t fw_type) + { +- struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend); ++ struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend); + uint32_t fw_mask = smu7_get_mask_for_firmware_type(fw_type); + uint32_t ret; + +@@ -497,7 +497,7 @@ int smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr, uint32_t fw_type) + + int smu7_reload_firmware(struct pp_hwmgr *hwmgr) + { +- return hwmgr->smumgr->smumgr_funcs->start_smu(hwmgr); ++ return hwmgr->smumgr_funcs->start_smu(hwmgr); + } + + static int smu7_upload_smc_firmware_data(struct pp_hwmgr *hwmgr, uint32_t length, uint32_t *src, uint32_t limit) +@@ -523,7 +523,7 @@ static int smu7_upload_smc_firmware_data(struct pp_hwmgr *hwmgr, uint32_t length + int smu7_upload_smu_firmware_image(struct pp_hwmgr *hwmgr) + { + int result = 0; +- struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend); ++ struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend); + + struct cgs_firmware_info info = {0}; + +@@ -534,7 +534,7 @@ int smu7_upload_smu_firmware_image(struct pp_hwmgr *hwmgr) + cgs_get_firmware_info(hwmgr->device, + smu7_convert_fw_type_to_cgs(UCODE_ID_SMU_SK), &info); + +- hwmgr->smumgr->is_kicker = info.is_kicker; ++ hwmgr->is_kicker = info.is_kicker; + + result = smu7_upload_smc_firmware_data(hwmgr, info.image_size, (uint32_t *)info.kptr, SMU7_SMC_SIZE); + +@@ -548,7 +548,7 @@ int smu7_init(struct pp_hwmgr *hwmgr) + uint64_t mc_addr = 0; + + /* Allocate memory for backend private data */ +- smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend); ++ smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend); + smu_data->header_buffer.data_size = + ((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096; + +@@ -568,7 +568,7 @@ int smu7_init(struct pp_hwmgr *hwmgr) + + PP_ASSERT_WITH_CODE((NULL != smu_data->header), + "Out of memory.", +- kfree(hwmgr->smumgr->backend); ++ kfree(hwmgr->smu_backend); + cgs_free_gpu_mem(hwmgr->device, + (cgs_handle_t)smu_data->header_buffer.handle); + return -EINVAL); +@@ -591,7 +591,7 @@ int smu7_init(struct pp_hwmgr *hwmgr) + + PP_ASSERT_WITH_CODE((NULL != internal_buf), + "Out of memory.", +- kfree(hwmgr->smumgr->backend); ++ kfree(hwmgr->smu_backend); + cgs_free_gpu_mem(hwmgr->device, + (cgs_handle_t)smu_data->smu_buffer.handle); + return -EINVAL); +@@ -607,8 +607,8 @@ int smu7_init(struct pp_hwmgr *hwmgr) + + int smu7_smu_fini(struct pp_hwmgr *hwmgr) + { +- kfree(hwmgr->smumgr->backend); +- hwmgr->smumgr->backend = NULL; ++ kfree(hwmgr->smu_backend); ++ hwmgr->smu_backend = NULL; + cgs_rel_firmware(hwmgr->device, CGS_UCODE_ID_SMU); + return 0; + } +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c +index a58346e..d3c12e0 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c +@@ -27,7 +27,6 @@ + #include <linux/slab.h> + #include <linux/types.h> + #include <drm/amdgpu_drm.h> +-#include "pp_instance.h" + #include "smumgr.h" + #include "cgs_common.h" + +@@ -46,89 +45,18 @@ MODULE_FIRMWARE("amdgpu/polaris12_smc.bin"); + MODULE_FIRMWARE("amdgpu/vega10_smc.bin"); + MODULE_FIRMWARE("amdgpu/vega10_acg_smc.bin"); + +-int smum_early_init(struct pp_instance *handle) +-{ +- struct pp_smumgr *smumgr; +- +- if (handle == NULL) +- return -EINVAL; +- +- smumgr = kzalloc(sizeof(struct pp_smumgr), GFP_KERNEL); +- if (smumgr == NULL) +- return -ENOMEM; +- +- smumgr->device = handle->device; +- smumgr->chip_family = handle->chip_family; +- smumgr->chip_id = handle->chip_id; +- smumgr->usec_timeout = AMD_MAX_USEC_TIMEOUT; +- smumgr->reload_fw = 1; +- handle->smu_mgr = smumgr; +- +- switch (smumgr->chip_family) { +- case AMDGPU_FAMILY_CI: +- smumgr->smumgr_funcs = &ci_smu_funcs; +- break; +- case AMDGPU_FAMILY_CZ: +- smumgr->smumgr_funcs = &cz_smu_funcs; +- break; +- case AMDGPU_FAMILY_VI: +- switch (smumgr->chip_id) { +- case CHIP_TOPAZ: +- smumgr->smumgr_funcs = &iceland_smu_funcs; +- break; +- case CHIP_TONGA: +- smumgr->smumgr_funcs = &tonga_smu_funcs; +- break; +- case CHIP_FIJI: +- smumgr->smumgr_funcs = &fiji_smu_funcs; +- break; +- case CHIP_POLARIS11: +- case CHIP_POLARIS10: +- case CHIP_POLARIS12: +- smumgr->smumgr_funcs = &polaris10_smu_funcs; +- break; +- default: +- return -EINVAL; +- } +- break; +- case AMDGPU_FAMILY_AI: +- switch (smumgr->chip_id) { +- case CHIP_VEGA10: +- smumgr->smumgr_funcs = &vega10_smu_funcs; +- break; +- default: +- return -EINVAL; +- } +- break; +- case AMDGPU_FAMILY_RV: +- switch (smumgr->chip_id) { +- case CHIP_RAVEN: +- smumgr->smumgr_funcs = &rv_smu_funcs; +- break; +- default: +- return -EINVAL; +- } +- break; +- default: +- kfree(smumgr); +- return -EINVAL; +- } +- +- return 0; +-} +- + int smum_thermal_avfs_enable(struct pp_hwmgr *hwmgr) + { +- if (NULL != hwmgr->smumgr->smumgr_funcs->thermal_avfs_enable) +- return hwmgr->smumgr->smumgr_funcs->thermal_avfs_enable(hwmgr); ++ if (NULL != hwmgr->smumgr_funcs->thermal_avfs_enable) ++ return hwmgr->smumgr_funcs->thermal_avfs_enable(hwmgr); + + return 0; + } + + int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) + { +- if (NULL != hwmgr->smumgr->smumgr_funcs->thermal_setup_fan_table) +- return hwmgr->smumgr->smumgr_funcs->thermal_setup_fan_table(hwmgr); ++ if (NULL != hwmgr->smumgr_funcs->thermal_setup_fan_table) ++ return hwmgr->smumgr_funcs->thermal_setup_fan_table(hwmgr); + + return 0; + } +@@ -136,8 +64,8 @@ int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) + int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr) + { + +- if (NULL != hwmgr->smumgr->smumgr_funcs->update_sclk_threshold) +- return hwmgr->smumgr->smumgr_funcs->update_sclk_threshold(hwmgr); ++ if (NULL != hwmgr->smumgr_funcs->update_sclk_threshold) ++ return hwmgr->smumgr_funcs->update_sclk_threshold(hwmgr); + + return 0; + } +@@ -145,74 +73,74 @@ int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr) + int smum_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type) + { + +- if (NULL != hwmgr->smumgr->smumgr_funcs->update_smc_table) +- return hwmgr->smumgr->smumgr_funcs->update_smc_table(hwmgr, type); ++ if (NULL != hwmgr->smumgr_funcs->update_smc_table) ++ return hwmgr->smumgr_funcs->update_smc_table(hwmgr, type); + + return 0; + } + + uint32_t smum_get_offsetof(struct pp_hwmgr *hwmgr, uint32_t type, uint32_t member) + { +- if (NULL != hwmgr->smumgr->smumgr_funcs->get_offsetof) +- return hwmgr->smumgr->smumgr_funcs->get_offsetof(type, member); ++ if (NULL != hwmgr->smumgr_funcs->get_offsetof) ++ return hwmgr->smumgr_funcs->get_offsetof(type, member); + + return 0; + } + + int smum_process_firmware_header(struct pp_hwmgr *hwmgr) + { +- if (NULL != hwmgr->smumgr->smumgr_funcs->process_firmware_header) +- return hwmgr->smumgr->smumgr_funcs->process_firmware_header(hwmgr); ++ if (NULL != hwmgr->smumgr_funcs->process_firmware_header) ++ return hwmgr->smumgr_funcs->process_firmware_header(hwmgr); + return 0; + } + + int smum_get_argument(struct pp_hwmgr *hwmgr) + { +- if (NULL != hwmgr->smumgr->smumgr_funcs->get_argument) +- return hwmgr->smumgr->smumgr_funcs->get_argument(hwmgr); ++ if (NULL != hwmgr->smumgr_funcs->get_argument) ++ return hwmgr->smumgr_funcs->get_argument(hwmgr); + + return 0; + } + + uint32_t smum_get_mac_definition(struct pp_hwmgr *hwmgr, uint32_t value) + { +- if (NULL != hwmgr->smumgr->smumgr_funcs->get_mac_definition) +- return hwmgr->smumgr->smumgr_funcs->get_mac_definition(value); ++ if (NULL != hwmgr->smumgr_funcs->get_mac_definition) ++ return hwmgr->smumgr_funcs->get_mac_definition(value); + + return 0; + } + + int smum_download_powerplay_table(struct pp_hwmgr *hwmgr, void **table) + { +- if (NULL != hwmgr->smumgr->smumgr_funcs->download_pptable_settings) +- return hwmgr->smumgr->smumgr_funcs->download_pptable_settings(hwmgr, ++ if (NULL != hwmgr->smumgr_funcs->download_pptable_settings) ++ return hwmgr->smumgr_funcs->download_pptable_settings(hwmgr, + table); + return 0; + } + + int smum_upload_powerplay_table(struct pp_hwmgr *hwmgr) + { +- if (NULL != hwmgr->smumgr->smumgr_funcs->upload_pptable_settings) +- return hwmgr->smumgr->smumgr_funcs->upload_pptable_settings(hwmgr); ++ if (NULL != hwmgr->smumgr_funcs->upload_pptable_settings) ++ return hwmgr->smumgr_funcs->upload_pptable_settings(hwmgr); + + return 0; + } + + int smum_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg) + { +- if (hwmgr == NULL || hwmgr->smumgr->smumgr_funcs->send_msg_to_smc == NULL) ++ if (hwmgr == NULL || hwmgr->smumgr_funcs->send_msg_to_smc == NULL) + return -EINVAL; + +- return hwmgr->smumgr->smumgr_funcs->send_msg_to_smc(hwmgr, msg); ++ return hwmgr->smumgr_funcs->send_msg_to_smc(hwmgr, msg); + } + + int smum_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, + uint16_t msg, uint32_t parameter) + { + if (hwmgr == NULL || +- hwmgr->smumgr->smumgr_funcs->send_msg_to_smc_with_parameter == NULL) ++ hwmgr->smumgr_funcs->send_msg_to_smc_with_parameter == NULL) + return -EINVAL; +- return hwmgr->smumgr->smumgr_funcs->send_msg_to_smc_with_parameter( ++ return hwmgr->smumgr_funcs->send_msg_to_smc_with_parameter( + hwmgr, msg, parameter); + } + +@@ -356,24 +284,24 @@ int smu_free_memory(void *device, void *handle) + + int smum_init_smc_table(struct pp_hwmgr *hwmgr) + { +- if (NULL != hwmgr->smumgr->smumgr_funcs->init_smc_table) +- return hwmgr->smumgr->smumgr_funcs->init_smc_table(hwmgr); ++ if (NULL != hwmgr->smumgr_funcs->init_smc_table) ++ return hwmgr->smumgr_funcs->init_smc_table(hwmgr); + + return 0; + } + + int smum_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) + { +- if (NULL != hwmgr->smumgr->smumgr_funcs->populate_all_graphic_levels) +- return hwmgr->smumgr->smumgr_funcs->populate_all_graphic_levels(hwmgr); ++ if (NULL != hwmgr->smumgr_funcs->populate_all_graphic_levels) ++ return hwmgr->smumgr_funcs->populate_all_graphic_levels(hwmgr); + + return 0; + } + + int smum_populate_all_memory_levels(struct pp_hwmgr *hwmgr) + { +- if (NULL != hwmgr->smumgr->smumgr_funcs->populate_all_memory_levels) +- return hwmgr->smumgr->smumgr_funcs->populate_all_memory_levels(hwmgr); ++ if (NULL != hwmgr->smumgr_funcs->populate_all_memory_levels) ++ return hwmgr->smumgr_funcs->populate_all_memory_levels(hwmgr); + + return 0; + } +@@ -381,16 +309,16 @@ int smum_populate_all_memory_levels(struct pp_hwmgr *hwmgr) + /*this interface is needed by island ci/vi */ + int smum_initialize_mc_reg_table(struct pp_hwmgr *hwmgr) + { +- if (NULL != hwmgr->smumgr->smumgr_funcs->initialize_mc_reg_table) +- return hwmgr->smumgr->smumgr_funcs->initialize_mc_reg_table(hwmgr); ++ if (NULL != hwmgr->smumgr_funcs->initialize_mc_reg_table) ++ return hwmgr->smumgr_funcs->initialize_mc_reg_table(hwmgr); + + return 0; + } + + bool smum_is_dpm_running(struct pp_hwmgr *hwmgr) + { +- if (NULL != hwmgr->smumgr->smumgr_funcs->is_dpm_running) +- return hwmgr->smumgr->smumgr_funcs->is_dpm_running(hwmgr); ++ if (NULL != hwmgr->smumgr_funcs->is_dpm_running) ++ return hwmgr->smumgr_funcs->is_dpm_running(hwmgr); + + return true; + } +@@ -398,8 +326,8 @@ bool smum_is_dpm_running(struct pp_hwmgr *hwmgr) + int smum_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr, + struct amd_pp_profile *request) + { +- if (hwmgr->smumgr->smumgr_funcs->populate_requested_graphic_levels) +- return hwmgr->smumgr->smumgr_funcs->populate_requested_graphic_levels( ++ if (hwmgr->smumgr_funcs->populate_requested_graphic_levels) ++ return hwmgr->smumgr_funcs->populate_requested_graphic_levels( + hwmgr, request); + + return 0; +@@ -407,8 +335,8 @@ int smum_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr, + + bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr) + { +- if (hwmgr->smumgr->smumgr_funcs->is_hw_avfs_present) +- return hwmgr->smumgr->smumgr_funcs->is_hw_avfs_present(hwmgr); ++ if (hwmgr->smumgr_funcs->is_hw_avfs_present) ++ return hwmgr->smumgr_funcs->is_hw_avfs_present(hwmgr); + + return false; + } +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c +index 68e1e19..1f720cc 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c +@@ -406,7 +406,7 @@ static int tonga_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU72_Discrete_ + { + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + struct smu7_dpm_table *dpm_table = &data->dpm_table; +- struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend); ++ struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend); + uint32_t i; + + /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */ +@@ -598,7 +598,7 @@ static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr, + int tonga_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) + { + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); +- struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend); ++ struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend); + struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); + struct smu7_dpm_table *dpm_table = &data->dpm_table; + struct phm_ppt_v1_pcie_table *pcie_table = pptable_info->pcie_table; +@@ -1002,7 +1002,7 @@ int tonga_populate_all_memory_levels(struct pp_hwmgr *hwmgr) + { + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + struct tonga_smumgr *smu_data = +- (struct tonga_smumgr *)(hwmgr->smumgr->backend); ++ (struct tonga_smumgr *)(hwmgr->smu_backend); + struct smu7_dpm_table *dpm_table = &data->dpm_table; + int result; + +@@ -1090,7 +1090,7 @@ static int tonga_populate_smc_acpi_level(struct pp_hwmgr *hwmgr, + { + int result = 0; + struct tonga_smumgr *smu_data = +- (struct tonga_smumgr *)(hwmgr->smumgr->backend); ++ (struct tonga_smumgr *)(hwmgr->smu_backend); + const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + struct pp_atomctrl_clock_dividers_vi dividers; + +@@ -1454,7 +1454,7 @@ static int tonga_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) + { + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + struct tonga_smumgr *smu_data = +- (struct tonga_smumgr *)(hwmgr->smumgr->backend); ++ (struct tonga_smumgr *)(hwmgr->smu_backend); + int result = 0; + SMU72_Discrete_MCArbDramTimingTable arb_regs; + uint32_t i, j; +@@ -1492,7 +1492,7 @@ static int tonga_populate_smc_boot_level(struct pp_hwmgr *hwmgr, + int result = 0; + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + struct tonga_smumgr *smu_data = +- (struct tonga_smumgr *)(hwmgr->smumgr->backend); ++ (struct tonga_smumgr *)(hwmgr->smu_backend); + table->GraphicsBootLevel = 0; + table->MemoryBootLevel = 0; + +@@ -1543,7 +1543,7 @@ static int tonga_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr) + volt_with_cks, value; + uint16_t clock_freq_u16; + struct tonga_smumgr *smu_data = +- (struct tonga_smumgr *)(hwmgr->smumgr->backend); ++ (struct tonga_smumgr *)(hwmgr->smu_backend); + uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2, + volt_offset = 0; + struct phm_ppt_v1_information *table_info = +@@ -1784,7 +1784,7 @@ static int tonga_populate_vr_config(struct pp_hwmgr *hwmgr, + */ + static int tonga_init_arb_table_index(struct pp_hwmgr *hwmgr) + { +- struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend); ++ struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend); + uint32_t tmp; + int result; + +@@ -1814,7 +1814,7 @@ static int tonga_init_arb_table_index(struct pp_hwmgr *hwmgr) + static int tonga_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr) + { + struct tonga_smumgr *smu_data = +- (struct tonga_smumgr *)(hwmgr->smumgr->backend); ++ (struct tonga_smumgr *)(hwmgr->smu_backend); + const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults; + SMU72_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); + struct phm_ppt_v1_information *table_info = +@@ -1861,7 +1861,7 @@ static int tonga_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr) + static int tonga_populate_svi_load_line(struct pp_hwmgr *hwmgr) + { + struct tonga_smumgr *smu_data = +- (struct tonga_smumgr *)(hwmgr->smumgr->backend); ++ (struct tonga_smumgr *)(hwmgr->smu_backend); + const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults; + + smu_data->power_tune_table.SviLoadLineEn = defaults->svi_load_line_en; +@@ -1876,7 +1876,7 @@ static int tonga_populate_tdc_limit(struct pp_hwmgr *hwmgr) + { + uint16_t tdc_limit; + struct tonga_smumgr *smu_data = +- (struct tonga_smumgr *)(hwmgr->smumgr->backend); ++ (struct tonga_smumgr *)(hwmgr->smu_backend); + const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults; + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); +@@ -1897,7 +1897,7 @@ static int tonga_populate_tdc_limit(struct pp_hwmgr *hwmgr) + static int tonga_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) + { + struct tonga_smumgr *smu_data = +- (struct tonga_smumgr *)(hwmgr->smumgr->backend); ++ (struct tonga_smumgr *)(hwmgr->smu_backend); + const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults; + uint32_t temp; + +@@ -1919,7 +1919,7 @@ static int tonga_populate_temperature_scaler(struct pp_hwmgr *hwmgr) + { + int i; + struct tonga_smumgr *smu_data = +- (struct tonga_smumgr *)(hwmgr->smumgr->backend); ++ (struct tonga_smumgr *)(hwmgr->smu_backend); + + /* Currently not used. Set all to zero. */ + for (i = 0; i < 16; i++) +@@ -1930,7 +1930,7 @@ static int tonga_populate_temperature_scaler(struct pp_hwmgr *hwmgr) + + static int tonga_populate_fuzzy_fan(struct pp_hwmgr *hwmgr) + { +- struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend); ++ struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend); + + if ((hwmgr->thermal_controller.advanceFanControlParameters. + usFanOutputSensitivity & (1 << 15)) || +@@ -1949,7 +1949,7 @@ static int tonga_populate_gnb_lpml(struct pp_hwmgr *hwmgr) + { + int i; + struct tonga_smumgr *smu_data = +- (struct tonga_smumgr *)(hwmgr->smumgr->backend); ++ (struct tonga_smumgr *)(hwmgr->smu_backend); + + /* Currently not used. Set all to zero. */ + for (i = 0; i < 16; i++) +@@ -1961,7 +1961,7 @@ static int tonga_populate_gnb_lpml(struct pp_hwmgr *hwmgr) + static int tonga_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr) + { + struct tonga_smumgr *smu_data = +- (struct tonga_smumgr *)(hwmgr->smumgr->backend); ++ (struct tonga_smumgr *)(hwmgr->smu_backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + uint16_t hi_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd; +@@ -1982,7 +1982,7 @@ static int tonga_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr) + static int tonga_populate_pm_fuses(struct pp_hwmgr *hwmgr) + { + struct tonga_smumgr *smu_data = +- (struct tonga_smumgr *)(hwmgr->smumgr->backend); ++ (struct tonga_smumgr *)(hwmgr->smu_backend); + uint32_t pm_fuse_table_offset; + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, +@@ -2051,7 +2051,7 @@ static int tonga_populate_pm_fuses(struct pp_hwmgr *hwmgr) + static int tonga_populate_mc_reg_address(struct pp_hwmgr *hwmgr, + SMU72_Discrete_MCRegisters *mc_reg_table) + { +- const struct tonga_smumgr *smu_data = (struct tonga_smumgr *)hwmgr->smumgr->backend; ++ const struct tonga_smumgr *smu_data = (struct tonga_smumgr *)hwmgr->smu_backend; + + uint32_t i, j; + +@@ -2097,7 +2097,7 @@ static int tonga_convert_mc_reg_table_entry_to_smc( + SMU72_Discrete_MCRegisterSet *mc_reg_table_data + ) + { +- struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend); ++ struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend); + uint32_t i = 0; + + for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) { +@@ -2141,7 +2141,7 @@ static int tonga_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr, + + static int tonga_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr) + { +- struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend); ++ struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend); + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + uint32_t address; + int32_t result; +@@ -2172,7 +2172,7 @@ static int tonga_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr) + static int tonga_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr) + { + int result; +- struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend); ++ struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend); + + memset(&smu_data->mc_regs, 0x00, sizeof(SMU72_Discrete_MCRegisters)); + result = tonga_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs)); +@@ -2191,7 +2191,7 @@ static int tonga_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr) + + static void tonga_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) + { +- struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend); ++ struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + +@@ -2207,7 +2207,7 @@ static void tonga_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) + + static void tonga_save_default_power_profile(struct pp_hwmgr *hwmgr) + { +- struct tonga_smumgr *data = (struct tonga_smumgr *)(hwmgr->smumgr->backend); ++ struct tonga_smumgr *data = (struct tonga_smumgr *)(hwmgr->smu_backend); + struct SMU72_Discrete_GraphicsLevel *levels = + data->smc_state_table.GraphicsLevel; + unsigned min_level = 1; +@@ -2253,7 +2253,7 @@ int tonga_init_smc_table(struct pp_hwmgr *hwmgr) + int result; + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + struct tonga_smumgr *smu_data = +- (struct tonga_smumgr *)(hwmgr->smumgr->backend); ++ (struct tonga_smumgr *)(hwmgr->smu_backend); + SMU72_Discrete_DpmTable *table = &(smu_data->smc_state_table); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); +@@ -2507,7 +2507,7 @@ int tonga_init_smc_table(struct pp_hwmgr *hwmgr) + int tonga_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) + { + struct tonga_smumgr *smu_data = +- (struct tonga_smumgr *)(hwmgr->smumgr->backend); ++ (struct tonga_smumgr *)(hwmgr->smu_backend); + SMU72_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE }; + uint32_t duty100; + uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2; +@@ -2611,7 +2611,7 @@ int tonga_update_sclk_threshold(struct pp_hwmgr *hwmgr) + { + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + struct tonga_smumgr *smu_data = +- (struct tonga_smumgr *)(hwmgr->smumgr->backend); ++ (struct tonga_smumgr *)(hwmgr->smu_backend); + + int result = 0; + uint32_t low_sclk_interrupt_threshold = 0; +@@ -2714,7 +2714,7 @@ uint32_t tonga_get_mac_definition(uint32_t value) + static int tonga_update_uvd_smc_table(struct pp_hwmgr *hwmgr) + { + struct tonga_smumgr *smu_data = +- (struct tonga_smumgr *)(hwmgr->smumgr->backend); ++ (struct tonga_smumgr *)(hwmgr->smu_backend); + uint32_t mm_boot_level_offset, mm_boot_level_value; + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); +@@ -2748,7 +2748,7 @@ static int tonga_update_uvd_smc_table(struct pp_hwmgr *hwmgr) + static int tonga_update_vce_smc_table(struct pp_hwmgr *hwmgr) + { + struct tonga_smumgr *smu_data = +- (struct tonga_smumgr *)(hwmgr->smumgr->backend); ++ (struct tonga_smumgr *)(hwmgr->smu_backend); + uint32_t mm_boot_level_offset, mm_boot_level_value; + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); +@@ -2778,7 +2778,7 @@ static int tonga_update_vce_smc_table(struct pp_hwmgr *hwmgr) + + static int tonga_update_samu_smc_table(struct pp_hwmgr *hwmgr) + { +- struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend); ++ struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend); + uint32_t mm_boot_level_offset, mm_boot_level_value; + + smu_data->smc_state_table.SamuBootLevel = 0; +@@ -2830,7 +2830,7 @@ int tonga_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type) + int tonga_process_firmware_header(struct pp_hwmgr *hwmgr) + { + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); +- struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend); ++ struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend); + + uint32_t tmp; + int result; +@@ -3156,7 +3156,7 @@ static int tonga_set_valid_flag(struct tonga_mc_reg_table *table) + int tonga_initialize_mc_reg_table(struct pp_hwmgr *hwmgr) + { + int result; +- struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend); ++ struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend); + pp_atomctrl_mc_reg_table *table; + struct tonga_mc_reg_table *ni_table = &smu_data->mc_reg_table; + uint8_t module_index = tonga_get_memory_modile_index(hwmgr); +@@ -3239,7 +3239,7 @@ int tonga_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr, + struct amd_pp_profile *request) + { + struct tonga_smumgr *smu_data = (struct tonga_smumgr *) +- (hwmgr->smumgr->backend); ++ (hwmgr->smu_backend); + struct SMU72_Discrete_GraphicsLevel *levels = + smu_data->smc_state_table.GraphicsLevel; + uint32_t array = smu_data->smu7_data.dpm_table_start + +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c +index c10e6f8..105cb2a 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c +@@ -176,7 +176,7 @@ static int tonga_smu_init(struct pp_hwmgr *hwmgr) + if (tonga_priv == NULL) + return -ENOMEM; + +- hwmgr->smumgr->backend = tonga_priv; ++ hwmgr->smu_backend = tonga_priv; + + if (smu7_init(hwmgr)) + return -EINVAL; +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c +index c631270..4cb5d34 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c +@@ -224,7 +224,7 @@ int vega10_copy_table_from_smc(struct pp_hwmgr *hwmgr, + uint8_t *table, int16_t table_id) + { + struct vega10_smumgr *priv = +- (struct vega10_smumgr *)(hwmgr->smumgr->backend); ++ (struct vega10_smumgr *)(hwmgr->smu_backend); + + PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE, + "Invalid SMU Table ID!", return -EINVAL); +@@ -262,7 +262,7 @@ int vega10_copy_table_to_smc(struct pp_hwmgr *hwmgr, + uint8_t *table, int16_t table_id) + { + struct vega10_smumgr *priv = +- (struct vega10_smumgr *)(hwmgr->smumgr->backend); ++ (struct vega10_smumgr *)(hwmgr->smu_backend); + + PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE, + "Invalid SMU Table ID!", return -EINVAL); +@@ -339,7 +339,7 @@ int vega10_get_smc_features(struct pp_hwmgr *hwmgr, + int vega10_set_tools_address(struct pp_hwmgr *hwmgr) + { + struct vega10_smumgr *priv = +- (struct vega10_smumgr *)(hwmgr->smumgr->backend); ++ (struct vega10_smumgr *)(hwmgr->smu_backend); + + if (priv->smu_tables.entry[TOOLSTABLE].table_addr_high || + priv->smu_tables.entry[TOOLSTABLE].table_addr_low) { +@@ -412,7 +412,7 @@ static int vega10_smu_init(struct pp_hwmgr *hwmgr) + if (!priv) + return -ENOMEM; + +- hwmgr->smumgr->backend = priv; ++ hwmgr->smu_backend = priv; + + /* allocate space for pptable */ + smu_allocate_memory(hwmgr->device, +@@ -425,7 +425,7 @@ static int vega10_smu_init(struct pp_hwmgr *hwmgr) + + PP_ASSERT_WITH_CODE(kaddr, + "[vega10_smu_init] Out of memory for pptable.", +- kfree(hwmgr->smumgr->backend); ++ kfree(hwmgr->smu_backend); + cgs_free_gpu_mem(hwmgr->device, + (cgs_handle_t)handle); + return -EINVAL); +@@ -451,7 +451,7 @@ static int vega10_smu_init(struct pp_hwmgr *hwmgr) + + PP_ASSERT_WITH_CODE(kaddr, + "[vega10_smu_init] Out of memory for wmtable.", +- kfree(hwmgr->smumgr->backend); ++ kfree(hwmgr->smu_backend); + cgs_free_gpu_mem(hwmgr->device, + (cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle); + cgs_free_gpu_mem(hwmgr->device, +@@ -479,7 +479,7 @@ static int vega10_smu_init(struct pp_hwmgr *hwmgr) + + PP_ASSERT_WITH_CODE(kaddr, + "[vega10_smu_init] Out of memory for avfs table.", +- kfree(hwmgr->smumgr->backend); ++ kfree(hwmgr->smu_backend); + cgs_free_gpu_mem(hwmgr->device, + (cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle); + cgs_free_gpu_mem(hwmgr->device, +@@ -532,7 +532,7 @@ static int vega10_smu_init(struct pp_hwmgr *hwmgr) + + PP_ASSERT_WITH_CODE(kaddr, + "[vega10_smu_init] Out of memory for avfs fuse table.", +- kfree(hwmgr->smumgr->backend); ++ kfree(hwmgr->smu_backend); + cgs_free_gpu_mem(hwmgr->device, + (cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle); + cgs_free_gpu_mem(hwmgr->device, +@@ -561,7 +561,7 @@ static int vega10_smu_init(struct pp_hwmgr *hwmgr) + static int vega10_smu_fini(struct pp_hwmgr *hwmgr) + { + struct vega10_smumgr *priv = +- (struct vega10_smumgr *)(hwmgr->smumgr->backend); ++ (struct vega10_smumgr *)(hwmgr->smu_backend); + + if (priv) { + cgs_free_gpu_mem(hwmgr->device, +@@ -575,8 +575,8 @@ static int vega10_smu_fini(struct pp_hwmgr *hwmgr) + (cgs_handle_t)priv->smu_tables.entry[TOOLSTABLE].handle); + cgs_free_gpu_mem(hwmgr->device, + (cgs_handle_t)priv->smu_tables.entry[AVFSFUSETABLE].handle); +- kfree(hwmgr->smumgr->backend); +- hwmgr->smumgr->backend = NULL; ++ kfree(hwmgr->smu_backend); ++ hwmgr->smu_backend = NULL; + } + return 0; + } +-- +2.7.4 + |