diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1847-drm-amdgpu-hdp-flush-should-be-put-it-initialized.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1847-drm-amdgpu-hdp-flush-should-be-put-it-initialized.patch | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1847-drm-amdgpu-hdp-flush-should-be-put-it-initialized.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1847-drm-amdgpu-hdp-flush-should-be-put-it-initialized.patch new file mode 100644 index 00000000..85e5e6af --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1847-drm-amdgpu-hdp-flush-should-be-put-it-initialized.patch @@ -0,0 +1,48 @@ +From 0eadc2a0d6c1213c64545e91d1d3aeba12a40b35 Mon Sep 17 00:00:00 2001 +From: Monk Liu <Monk.Liu@amd.com> +Date: Fri, 15 Sep 2017 15:03:24 +0800 +Subject: [PATCH 1847/4131] drm/amdgpu:hdp flush should be put it initialized +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Change-Id: I635271ba4c89189017daa302a7fe5cd65c3eef06 +Signed-off-by: Monk Liu <Monk.Liu@amd.com> +Acked-by: Christian König <christian.koenig@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +index 6f03a9e..c246f2a 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +@@ -708,12 +708,6 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) + if (r) + return r; + +- /* After HDP is initialized, flush HDP.*/ +- if (adev->flags & AMD_IS_APU) +- nbio_v7_0_hdp_flush(adev); +- else +- nbio_v6_1_hdp_flush(adev); +- + switch (adev->asic_type) { + case CHIP_RAVEN: + mmhub_v1_0_initialize_power_gating(adev); +@@ -736,6 +730,12 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) + tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL); + WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp); + ++ /* After HDP is initialized, flush HDP.*/ ++ if (adev->flags & AMD_IS_APU) ++ nbio_v7_0_hdp_flush(adev); ++ else ++ nbio_v6_1_hdp_flush(adev); ++ + if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) + value = false; + else +-- +2.7.4 + |