diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1846-drm-amdgpu-insert-TMZ_BEGIN.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1846-drm-amdgpu-insert-TMZ_BEGIN.patch | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1846-drm-amdgpu-insert-TMZ_BEGIN.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1846-drm-amdgpu-insert-TMZ_BEGIN.patch new file mode 100644 index 00000000..5a952bb8 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1846-drm-amdgpu-insert-TMZ_BEGIN.patch @@ -0,0 +1,60 @@ +From 71704d4f117190104d1f23dedf8ca6ffcbf278e0 Mon Sep 17 00:00:00 2001 +From: Monk Liu <Monk.Liu@amd.com> +Date: Fri, 9 Jun 2017 15:04:49 +0800 +Subject: [PATCH 1846/4131] drm/amdgpu:insert TMZ_BEGIN +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +FRAME_CONTROL(begin) is needed for vega10 due to ucode logic change, +it can fix some CTS random fail under gfx preemption enabled mode. + +Change-Id: I0442337f6cde13ed2a33f033badcb522e0f35e2d +Signed-off-by: Monk Liu <Monk.Liu@amd.com> +Acked-by: Christian König <christian.koenig@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 14 ++++++++------ + 1 file changed, 8 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +index 2a3fad0..f90415a 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -3770,6 +3770,12 @@ static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring) + amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2); + } + ++static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start) ++{ ++ amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); ++ amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */ ++} ++ + static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) + { + uint32_t dw2 = 0; +@@ -3777,6 +3783,8 @@ static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) + if (amdgpu_sriov_vf(ring->adev)) + gfx_v9_0_ring_emit_ce_meta(ring); + ++ gfx_v9_0_ring_emit_tmz(ring, true); ++ + dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ + if (flags & AMDGPU_HAVE_CTX_SWITCH) { + /* set load_global_config & load_global_uconfig */ +@@ -3827,12 +3835,6 @@ static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigne + ring->ring[offset] = (ring->ring_size>>2) - offset + cur; + } + +-static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start) +-{ +- amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); +- amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */ +-} +- + static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg) + { + struct amdgpu_device *adev = ring->adev; +-- +2.7.4 + |