diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1831-drm-amdgpu-sdma3-Enable-sdma-wptr-polling-for-SRIOV.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1831-drm-amdgpu-sdma3-Enable-sdma-wptr-polling-for-SRIOV.patch | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1831-drm-amdgpu-sdma3-Enable-sdma-wptr-polling-for-SRIOV.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1831-drm-amdgpu-sdma3-Enable-sdma-wptr-polling-for-SRIOV.patch new file mode 100644 index 00000000..2cdface2 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1831-drm-amdgpu-sdma3-Enable-sdma-wptr-polling-for-SRIOV.patch @@ -0,0 +1,56 @@ +From 4ea7a70bf470977698ce08301fbca332bbd0125a Mon Sep 17 00:00:00 2001 +From: "Xiangliang.Yu" <Xiangliang.Yu@amd.com> +Date: Tue, 12 Sep 2017 17:31:46 +0800 +Subject: [PATCH 1831/4131] drm/amdgpu/sdma3: Enable sdma wptr polling for + SRIOV + +When hypervisor triggering FLR for one of VFs, need to enable sdma +wptr polling to avoid missing wptr update if enabling doorbell. + +Signed-off-by: Xiangliang.Yu <Xiangliang.Yu@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 17 ++++++++++++++++- + 1 file changed, 16 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +index eaa6239..7b97ce8 100644 +--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +@@ -641,10 +641,11 @@ static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable) + static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) + { + struct amdgpu_ring *ring; +- u32 rb_cntl, ib_cntl; ++ u32 rb_cntl, ib_cntl, wptr_poll_cntl; + u32 rb_bufsz; + u32 wb_offset; + u32 doorbell; ++ u64 wptr_gpu_addr; + int i, j, r; + + for (i = 0; i < adev->sdma.num_instances; i++) { +@@ -707,6 +708,20 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) + } + WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell); + ++ /* setup the wptr shadow polling */ ++ wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); ++ ++ WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i], ++ lower_32_bits(wptr_gpu_addr)); ++ WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i], ++ upper_32_bits(wptr_gpu_addr)); ++ wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]); ++ if (amdgpu_sriov_vf(adev)) ++ wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1); ++ else ++ wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 0); ++ WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl); ++ + /* enable DMA RB */ + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); + WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); +-- +2.7.4 + |