summaryrefslogtreecommitdiffstats
path: root/drivers/pinctrl/mvebu/pinctrl-orion.c
blob: 29bb9d8cbbb5bafc9a4288cc3a3af00920a35a3c (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Marvell Orion pinctrl driver based on mvebu pinctrl core
 *
 * Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * The first 16 MPP pins on Orion are easy to handle: they are
 * configured through 2 consecutive registers, located at the base
 * address of the MPP device.
 *
 * However the last 4 MPP pins are handled by a register at offset
 * 0x50 from the base address, so it is not consecutive with the first
 * two registers.
 */

#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>

#include "pinctrl-mvebu.h"

static void __iomem *mpp_base;
static void __iomem *high_mpp_base;

static int orion_mpp_ctrl_get(struct mvebu_mpp_ctrl_data *data,
			      unsigned pid, unsigned long *config)
{
	unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;

	if (pid < 16) {
		unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
		*config = (readl(mpp_base + off) >> shift) & MVEBU_MPP_MASK;
	}
	else {
		*config = (readl(high_mpp_base) >> shift) & MVEBU_MPP_MASK;
	}

	return 0;
}

static int orion_mpp_ctrl_set(struct mvebu_mpp_ctrl_data *data,
			      unsigned pid, unsigned long config)
{
	unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;

	if (pid < 16) {
		unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
		u32 reg = readl(mpp_base + off) & ~(MVEBU_MPP_MASK << shift);
		writel(reg | (config << shift), mpp_base + off);
	}
	else {
		u32 reg = readl(high_mpp_base) & ~(MVEBU_MPP_MASK << shift);
		writel(reg | (config << shift), high_mpp_base);
	}

	return 0;
}

#define V(f5181, f5182, f5281) \
	((f5181 << 0) | (f5182 << 1) | (f5281 << 2))

enum orion_variant {
	V_5181  = V(1, 0, 0),
	V_5182  = V(0, 1, 0),
	V_5281  = V(0, 0, 1),
	V_ALL   = V(1, 1, 1),
};

static struct mvebu_mpp_mode orion_mpp_modes[] = {
	MPP_MODE(0,
		 MPP_VAR_FUNCTION(0x0, "pcie", "rstout",    V_ALL),
		 MPP_VAR_FUNCTION(0x2, "pci", "req2",       V_ALL),
		 MPP_VAR_FUNCTION(0x3, "gpio", NULL,        V_ALL)),
	MPP_MODE(1,
		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
		 MPP_VAR_FUNCTION(0x2, "pci", "gnt2",       V_ALL)),
	MPP_MODE(2,
		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
		 MPP_VAR_FUNCTION(0x2, "pci", "req3",       V_ALL),
		 MPP_VAR_FUNCTION(0x3, "pci-1", "pme",      V_ALL)),
	MPP_MODE(3,
		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
		 MPP_VAR_FUNCTION(0x2, "pci", "gnt3",       V_ALL)),
	MPP_MODE(4,
		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
		 MPP_VAR_FUNCTION(0x2, "pci", "req4",       V_ALL),
		 MPP_VAR_FUNCTION(0x4, "bootnand", "re",    V_5182 | V_5281),
		 MPP_VAR_FUNCTION(0x5, "sata0", "prsnt",    V_5182)),
	MPP_MODE(5,
		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
		 MPP_VAR_FUNCTION(0x2, "pci", "gnt4",       V_ALL),
		 MPP_VAR_FUNCTION(0x4, "bootnand", "we",    V_5182 | V_5281),
		 MPP_VAR_FUNCTION(0x5, "sata1", "prsnt",    V_5182)),
	MPP_MODE(6,
		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
		 MPP_VAR_FUNCTION(0x2, "pci", "req5",       V_ALL),
		 MPP_VAR_FUNCTION(0x4, "nand", "re0",       V_5182 | V_5281),
		 MPP_VAR_FUNCTION(0x5, "pci-1", "clk",      V_5181),
		 MPP_VAR_FUNCTION(0x5, "sata0", "act",      V_5182)),
	MPP_MODE(7,
		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
		 MPP_VAR_FUNCTION(0x2, "pci", "gnt5",       V_ALL),
		 MPP_VAR_FUNCTION(0x4, "nand", "we0",       V_5182 | V_5281),
		 MPP_VAR_FUNCTION(0x5, "pci-1", "clk",      V_5181),
		 MPP_VAR_FUNCTION(0x5, "sata1", "act",      V_5182)),
	MPP_MODE(8,
		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
		 MPP_VAR_FUNCTION(0x1, "ge", "col",         V_ALL)),
	MPP_MODE(9,
		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
		 MPP_VAR_FUNCTION(0x1, "ge", "rxerr",       V_ALL)),
	MPP_MODE(10,
		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
		 MPP_VAR_FUNCTION(0x1, "ge", "crs",         V_ALL)),
	MPP_MODE(11,
		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
		 MPP_VAR_FUNCTION(0x1, "ge", "txerr",       V_ALL)),
	MPP_MODE(12,
		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
		 MPP_VAR_FUNCTION(0x1, "ge", "txd4",        V_ALL),
		 MPP_VAR_FUNCTION(0x4, "nand", "re1",       V_5182 | V_5281),
		 MPP_VAR_FUNCTION(0x5, "sata0", "ledprsnt", V_5182)),
	MPP_MODE(13,
		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
		 MPP_VAR_FUNCTION(0x1, "ge", "txd5",        V_ALL),
		 MPP_VAR_FUNCTION(0x4, "nand", "we1",       V_5182 | V_5281),
		 MPP_VAR_FUNCTION(0x5, "sata1", "ledprsnt", V_5182)),
	MPP_MODE(14,
		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
		 MPP_VAR_FUNCTION(0x1, "ge", "txd6",        V_ALL),
		 MPP_VAR_FUNCTION(0x4, "nand", "re2",       V_5182 | V_5281),
		 MPP_VAR_FUNCTION(0x5, "sata0", "ledact",   V_5182)),
	MPP_MODE(15,
		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
		 MPP_VAR_FUNCTION(0x1, "ge", "txd7",        V_ALL),
		 MPP_VAR_FUNCTION(0x4, "nand", "we2",       V_5182 | V_5281),
		 MPP_VAR_FUNCTION(0x5, "sata1", "ledact",   V_5182)),
	MPP_MODE(16,
		 MPP_VAR_FUNCTION(0x0, "uart1", "rxd",      V_5182 | V_5281),
		 MPP_VAR_FUNCTION(0x1, "ge", "rxd4",        V_ALL),
		 MPP_VAR_FUNCTION(0x5, "gpio", NULL,        V_5182)),
	MPP_MODE(17,
		 MPP_VAR_FUNCTION(0x0, "uart1", "txd",      V_5182 | V_5281),
		 MPP_VAR_FUNCTION(0x1, "ge", "rxd5",        V_ALL),
		 MPP_VAR_FUNCTION(0x5, "gpio", NULL,        V_5182)),
	MPP_MODE(18,
		 MPP_VAR_FUNCTION(0x0, "uart1", "cts",      V_5182 | V_5281),
		 MPP_VAR_FUNCTION(0x1, "ge", "rxd6",        V_ALL),
		 MPP_VAR_FUNCTION(0x5, "gpio", NULL,        V_5182)),
	MPP_MODE(19,
		 MPP_VAR_FUNCTION(0x0, "uart1", "rts",      V_5182 | V_5281),
		 MPP_VAR_FUNCTION(0x1, "ge", "rxd7",        V_ALL),
		 MPP_VAR_FUNCTION(0x5, "gpio", NULL,        V_5182)),
};

static const struct mvebu_mpp_ctrl orion_mpp_controls[] = {
	MPP_FUNC_CTRL(0, 19, NULL, orion_mpp_ctrl),
};

static struct pinctrl_gpio_range mv88f5181_gpio_ranges[] = {
	MPP_GPIO_RANGE(0, 0, 0, 16),
};

static struct pinctrl_gpio_range mv88f5182_gpio_ranges[] = {
	MPP_GPIO_RANGE(0, 0, 0, 19),
};

static struct pinctrl_gpio_range mv88f5281_gpio_ranges[] = {
	MPP_GPIO_RANGE(0, 0, 0, 16),
};

static struct mvebu_pinctrl_soc_info mv88f5181_info = {
	.variant = V_5181,
	.controls = orion_mpp_controls,
	.ncontrols = ARRAY_SIZE(orion_mpp_controls),
	.modes = orion_mpp_modes,
	.nmodes = ARRAY_SIZE(orion_mpp_modes),
	.gpioranges = mv88f5181_gpio_ranges,
	.ngpioranges = ARRAY_SIZE(mv88f5181_gpio_ranges),
};

static struct mvebu_pinctrl_soc_info mv88f5182_info = {
	.variant = V_5182,
	.controls = orion_mpp_controls,
	.ncontrols = ARRAY_SIZE(orion_mpp_controls),
	.modes = orion_mpp_modes,
	.nmodes = ARRAY_SIZE(orion_mpp_modes),
	.gpioranges = mv88f5182_gpio_ranges,
	.ngpioranges = ARRAY_SIZE(mv88f5182_gpio_ranges),
};

static struct mvebu_pinctrl_soc_info mv88f5281_info = {
	.variant = V_5281,
	.controls = orion_mpp_controls,
	.ncontrols = ARRAY_SIZE(orion_mpp_controls),
	.modes = orion_mpp_modes,
	.nmodes = ARRAY_SIZE(orion_mpp_modes),
	.gpioranges = mv88f5281_gpio_ranges,
	.ngpioranges = ARRAY_SIZE(mv88f5281_gpio_ranges),
};

/*
 * There are multiple variants of the Orion SoCs, but in terms of pin
 * muxing, they are identical.
 */
static const struct of_device_id orion_pinctrl_of_match[] = {
	{ .compatible = "marvell,88f5181-pinctrl", .data = &mv88f5181_info },
	{ .compatible = "marvell,88f5181l-pinctrl", .data = &mv88f5181_info },
	{ .compatible = "marvell,88f5182-pinctrl", .data = &mv88f5182_info },
	{ .compatible = "marvell,88f5281-pinctrl", .data = &mv88f5281_info },
	{ }
};

static int orion_pinctrl_probe(struct platform_device *pdev)
{
	const struct of_device_id *match =
		of_match_device(orion_pinctrl_of_match, &pdev->dev);
	struct resource *res;

	pdev->dev.platform_data = (void*)match->data;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	mpp_base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(mpp_base))
		return PTR_ERR(mpp_base);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	high_mpp_base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(high_mpp_base))
		return PTR_ERR(high_mpp_base);

	return mvebu_pinctrl_probe(pdev);
}

static struct platform_driver orion_pinctrl_driver = {
	.driver = {
		.name = "orion-pinctrl",
		.of_match_table = of_match_ptr(orion_pinctrl_of_match),
	},
	.probe = orion_pinctrl_probe,
};
builtin_platform_driver(orion_pinctrl_driver);