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path: root/drivers/clk
AgeCommit message (Expand)Author
2021-08-12clk: fix leak on devm_clk_bulk_get_all() unwindBrian Norris
2021-08-12clk: stm32f4: fix post divisor setup for I2S/SAI PLLsDario Binacchi
2021-07-19clk: tegra: Ensure that PLLU configuration is applied properlyDmitry Osipenko
2021-07-19clk: renesas: r8a77995: Add ZA2 clockKuninori Morimoto
2021-07-14clk: si5341: Update initialization magicRobert Hancock
2021-07-14clk: si5341: Avoid divide errors due to bogus register contentsRobert Hancock
2021-07-14clk: actions: Fix bisp_factor_table based clocks on Owl S500 SoCCristian Ciocaltea
2021-07-14clk: actions: Fix SD clocks factor table on Owl S500 SoCCristian Ciocaltea
2021-07-14clk: actions: Fix UART clock dividers on Owl S500 SoCCristian Ciocaltea
2021-07-14clk: meson: g12a: fix gp0 and hifi rangesJerome Brunet
2021-06-23clocksource/drivers/timer-ti-dm: Handle dra7 timer wrap errata i940Tony Lindgren
2021-05-19clk: exynos7: Mark aclk_fsys1_200 as criticalPaweł Chmiel
2021-05-14clk: uniphier: Fix potential infinite loopColin Ian King
2021-05-14clk: qcom: a53-pll: Add missing MODULE_DEVICE_TABLEChen Hui
2021-05-14clk: zynqmp: move zynqmp_pll_set_mode out of round_rate callbackQuanyang Wang
2021-05-14media: aspeed: fix clock handling logicJae Hyun Yoo
2021-05-14clk: mvebu: armada-37xx-periph: Fix workaround for switching from L1 to L0Pali Rohár
2021-05-14clk: mvebu: armada-37xx-periph: Fix switching CPU freq from 250 Mhz to 1 GHzPali Rohár
2021-05-14clk: mvebu: armada-37xx-periph: remove .set_parent method for CPU PM clockMarek Behún
2021-05-11clk: socfpga: arria10: Fix memory leak of socfpga_clk on error returnColin Ian King
2021-04-14clk: socfpga: fix iomem pointer cast on 64-bitKrzysztof Kozlowski
2021-04-14clk: fix invalid usage of list cursor in unregisterLukasz Bartosik
2021-04-14clk: fix invalid usage of list cursor in registerLukasz Bartosik
2021-03-04clk: aspeed: Fix APLL calculate formula from ast2600-A2Ryan Chen
2021-03-04clk: qcom: gcc-msm8998: Fix Alpha PLL type for all GPLLsAngeloGioacchino Del Regno
2021-03-04clk: sunxi-ng: h6: Fix clock divider range on some clocksAndre Przywara
2021-03-04clk: sunxi-ng: h6: Fix CEC clockAndre Przywara
2021-03-04clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate()Martin Blumenstingl
2021-03-04clk: meson: clk-pll: make "ret" a signed integerMartin Blumenstingl
2021-03-04clk: meson: clk-pll: fix initializing the old rate (fallback) for a PLLMartin Blumenstingl
2021-02-17clk: sunxi-ng: mp: fix parent rate change flag checkJernej Skrabec
2021-01-27clk: tegra30: Add hda clock default rates to clock driverPeter Geis
2020-12-30clk: tegra: Do not return 0 on failureNicolin Chen
2020-12-30clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9Terry Zhou
2020-12-30clk: ingenic: Fix divider calculation with div tablesPaul Cercueil
2020-12-30clk: sunxi-ng: Make sure divider tables have sentinelJernej Skrabec
2020-12-30clk: s2mps11: Fix a resource leak in error handling paths in the probe functionChristophe JAILLET
2020-12-30clk: at91: sam9x60: remove atmel,osc-bypass supportAlexandre Belloni
2020-12-30clk: ti: Fix memleak in ti_fapll_synth_setupZhang Qilong
2020-12-30clk: tegra: Fix duplicated SE clock entryDmitry Osipenko
2020-12-30clk: meson: Kconfig: fix dependency for G12AKevin Hilman
2020-12-30clk: renesas: r9a06g032: Drop __packed for portabilityGeert Uytterhoeven
2020-11-05clk: ti: clockdomain: fix static checker warningTero Kristo
2020-10-29clk: imx8mq: Fix usdhc parents orderAbel Vesa
2020-10-29clk: bcm2835: add missing release if devm_clk_hw_register failsNavid Emamdoost
2020-10-29clk: at91: clk-main: update key before writing AT91_CKGR_MORClaudiu Beznea
2020-10-29clk: mediatek: add UART0 clock supportHanks Chen
2020-10-29clk: rockchip: Initialize hw to error to avoid undefined behaviorStephen Boyd
2020-10-29clk: keystone: sci-clk: fix parsing assigned-clock data during probeTero Kristo
2020-10-29clk: qcom: gcc-sdm660: Fix wrong parent_mapKonrad Dybcio