summaryrefslogtreecommitdiffstats
path: root/drivers/clk
AgeCommit message (Expand)Author
2020-09-04clk: scmi: Fix min and max rate when registering clocks with discrete ratesSudeep Holla
2020-09-04clk: qcom: clk-rpmh: Wait for completion when enabling clocksMike Tipton
2020-07-16clk: sifive: allocate sufficient memory for struct __prci_dataVincent Chen
2020-07-13clk: sprd: return correct type of value for _sprd_pll_recalc_rateChunyan Zhang
2020-07-13clk: bcm2835: Fix return type of bcm2835_register_gateNathan Chancellor
2020-07-13clk: samsung: exynos5433: Add IGNORE_UNUSED flag to sclk_i2s1Marek Szyprowski
2020-07-13clk: ti: composite: fix memory leakTero Kristo
2020-07-13clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registersMartin Blumenstingl
2020-07-13clk: meson: meson8b: Fix the vclk_div{1, 2, 4, 6, 12}_en gate bitsMartin Blumenstingl
2020-07-13clk: meson: meson8b: Fix the polarity of the RESET_N linesMartin Blumenstingl
2020-07-13clk: clk-flexgen: fix clock-critical handlingAlain Volmat
2020-07-13clk: zynqmp: fix memory leak in zynqmp_register_clocksQuanyang Wang
2020-07-13clk: renesas: cpg-mssr: Fix STBCR suspend/resume handlingGeert Uytterhoeven
2020-07-13clk: samsung: Mark top ISP and CAM clocks on Exynos542x as criticalMarek Szyprowski
2020-07-13clk: qcom: msm8916: Fix the address location of pll->config_regBryan O'Donoghue
2020-07-13clk: sunxi: Fix incorrect usage of round_down()Rikard Falkeborn
2020-07-11clk: mediatek: assign the initial value to clk_init_data of mtk_muxWeiyi Lu
2020-07-07clk: qcom: fix QCS404 TuringCC regmapJorge Ramirez-Ortiz
2020-07-07PM: runtime: clk: Fix clk_pm_runtime_get() error pathRafael J. Wysocki
2020-06-08clk: ti: am33xx: fix RTC clock parentTero Kristo
2020-06-08clk: rockchip: fix incorrect configuration of rk3228 aclk_gpu* clocksJustin Swartz
2020-06-01clk: tegra: Fix Tegra PMC clock out parentsSowjanya Komatineni
2020-06-01clk: at91: usb: continue if clk_hw_round_rate() return zeroClaudiu Beznea
2020-06-01clk: Don't cache errors from clk_ops::get_phase()Stephen Boyd
2020-06-01clk: at91: usb: use proper usbs_maskClaudiu Beznea
2020-06-01clk: at91: sam9x60: fix usb clock parentsClaudiu Beznea
2020-06-01clk: ingenic/jz4770: Exit with error if CGU init failedPaul Cercueil
2020-06-01clk: ti: am43xx: Fix clock parent for RTC clockTony Lindgren
2020-06-01clk: imx: Align imx sc clock parent msg structs to 4Leonard Crestez
2020-06-01clk: imx: Align imx sc clock msg structs to 4Leonard Crestez
2020-05-15clk: Unlink clock if failed to prepare or enableMarc Zyngier
2020-05-15clk: uniphier: Add SCSSI clock gate for each channelKunihiko Hayashi
2020-05-15clk: Use parent node pointer during registration if necessaryStephen Boyd
2020-05-15clk: sunxi-ng: add mux and pll notifiers for A64 CPU clockIcenowy Zheng
2020-05-15clk: actually call the clock init before any other callback of the clockJerome Brunet
2020-05-15clk: renesas: rcar-gen3: Allow changing the RPC[D2] clocksSergei Shtylyov
2020-05-15clk: qcom: smd: Add missing bimc clockJeffrey Hugo
2020-05-15clk: qcom: rcg2: Don't crash if our parent can't be found; return an errorDouglas Anderson
2020-05-15clk: qcom: Don't overwrite 'cfg' in clk_rcg2_dfs_populate_freq()Stephen Boyd
2020-05-15clk: ti: dra7: fix parent for gmac_clkctrlGrygorii Strashko
2020-05-15clk: meson: meson8b: make the CCF use the glitch-free mali muxMartin Blumenstingl
2020-05-15clk: at91: sam9x60: fix programmable clock prescalerEugen Hristev
2020-05-15clk: meson: pll: Fix by 0 division in __pll_params_to_rate()Remi Pommarel
2020-05-04clk: meson: g12a: fix missing uart2 in regmap tableJerome Brunet
2020-05-04clk: tegra: Mark fuse clock as criticalStephen Warren
2020-04-16clk: mmp2: Fix the order of timer mux parentsLubomir Rintel
2020-04-16clk: sunxi-ng: h6-r: Fix AR100/R_APB2 parent orderSamuel Holland
2020-04-12clk: imx7ulp: Correct DDR clock mux optionsAnson Huang
2020-04-12clk: imx7ulp: Correct system clock source option #7Anson Huang
2020-04-12clk: sprd: Use IS_ERR() to validate the return value of syscon_regmap_lookup_...Baolin Wang