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path: root/drivers/clk
AgeCommit message (Expand)Author
2020-12-30clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9Terry Zhou
2020-12-30clk: sunxi-ng: Make sure divider tables have sentinelJernej Skrabec
2020-12-30clk: s2mps11: Fix a resource leak in error handling paths in the probe functionChristophe JAILLET
2020-12-30clk: ti: Fix memleak in ti_fapll_synth_setupZhang Qilong
2020-12-30clk: tegra: Fix duplicated SE clock entryDmitry Osipenko
2020-12-30clk: renesas: r9a06g032: Drop __packed for portabilityGeert Uytterhoeven
2020-11-05clk: ti: clockdomain: fix static checker warningTero Kristo
2020-10-30clk: bcm2835: add missing release if devm_clk_hw_register failsNavid Emamdoost
2020-10-30clk: at91: clk-main: update key before writing AT91_CKGR_MORClaudiu Beznea
2020-10-30clk: rockchip: Initialize hw to error to avoid undefined behaviorStephen Boyd
2020-10-07clk: samsung: exynos4: mark 'chipid' clock as CLK_IGNORE_UNUSEDMarek Szyprowski
2020-10-07clk: socfpga: stratix10: fix the divider for the emac_ptp_free_clkDinh Nguyen
2020-10-01clk: stratix10: use do_div() for 64-bit calculationDinh Nguyen
2020-10-01clk/ti/adpll: allocate room for terminating nullStephen Kitt
2020-09-23clk: rockchip: Fix initialization of mux_pll_src_4plls_pNathan Chancellor
2020-09-23clk: davinci: Use the correct size when allocating memoryChristophe JAILLET
2020-08-26clk: Evict unregistered clks from parent cachesStephen Boyd
2020-08-21clk: clk-atlas6: fix return value check in atlas6_clk_init()Xu Wang
2020-08-19clk: scmi: Fix min and max rate when registering clocks with discrete ratesSudeep Holla
2020-06-25clk: sprd: return correct type of value for _sprd_pll_recalc_rateChunyan Zhang
2020-06-25clk: bcm2835: Fix return type of bcm2835_register_gateNathan Chancellor
2020-06-25clk: samsung: exynos5433: Add IGNORE_UNUSED flag to sclk_i2s1Marek Szyprowski
2020-06-25clk: ti: composite: fix memory leakTero Kristo
2020-06-25clk: clk-flexgen: fix clock-critical handlingAlain Volmat
2020-06-25clk: samsung: Mark top ISP and CAM clocks on Exynos542x as criticalMarek Szyprowski
2020-06-25clk: qcom: msm8916: Fix the address location of pll->config_regBryan O'Donoghue
2020-06-25clk: sunxi: Fix incorrect usage of round_down()Rikard Falkeborn
2020-06-22PM: runtime: clk: Fix clk_pm_runtime_get() error pathRafael J. Wysocki
2020-05-20clk: Unlink clock if failed to prepare or enableMarc Zyngier
2020-05-20clk: rockchip: fix incorrect configuration of rk3228 aclk_gpu* clocksJustin Swartz
2020-04-23clk: tegra: Fix Tegra PMC clock out parentsSowjanya Komatineni
2020-04-23clk: at91: usb: continue if clk_hw_round_rate() return zeroClaudiu Beznea
2020-04-17clk: ingenic/jz4770: Exit with error if CGU init failedPaul Cercueil
2020-04-13clk: qcom: rcg: Return failure for RCG updateTaniya Das
2020-02-24clk: uniphier: Add SCSSI clock gate for each channelKunihiko Hayashi
2020-02-24clk: sunxi-ng: add mux and pll notifiers for A64 CPU clockIcenowy Zheng
2020-02-24clk: qcom: rcg2: Don't crash if our parent can't be found; return an errorDouglas Anderson
2020-02-11clk: tegra: Mark fuse clock as criticalStephen Warren
2020-02-05clk: mmp2: Fix the order of timer mux parentsLubomir Rintel
2020-02-05clk: sunxi-ng: h6-r: Fix AR100/R_APB2 parent orderSamuel Holland
2020-01-27clk: actions: Fix factor clk struct member accessManivannan Sadhasivam
2020-01-27clk: sunxi-ng: v3s: add the missing PLL_DDR1Icenowy Zheng
2020-01-27clk: qcom: Fix -Wunused-const-variableNathan Huckleberry
2020-01-27clk: sunxi-ng: sun50i-h6-r: Fix incorrect W1 clock gate registerOndrej Jirman
2020-01-27clk: meson: axg: spread spectrum is on mpll2Jerome Brunet
2020-01-27clk: meson: gxbb: no spread spectrum on mpll0Jerome Brunet
2020-01-27clk: qcom: Skip halt checks on gcc_pcie_0_pipe_clk for 8998Marc Gonzalez
2020-01-27clk: ingenic: jz4740: Fix gating of UDC clockPaul Cercueil
2020-01-27clk: sunxi-ng: sun8i-a23: Enable PLL-MIPI LDOs when ungating itChen-Yu Tsai
2020-01-27clk: dove: fix refcount leak in dove_clk_init()Yangtao Li