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path: root/drivers/clk/tegra/clk-tegra114.c
AgeCommit message (Expand)Author
2022-10-26clk: tegra: Fix refcount leak in tegra114_clock_initMiaoqian Lin
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201Thomas Gleixner
2018-12-14clk: tegra: Fix maximum audio sync clock for Tegra124/210Jon Hunter
2018-05-18clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20Dmitry Osipenko
2018-03-12clk: tegra: Specify VDE clock rateDmitry Osipenko
2018-03-12clk: tegra: Mark HCLK, SCLK and EMC as criticalDmitry Osipenko
2017-10-19clk: tegra: Use tegra_clk_register_periph_data()Thierry Reding
2017-03-20clk: tegra: Add CEC clockPeter De Schrijver
2016-08-24clk: tegra: remove TEGRA_PLL_USE_LOCK for PLLD/PLLD2Vince Hsu
2016-06-30clk: tegra: Initialize UTMI PLL when enabling PLLUAndrew Bresticker
2016-04-28clk: tegra: Special-case mipi-cal parent on Tegra114Thierry Reding
2016-03-02clk: tegra: Remove CLK_IS_ROOTStephen Boyd
2015-11-20clk: tegra: pll: Update PLLM handlingDanny Huang
2015-11-20clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rateRhyland Klein
2015-11-20clk: tegra: pll: Don't unconditionally set LOCK flagsRhyland Klein
2015-11-20clk: tegra: Constify pdiv-to-hw mappingsThierry Reding
2015-11-18clk: tegra: Format tables consistentlyThierry Reding
2015-11-18clk: tegra: Miscellaneous coding style cleanupsThierry Reding
2015-11-18clk: tegra: Fix 26 MHz oscillator frequencyThierry Reding
2015-10-20clk: tegra: Modify tegra_audio_clk_init to accept more pllsRhyland Klein
2015-07-20clk: tegra: Properly include clk.hStephen Boyd
2015-04-10clk: tegra: Use generic tegra_osc_clk_init() on Tegra114Thierry Reding
2015-04-10clk: tegra: Various whitespace cleanupsThierry Reding
2015-02-02clk: tegra: Define PLLD_DSI and remove dsia(b)_muxMark Zhang
2014-11-26clk: tegra: Implement memory-controller clockThierry Reding
2014-06-25clk: tegra: fix vi_sensor clocks on Tegra124Peter De Schrijver
2014-05-22clk: tegra: Initialize xusb clocksAndrew Bresticker
2014-05-22clk: tegra: Fix xusb_hs_src clock hierarchyAndrew Bresticker
2014-02-17clk: tegra: fix sdmmc clks on Tegra1x4Andrew Bresticker
2013-12-11clk: tegra: implement a reset driverStephen Warren
2013-11-26clk: tegra: Initialize DSI low-power clocksThierry Reding
2013-11-26clk: tegra: add FUSE clock deviceAlexandre Courbot
2013-11-26clk: tegra114: Initialize clocks needed for HDMIMikko Perttunen
2013-11-26clk: tegra: introduce common gen4 super clockPeter De Schrijver
2013-11-26clk: tegra: move PMC, fixed clocks to common filesPeter De Schrijver
2013-11-26clk: tegra: move periph clocks to common filePeter De Schrijver
2013-11-26clk: tegra: move audio clk to common filePeter De Schrijver
2013-11-26clk: tegra: add clkdev registration infraPeter De Schrijver
2013-11-26clk: tegra: move fields to tegra_clk_pll_paramsPeter De Schrijver
2013-11-26clk: tegra: use pll_ref as the pll_e parentPeter De Schrijver
2013-11-26clk: tegra: move some PLLC and PLLXC init to clk-pll.cPeter De Schrijver
2013-11-26clk: tegra: common periph_clk_enb_refcnt and clksPeter De Schrijver
2013-11-26clk: tegra: simplify periph clock dataPeter De Schrijver
2013-11-26clk: tegra114: Rename gr_2d/gr_3d to gr2d/gr3dThierry Reding
2013-11-26clk: tegra: Set the clk parent of host1x to pll_pAndrew Chew
2013-11-26clk: tegra: add TEGRA_DIVIDER_ROUND_UP for periph clksPeter De Schrijver
2013-11-25clk: tegra: Set the clock parent of gr2d/gr3d to pll_c2Mark Zhang
2013-11-25clk: tegra: Fix vde/2d/3d clock src offsetMark Zhang
2013-11-25clk: tegra: Correct sbc mux width & parentMark Zhang
2013-11-25clk: tegra: replace enum tegra114_clk by binding headerPeter De Schrijver