| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-06-05 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288 |   Thomas Gleixner |
| 2018-04-06 | clk: socfpga: stratix10: add clock driver for Stratix10 platform |   Dinh Nguyen |
| 2017-06-19 | clk: socfpga: Fix the smplsel on Arria10 and Stratix10 | Dinh Nguyen |
| 2015-08-24 | clk: socfpga: Add a second parent option for the dbg_base_clk |   Dinh Nguyen |
| 2015-07-28 | clk: socfpga: switch to GENMASK() |   Andy Shevchenko |
| 2015-07-20 | clk: socfpga: Remove clk.h and clkdev.h includes |   Stephen Boyd |
| 2015-05-21 | clk: socfpga: add a clock driver for the Arria 10 platform | Dinh Nguyen |
| 2015-05-21 | clk: socfpga: update clk.h so for Arria10 platform to use | Dinh Nguyen |
| 2014-05-12 | clk: socfpga: add divider registers to the main pll outputs |   Dinh Nguyen |
| 2014-02-18 | clk: socfpga: split clk code |   Steffen Trumtrar |
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index : linux-yocto | |
| Yocto Linux Embedded kernel | Grokmirror user |
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