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path: root/drivers/clk/renesas/r8a77990-cpg-mssr.c
AgeCommit message (Expand)Author
2020-06-22clk: renesas: rcar-gen3: Mark RWDT clocks as criticalUlrich Hecht
2020-02-10clk: renesas: rcar-gen3: Add CCREE clocksGeert Uytterhoeven
2019-06-18clk: renesas: r8a77990: Add CMM clocksJacopo Mondi
2019-04-02clk: renesas: rcar-gen3: Rename DRIF clocksTakeshi Kihara
2019-04-02clk: renesas: rcar-gen3: Correct parent clock of Audio-DMACTakeshi Kihara
2019-04-02clk: renesas: rcar-gen3: Correct parent clock of HS-USBKazuya Mizuguchi
2019-04-02clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCIKazuya Mizuguchi
2019-04-02clk: renesas: r8a77990: Add Z2 clockTakeshi Kihara
2018-12-04clk: renesas: r8a77990: Correct parent clock of DUTakeshi Kihara
2018-09-25clk: renesas: r8a77990: Fix incorrect PLL0 divider in commentGeert Uytterhoeven
2018-08-31clk: renesas: r8a77990: Add missing I2C7 clockGeert Uytterhoeven
2018-08-27clk: renesas: r8a77990: Correct RCLK handlingGeert Uytterhoeven
2018-05-09clk: renesas: cpg-mssr: Add support for R-Car E3Yoshihiro Shimoda