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path: root/drivers/clk/ingenic
AgeCommit message (Expand)Author
2020-03-20clk: ingenic/TCU: Fix round_rate returning errorPaul Cercueil
2020-03-20clk: ingenic/jz4770: Exit with error if CGU init failedPaul Cercueil
2020-03-20clk: JZ4780: Add function for enable the second core.周琰杰 (Zhou Yanjie)
2020-03-20clk: Ingenic: Add support for TCU of X1000.周琰杰 (Zhou Yanjie)
2019-11-27Merge branches 'clk-ingenic', 'clk-init-leak', 'clk-ux500' and 'clk-bitmain' ...Stephen Boyd
2019-11-22clk: ingenic: Allow drivers to be built with COMPILE_TESTStephen Boyd
2019-11-13clk: Ingenic: Add CGU driver for X1000.Zhou Yanjie
2019-11-08drivers/clk: convert VL struct to struct_sizeStephen Kitt
2019-09-22Merge tag 'mips_5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linuxLinus Torvalds
2019-08-12clk: ingenic: Use CLK_OF_DECLARE_DRIVER macroPaul Cercueil
2019-08-08clk: jz4740: Add TCU clockPaul Cercueil
2019-08-08clk: ingenic: Add driver for the TCU clocksPaul Cercueil
2019-08-07clk: ingenic/jz4740: Fix "pll half" divider not read/written properlyPaul Cercueil
2019-07-17Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds
2019-06-25clk: ingenic: Remove unused functionsPaul Cercueil
2019-06-25clk: ingenic: Handle setting the Low-Power Mode bitPaul Cercueil
2019-06-25clk: ingenic: Add missing header in cgu.hPaul Cercueil
2019-06-07clk: ingenic/jz4725b: Fix "pll half" divider not read/written properlyPaul Cercueil
2019-06-07clk: ingenic/jz4725b: Fix incorrect dividers for main clocksPaul Cercueil
2019-06-07clk: ingenic/jz4770: Fix incorrect dividers for main clocksPaul Cercueil
2019-06-07clk: ingenic/jz4740: Fix incorrect dividers for main clocksPaul Cercueil
2019-06-07clk: ingenic: Add support for divider tablesPaul Cercueil
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157Thomas Gleixner
2019-05-21treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner
2019-05-15clk: Remove io.h from clk-provider.hStephen Boyd
2019-04-11clk: ingenic: jz4725b: Add UDC PHY clockPaul Cercueil
2019-02-26clk: ingenic: Remove set but not used variable 'enable'YueHaibing
2019-02-22clk: ingenic: Fix doc of ingenic_cgu_div_infoPaul Cercueil
2019-02-22clk: ingenic: Fix round_rate misbehaving with non-integer dividersPaul Cercueil
2019-02-05clk: ingenic: jz4740: Fix gating of UDC clockPaul Cercueil
2018-10-16clk: Add Ingenic jz4725b CGU driverPaul Cercueil
2018-10-16clk: ingenic: Add proper Kconfig entriesPaul Cercueil
2018-07-06clk: ingenic: Add missing flag for UDC clockPaul Cercueil
2018-07-06clk: ingenic: Fix incorrect data for the i2s clockPaul Cercueil
2018-06-15docs: Fix some broken referencesMauro Carvalho Chehab
2018-06-01clk: ingenic: jz4770: Add 150us delay after enabling VPU clockPaul Cercueil
2018-06-01clk: ingenic: jz4770: Enable power of AHB1 bus after ungating VPU clockPaul Cercueil
2018-06-01clk: ingenic: jz4770: Modify C1CLK clock to disable CPU clock stop on idlePaul Cercueil
2018-06-01clk: ingenic: jz4770: Change OTG from custom to standard gated clockPaul Cercueil
2018-06-01clk: ingenic: Support specifying "wait for clock stable" delayPaul Cercueil
2018-06-01clk: ingenic: Add support for clocks whose gate bit is invertedPaul Cercueil
2018-01-18clk: Add Ingenic jz4770 CGU driverPaul Cercueil
2018-01-18clk: ingenic: Add code to enable/disable PLLsPaul Cercueil
2018-01-18clk: ingenic: support PLLs with no bypass bitPaul Cercueil
2018-01-18clk: ingenic: Fix recalc_rate for clocks with fixed dividerPaul Cercueil
2018-01-18clk: ingenic: Use const pointer to clk_ops in structPaul Cercueil
2017-11-03Update MIPS email addressesPaul Burton
2016-05-12clk: ingenic: Allow divider value to be dividedHarvey Hunt
2015-07-20clk: ingenic: Include clk.hStephen Boyd
2015-06-21clk: ingenic: add JZ4780 CGU supportPaul Burton