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path: root/arch/riscv/boot/dts/starfive/jh7100.dtsi
AgeCommit message (Expand)Author
2024-04-30riscv: dts: starfive: add 'cpus' label to jh7110 and jh7100 soc dtsiJisheng Zhang
2024-03-19Merge tag 'soc-late-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc...Linus Torvalds
2024-03-06Merge tag 'riscv-dt-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/...Arnd Bergmann
2024-03-05riscv: dts: starfive: jh7100: fix root clock namesKrzysztof Kozlowski
2024-02-13riscv: dts: starfive: replace underscores in node namesKrzysztof Kozlowski
2024-01-31riscv: dts: starfive: jh7100: Add sysmain and gmac DT nodesCristian Ciocaltea
2024-01-22riscv: dts: starfive: jh7100: Add PWM node and pins configurationWilliam Qiu
2023-12-13riscv: dts: starfive: Add JH7100 MMC nodesEmil Renner Berthing
2023-12-13riscv: dts: starfive: Add JH7100 cache controllerEmil Renner Berthing
2023-12-13riscv: dts: starfive: Mark the JH7100 as having non-coherent DMAsEmil Renner Berthing
2023-12-13riscv: dts: starfive: Group tuples in interrupt propertiesGeert Uytterhoeven
2023-10-15riscv: dts: starfive: convert isa detection to new propertiesConor Dooley
2023-07-25riscv: dts: starfive: jh7100: Add temperature sensor node and thermal-zonesHal Feng
2023-05-15riscv: dts: starfive: jh7100: Add watchdog nodeXingyu Wu
2022-08-11riscv: dts: starfive: correct number of external interruptsMark Kettenis
2022-07-14riscv: dts: starfive: Add JH7100 CPU topologyJonas Hahnfeld
2021-12-16RISC-V: Add initial StarFive JH7100 device treeEmil Renner Berthing