diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/snowridgex/memory.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/snowridgex/memory.json | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/memory.json b/tools/perf/pmu-events/arch/x86/snowridgex/memory.json index c02eb0e836ad..34306ec24e9b 100644 --- a/tools/perf/pmu-events/arch/x86/snowridgex/memory.json +++ b/tools/perf/pmu-events/arch/x86/snowridgex/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.", + "Counter": "0,1,2,3", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "SampleAfterValue": "20003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Counts the number of misaligned load uops that are 4K page splits.", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT", "PEBS": "1", @@ -16,6 +18,7 @@ }, { "BriefDescription": "Counts the number of misaligned store uops that are 4K page splits.", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT", "PEBS": "1", @@ -24,6 +27,7 @@ }, { "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -42,6 +47,7 @@ }, { "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.COREWB_M.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -51,6 +57,7 @@ }, { "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.COREWB_M.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -60,6 +67,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -69,6 +77,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -78,6 +87,7 @@ }, { "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -87,6 +97,7 @@ }, { "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -96,6 +107,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", @@ -106,6 +118,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL", @@ -116,6 +129,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -125,6 +139,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -134,6 +149,7 @@ }, { "BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.FULL_STREAMING_WR.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -143,6 +159,7 @@ }, { "BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.FULL_STREAMING_WR.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -152,6 +169,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -161,6 +179,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -170,6 +189,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -179,6 +199,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -188,6 +209,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -197,6 +219,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -206,6 +229,7 @@ }, { "BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.L1WB_M.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -215,6 +239,7 @@ }, { "BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.L1WB_M.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -224,6 +249,7 @@ }, { "BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.L2WB_M.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -233,6 +259,7 @@ }, { "BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.L2WB_M.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -242,6 +269,7 @@ }, { "BriefDescription": "Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.OTHER.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -251,6 +279,7 @@ }, { "BriefDescription": "Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.OTHER.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -260,6 +289,7 @@ }, { "BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.PARTIAL_STREAMING_WR.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -269,6 +299,7 @@ }, { "BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.PARTIAL_STREAMING_WR.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -278,6 +309,7 @@ }, { "BriefDescription": "Counts all hardware and software prefetches that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.PREFETCHES.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -287,6 +319,7 @@ }, { "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -296,6 +329,7 @@ }, { "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -305,6 +339,7 @@ }, { "BriefDescription": "Counts streaming stores that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.STREAMING_WR.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -314,6 +349,7 @@ }, { "BriefDescription": "Counts streaming stores that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.STREAMING_WR.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -323,6 +359,7 @@ }, { "BriefDescription": "Counts uncached memory reads that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -332,6 +369,7 @@ }, { "BriefDescription": "Counts uncached memory reads that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -341,6 +379,7 @@ }, { "BriefDescription": "Counts uncached memory writes that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_WR.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -350,6 +389,7 @@ }, { "BriefDescription": "Counts uncached memory writes that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_WR.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", |