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-rw-r--r--tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-cxl.json110
1 files changed, 110 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-cxl.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-cxl.json
index f3e84fd88de3..ff81f3a6426a 100644
--- a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-cxl.json
+++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-cxl.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "Counts the number of lfclk ticks",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x01",
"EventName": "UNC_CXLCM_CLOCKTICKS",
"PerPkg": "1",
@@ -9,390 +10,487 @@
},
{
"BriefDescription": "Number of Allocation to Mem Rxx AGF 0",
+ "Counter": "4,5,6,7",
"EventCode": "0x43",
"EventName": "UNC_CXLCM_RxC_AGF_INSERTS.CACHE_DATA",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Cache Req AGF0",
+ "Counter": "4,5,6,7",
"EventCode": "0x43",
"EventName": "UNC_CXLCM_RxC_AGF_INSERTS.CACHE_REQ0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Cache Rsp AGF",
+ "Counter": "4,5,6,7",
"EventCode": "0x43",
"EventName": "UNC_CXLCM_RxC_AGF_INSERTS.CACHE_REQ1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Cache Data AGF",
+ "Counter": "4,5,6,7",
"EventCode": "0x43",
"EventName": "UNC_CXLCM_RxC_AGF_INSERTS.CACHE_RSP0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Cache Rsp AGF",
+ "Counter": "4,5,6,7",
"EventCode": "0x43",
"EventName": "UNC_CXLCM_RxC_AGF_INSERTS.CACHE_RSP1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Cache Req AGF 1",
+ "Counter": "4,5,6,7",
"EventCode": "0x43",
"EventName": "UNC_CXLCM_RxC_AGF_INSERTS.MEM_DATA",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Mem Data AGF",
+ "Counter": "4,5,6,7",
"EventCode": "0x43",
"EventName": "UNC_CXLCM_RxC_AGF_INSERTS.MEM_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of Flits with AK set",
+ "Counter": "4,5,6,7",
"EventCode": "0x4b",
"EventName": "UNC_CXLCM_RxC_FLITS.AK_HDR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of Flits with BE set",
+ "Counter": "4,5,6,7",
"EventCode": "0x4b",
"EventName": "UNC_CXLCM_RxC_FLITS.BE_HDR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of control flits received",
+ "Counter": "4,5,6,7",
"EventCode": "0x4b",
"EventName": "UNC_CXLCM_RxC_FLITS.CTRL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of Headerless flits received",
+ "Counter": "4,5,6,7",
"EventCode": "0x4b",
"EventName": "UNC_CXLCM_RxC_FLITS.NO_HDR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of protocol flits received",
+ "Counter": "4,5,6,7",
"EventCode": "0x4b",
"EventName": "UNC_CXLCM_RxC_FLITS.PROT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of Flits with SZ set",
+ "Counter": "4,5,6,7",
"EventCode": "0x4b",
"EventName": "UNC_CXLCM_RxC_FLITS.SZ_HDR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of flits received",
+ "Counter": "4,5,6,7",
"EventCode": "0x4b",
"EventName": "UNC_CXLCM_RxC_FLITS.VALID",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of valid messages in the flit",
+ "Counter": "4,5,6,7",
"EventCode": "0x4b",
"EventName": "UNC_CXLCM_RxC_FLITS.VALID_MSG",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of CRC errors detected",
+ "Counter": "4,5,6,7",
"EventCode": "0x40",
"EventName": "UNC_CXLCM_RxC_MISC.CRC_ERRORS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of Init flits sent",
+ "Counter": "4,5,6,7",
"EventCode": "0x40",
"EventName": "UNC_CXLCM_RxC_MISC.INIT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of LLCRD flits sent",
+ "Counter": "4,5,6,7",
"EventCode": "0x40",
"EventName": "UNC_CXLCM_RxC_MISC.LLCRD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of Retry flits sent",
+ "Counter": "4,5,6,7",
"EventCode": "0x40",
"EventName": "UNC_CXLCM_RxC_MISC.RETRY",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of cycles the Packing Buffer is Full",
+ "Counter": "4,5,6,7",
"EventCode": "0x52",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_FULL.CACHE_DATA",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of cycles the Packing Buffer is Full",
+ "Counter": "4,5,6,7",
"EventCode": "0x52",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_FULL.CACHE_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of cycles the Packing Buffer is Full",
+ "Counter": "4,5,6,7",
"EventCode": "0x52",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_FULL.CACHE_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of cycles the Packing Buffer is Full",
+ "Counter": "4,5,6,7",
"EventCode": "0x52",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_FULL.MEM_DATA",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of cycles the Packing Buffer is Full",
+ "Counter": "4,5,6,7",
"EventCode": "0x52",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_FULL.MEM_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Cache Data Packing buffer",
+ "Counter": "4,5,6,7",
"EventCode": "0x41",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.CACHE_DATA",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Cache Req Packing buffer",
+ "Counter": "4,5,6,7",
"EventCode": "0x41",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.CACHE_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Cache Rsp Packing buffer",
+ "Counter": "4,5,6,7",
"EventCode": "0x41",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.CACHE_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Mem Data Packing buffer",
+ "Counter": "4,5,6,7",
"EventCode": "0x41",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.MEM_DATA",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Mem Rxx Packing buffer",
+ "Counter": "4,5,6,7",
"EventCode": "0x41",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.MEM_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of cycles of Not Empty for Cache Data Packing buffer",
+ "Counter": "4,5,6,7",
"EventCode": "0x42",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_NE.CACHE_DATA",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of cycles of Not Empty for Cache Req Packing buffer",
+ "Counter": "4,5,6,7",
"EventCode": "0x42",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_NE.CACHE_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of cycles of Not Empty for Cache Rsp Packing buffer",
+ "Counter": "4,5,6,7",
"EventCode": "0x42",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_NE.CACHE_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of cycles of Not Empty for Mem Data Packing buffer",
+ "Counter": "4,5,6,7",
"EventCode": "0x42",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_NE.MEM_DATA",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of cycles of Not Empty for Mem Rxx Packing buffer",
+ "Counter": "4,5,6,7",
"EventCode": "0x42",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_NE.MEM_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of Flits with AK set",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_CXLCM_TxC_FLITS.AK_HDR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of Flits with BE set",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_CXLCM_TxC_FLITS.BE_HDR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of control flits packed",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_CXLCM_TxC_FLITS.CTRL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of Headerless flits packed",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_CXLCM_TxC_FLITS.NO_HDR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of protocol flits packed",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_CXLCM_TxC_FLITS.PROT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of Flits with SZ set",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_CXLCM_TxC_FLITS.SZ_HDR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of flits packed",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_CXLCM_TxC_FLITS.VALID",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Cache Data Packing buffer",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.CACHE_DATA",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Cache Req Packing buffer",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.CACHE_REQ0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Cache Rsp1 Packing buffer",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.CACHE_REQ1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Cache Rsp0 Packing buffer",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.CACHE_RSP0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Cache Req Packing buffer",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.CACHE_RSP1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Mem Data Packing buffer",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.MEM_DATA",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Mem Rxx Packing buffer",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.MEM_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "CXLCM"
},
{
"BriefDescription": "Counts the number of uclk ticks",
+ "Counter": "0,1,2,3",
"EventCode": "0x01",
"EventName": "UNC_CXLDP_CLOCKTICKS",
"PerPkg": "1",
@@ -401,48 +499,60 @@
},
{
"BriefDescription": "Number of Allocation to M2S Data AGF",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_CXLDP_TxC_AGF_INSERTS.M2S_DATA",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "CXLDP"
},
{
"BriefDescription": "Number of Allocation to M2S Req AGF",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_CXLDP_TxC_AGF_INSERTS.M2S_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CXLDP"
},
{
"BriefDescription": "Number of Allocation to U2C Data AGF",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_CXLDP_TxC_AGF_INSERTS.U2C_DATA",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "CXLDP"
},
{
"BriefDescription": "Number of Allocation to U2C Req AGF",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_CXLDP_TxC_AGF_INSERTS.U2C_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CXLDP"
},
{
"BriefDescription": "Number of Allocation to U2C Rsp AGF 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_CXLDP_TxC_AGF_INSERTS.U2C_RSP0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CXLDP"
},
{
"BriefDescription": "Number of Allocation to U2C Rsp AGF 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_CXLDP_TxC_AGF_INSERTS.U2C_RSP1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CXLDP"
generated by cgit (git 2.34.1) at 2025-03-18 15:05:44 +0000