diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/meteorlake/uncore-memory.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/meteorlake/uncore-memory.json | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/uncore-memory.json b/tools/perf/pmu-events/arch/x86/meteorlake/uncore-memory.json index c9d248d1042e..783a4f7fd05b 100644 --- a/tools/perf/pmu-events/arch/x86/meteorlake/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/meteorlake/uncore-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts every CAS read command sent from the Memory Controller 0 to DRAM (sum of all channels).", + "Counter": "0", "EventCode": "0xff", "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN", "PerPkg": "1", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Counts every read and write request entering the Memory Controller 0.", + "Counter": "2", "EventCode": "0xff", "EventName": "UNC_MC0_TOTAL_REQCOUNT_FREERUN", "PerPkg": "1", @@ -19,6 +21,7 @@ }, { "BriefDescription": "Counts every CAS write command sent from the Memory Controller 0 to DRAM (sum of all channels).", + "Counter": "1", "EventCode": "0xff", "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN", "PerPkg": "1", @@ -28,6 +31,7 @@ }, { "BriefDescription": "Counts every CAS read command sent from the Memory Controller 1 to DRAM (sum of all channels).", + "Counter": "3", "EventCode": "0xff", "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN", "PerPkg": "1", @@ -37,6 +41,7 @@ }, { "BriefDescription": "Counts every read and write request entering the Memory Controller 1.", + "Counter": "5", "EventCode": "0xff", "EventName": "UNC_MC1_TOTAL_REQCOUNT_FREERUN", "PerPkg": "1", @@ -46,6 +51,7 @@ }, { "BriefDescription": "Counts every CAS write command sent from the Memory Controller 1 to DRAM (sum of all channels).", + "Counter": "4", "EventCode": "0xff", "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN", "PerPkg": "1", @@ -55,6 +61,7 @@ }, { "BriefDescription": "ACT command for a read request sent to DRAM", + "Counter": "0,1,2,3,4", "EventCode": "0x24", "EventName": "UNC_M_ACT_COUNT_RD", "PerPkg": "1", @@ -62,6 +69,7 @@ }, { "BriefDescription": "ACT command sent to DRAM", + "Counter": "0,1,2,3,4", "EventCode": "0x26", "EventName": "UNC_M_ACT_COUNT_TOTAL", "PerPkg": "1", @@ -69,6 +77,7 @@ }, { "BriefDescription": "ACT command for a write request sent to DRAM", + "Counter": "0,1,2,3,4", "EventCode": "0x25", "EventName": "UNC_M_ACT_COUNT_WR", "PerPkg": "1", @@ -76,6 +85,7 @@ }, { "BriefDescription": "Read CAS command sent to DRAM", + "Counter": "0,1,2,3,4", "EventCode": "0x22", "EventName": "UNC_M_CAS_COUNT_RD", "PerPkg": "1", @@ -83,6 +93,7 @@ }, { "BriefDescription": "Write CAS command sent to DRAM", + "Counter": "0,1,2,3,4", "EventCode": "0x23", "EventName": "UNC_M_CAS_COUNT_WR", "PerPkg": "1", @@ -90,6 +101,7 @@ }, { "BriefDescription": "PRE command sent to DRAM due to page table idle timer expiration", + "Counter": "0,1,2,3,4", "EventCode": "0x28", "EventName": "UNC_M_PRE_COUNT_IDLE", "PerPkg": "1", @@ -97,6 +109,7 @@ }, { "BriefDescription": "PRE command sent to DRAM for a read/write request", + "Counter": "0,1,2,3,4", "EventCode": "0x27", "EventName": "UNC_M_PRE_COUNT_PAGE_MISS", "PerPkg": "1", @@ -104,6 +117,7 @@ }, { "BriefDescription": "Number of bytes read from DRAM, in 32B chunks. Counter increments by 1 after receiving 32B chunk data.", + "Counter": "0,1,2,3,4", "EventCode": "0x3A", "EventName": "UNC_M_RD_DATA", "PerPkg": "1", @@ -111,6 +125,7 @@ }, { "BriefDescription": "Total number of read and write byte transfers to/from DRAM, in 32B chunks. Counter increments by 1 after sending or receiving 32B chunk data.", + "Counter": "0,1,2,3,4", "EventCode": "0x3C", "EventName": "UNC_M_TOTAL_DATA", "PerPkg": "1", @@ -118,6 +133,7 @@ }, { "BriefDescription": "Number of bytes written to DRAM, in 32B chunks. Counter increments by 1 after sending 32B chunk data.", + "Counter": "0,1,2,3,4", "EventCode": "0x3B", "EventName": "UNC_M_WR_DATA", "PerPkg": "1", |