diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/jaketown/memory.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/jaketown/memory.json | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/memory.json b/tools/perf/pmu-events/arch/x86/jaketown/memory.json index a71e630fd030..41200f0e0df6 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/memory.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers. Machine clears can have a significant performance impact if they are happening frequently.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Loads with latency value being above 128.", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", "MSRIndex": "0x3F6", @@ -19,6 +21,7 @@ }, { "BriefDescription": "Loads with latency value being above 16.", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", "MSRIndex": "0x3F6", @@ -29,6 +32,7 @@ }, { "BriefDescription": "Loads with latency value being above 256.", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", "MSRIndex": "0x3F6", @@ -39,6 +43,7 @@ }, { "BriefDescription": "Loads with latency value being above 32.", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", "MSRIndex": "0x3F6", @@ -49,6 +54,7 @@ }, { "BriefDescription": "Loads with latency value being above 4 .", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", "MSRIndex": "0x3F6", @@ -59,6 +65,7 @@ }, { "BriefDescription": "Loads with latency value being above 512.", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", "MSRIndex": "0x3F6", @@ -69,6 +76,7 @@ }, { "BriefDescription": "Loads with latency value being above 64.", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", "MSRIndex": "0x3F6", @@ -79,6 +87,7 @@ }, { "BriefDescription": "Loads with latency value being above 8.", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", "MSRIndex": "0x3F6", @@ -89,6 +98,7 @@ }, { "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE", "PEBS": "2", @@ -97,6 +107,7 @@ }, { "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache.", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "MISALIGN_MEM_REF.LOADS", "SampleAfterValue": "2000003", @@ -104,6 +115,7 @@ }, { "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache.", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "MISALIGN_MEM_REF.STORES", "SampleAfterValue": "2000003", @@ -111,6 +123,7 @@ }, { "BriefDescription": "This event counts all LLC misses for all demand and L2 prefetches. LLC prefetches are excluded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -120,6 +133,7 @@ }, { "BriefDescription": "Counts all local dram accesses for all demand and L2 prefetches. LLC prefetches are excluded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -129,6 +143,7 @@ }, { "BriefDescription": "This event counts all remote cache-to-cache transfers (includes HITM and HIT-Forward) for all demand and L2 prefetches. LLC prefetches are excluded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.REMOTE_HITM_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", @@ -138,6 +153,7 @@ }, { "BriefDescription": "Counts all demand code reads that miss the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -147,6 +163,7 @@ }, { "BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from local dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -156,6 +173,7 @@ }, { "BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from remote dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -165,6 +183,7 @@ }, { "BriefDescription": "Counts all demand code reads that miss the LLC the data is found in M state in remote cache and forwarded from there", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -174,6 +193,7 @@ }, { "BriefDescription": "Counts all demand code reads that miss the LLC and the data forwarded from remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", @@ -183,6 +203,7 @@ }, { "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote & local dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -192,6 +213,7 @@ }, { "BriefDescription": "Counts demand data reads that miss in the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -201,6 +223,7 @@ }, { "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from local dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -210,6 +233,7 @@ }, { "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -219,6 +243,7 @@ }, { "BriefDescription": "Counts demand data reads that miss the LLC the data is found in M state in remote cache and forwarded from there", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -228,6 +253,7 @@ }, { "BriefDescription": "Counts demand data reads that miss the LLC and the data forwarded from remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", @@ -237,6 +263,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from remote & local dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -246,6 +273,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote & local dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -255,6 +283,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -264,6 +293,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from local dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -273,6 +303,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -282,6 +313,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC the data is found in M state in remote cache and forwarded from there", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -291,6 +323,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data forwarded from remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", @@ -300,6 +333,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -309,6 +343,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", |