diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/ivybridge/memory.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/ivybridge/memory.json | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/memory.json b/tools/perf/pmu-events/arch/x86/ivybridge/memory.json index fd1fe491c577..40f40384d58b 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/memory.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "SampleAfterValue": "100003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Loads with latency value being above 128", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", "MSRIndex": "0x3F6", @@ -19,6 +21,7 @@ }, { "BriefDescription": "Loads with latency value being above 16", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", "MSRIndex": "0x3F6", @@ -30,6 +33,7 @@ }, { "BriefDescription": "Loads with latency value being above 256", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", "MSRIndex": "0x3F6", @@ -41,6 +45,7 @@ }, { "BriefDescription": "Loads with latency value being above 32", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", "MSRIndex": "0x3F6", @@ -52,6 +57,7 @@ }, { "BriefDescription": "Loads with latency value being above 4", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", "MSRIndex": "0x3F6", @@ -63,6 +69,7 @@ }, { "BriefDescription": "Loads with latency value being above 512", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", "MSRIndex": "0x3F6", @@ -74,6 +81,7 @@ }, { "BriefDescription": "Loads with latency value being above 64", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", "MSRIndex": "0x3F6", @@ -85,6 +93,7 @@ }, { "BriefDescription": "Loads with latency value being above 8", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", "MSRIndex": "0x3F6", @@ -96,6 +105,7 @@ }, { "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only.", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE", "PEBS": "2", @@ -104,6 +114,7 @@ }, { "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "MISALIGN_MEM_REF.LOADS", "PublicDescription": "Speculative cache-line split load uops dispatched to L1D.", @@ -112,6 +123,7 @@ }, { "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "MISALIGN_MEM_REF.STORES", "PublicDescription": "Speculative cache-line split Store-address uops dispatched to L1D.", @@ -120,6 +132,7 @@ }, { "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC and the data returned from dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -129,6 +142,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads that miss the LLC and the data returned from dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -138,6 +152,7 @@ }, { "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -147,6 +162,7 @@ }, { "BriefDescription": "Counts LLC replacements", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -156,6 +172,7 @@ }, { "BriefDescription": "Counts demand code reads that miss the LLC and the data returned from dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -165,6 +182,7 @@ }, { "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -174,6 +192,7 @@ }, { "BriefDescription": "Number of any page walk that had a miss in LLC.", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "PAGE_WALKS.LLC_MISS", "SampleAfterValue": "100003", |