diff options
Diffstat (limited to 'meta-xilinx-core/dynamic-layers/openamp-layer/recipes-bsp')
10 files changed, 510 insertions, 0 deletions
diff --git a/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-bsp/device-tree/device-tree.bbappend b/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-bsp/device-tree/device-tree.bbappend new file mode 100644 index 00000000..7dcee565 --- /dev/null +++ b/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-bsp/device-tree/device-tree.bbappend @@ -0,0 +1,21 @@ +FILESEXTRAPATHS:prepend := "${THISDIR}/files:" + +# openamp.dtsi is in the WORKDIR +DT_INCLUDE:append = " ${WORKDIR}" + +do_configure[vardeps] += "ENABLE_OPENAMP_DTSI OPENAMP_EXTRA_OVERLAYS" + +OPENAMP_EXTRA_OVERLAYS:zynq = "zynq-openamp.dtsi" +OPENAMP_EXTRA_OVERLAYS:zynqmp = "zynqmp-openamp.dtsi" +OPENAMP_EXTRA_OVERLAYS:versal = "versal-openamp.dtsi" +OPENAMP_EXTRA_OVERLAYS:versal-net = "versal-net-openamp.dtsi" + +def set_openamp_extra_overlays(d): + distro_features = d.getVar('DISTRO_FEATURES', True) + enable_openamp_dtsi = d.getVar('ENABLE_OPENAMP_DTSI') + if 'openamp' in distro_features and enable_openamp_dtsi == '1': + return ' ${OPENAMP_EXTRA_OVERLAYS}' + else: + return '' + +EXTRA_OVERLAYS:append = "${@set_openamp_extra_overlays(d)}" diff --git a/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-bsp/device-tree/files/versal-net-openamp-overlay.dts b/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-bsp/device-tree/files/versal-net-openamp-overlay.dts new file mode 100644 index 00000000..9fdebe39 --- /dev/null +++ b/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-bsp/device-tree/files/versal-net-openamp-overlay.dts @@ -0,0 +1,13 @@ +/* + * SPDX-License-Identifier: MIT + * + * dts overlay file for Versal NET OpenAMP + * + * Copyright (C) 2023, Advanced Micro Devices, Inc. All rights reserved. + * + */ + +/dts-v1/; +/plugin/; + +#include "versal-net-openamp.dtsi" diff --git a/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-bsp/device-tree/files/versal-net-openamp.dtsi b/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-bsp/device-tree/files/versal-net-openamp.dtsi new file mode 100644 index 00000000..694a2fd0 --- /dev/null +++ b/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-bsp/device-tree/files/versal-net-openamp.dtsi @@ -0,0 +1,97 @@ +/* + * SPDX-License-Identifier: MIT + * + * dts file for Versal NET OpenAMP + * + * Copyright (C) 2023, Advanced Micro Devices, Inc. All rights reserved. + * + */ + +&{/} { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + rproc_0_reserved: rproc@3ed00000 { + no-map; + reg = <0x0 0x3ed00000 0x0 0x40000>; + }; + rpu0vdev0vring0: rpu0vdev0vring0@3ed40000 { + no-map; + reg = <0x0 0x3ed40000 0x0 0x4000>; + }; + rpu0vdev0vring1: rpu0vdev0vring1@3ed44000 { + no-map; + reg = <0x0 0x3ed44000 0x0 0x4000>; + }; + rpu0vdev0buffer: rpu0vdev0buffer@3ed48000 { + no-map; + reg = <0x0 0x3ed48000 0x0 0x100000>; + }; + }; + + tcm_0a: tcm_0a@eba00000 { + no-map; + reg = <0x0 0xeba00000 0x0 0x10000>; + status = "okay"; + compatible = "mmio-sram"; + power-domain = <&versal_net_firmware 0x183180cb>; + }; + + tcm_0b: tcm_0b@eba10000 { + no-map; + reg = <0x0 0xeba10000 0x0 0x8000>; + status = "okay"; + compatible = "mmio-sram"; + power-domain = <&versal_net_firmware 0x183180cc>; + }; + + tcm_0c: tcm_0b@eba20000 { + no-map; + reg = <0x0 0xeba20000 0x0 0x8000>; + status = "okay"; + compatible = "mmio-sram"; + power-domain = <&versal_net_firmware 0x183180cd>; + }; + + r52ss { + compatible = "xlnx,versal-net-r52-remoteproc"; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + xlnx,cluster-mode = <1>; + + r52_0 { + compatible = "xilinx,r52"; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + sram = <&tcm_0a>, <&tcm_0b>, <&tcm_0c>; + memory-region = <&rproc_0_reserved>, <&rpu0vdev0buffer>, <&rpu0vdev0vring0>, <&rpu0vdev0vring1>; + power-domain = <&versal_net_firmware 0x181100BF>; + mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>; + mbox-names = "tx", "rx"; + }; + }; + + zynqmp_ipi1 { + compatible = "xlnx,zynqmp-ipi-mailbox"; + interrupt-parent = <&gic>; + interrupts = <0x00 0x3c 0x04>; + xlnx,ipi-id = <5>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* APU<->RPU0 IPI mailbox controller */ + ipi_mailbox_rpu0: mailbox@eb3f0ac0 { + reg = <0xeb3f0ac0 0x20 0xeb3f0ae0 0x20 0xeb3f0740 0x20 0xeb3f0760 0x20>; + reg-names = "local_request_region", + "local_response_region", + "remote_request_region", + "remote_response_region"; + #mbox-cells = <0x01>; + xlnx,ipi-id = <0x03>; + }; + }; +}; diff --git a/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-bsp/device-tree/files/versal-openamp-overlay.dts b/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-bsp/device-tree/files/versal-openamp-overlay.dts new file mode 100644 index 00000000..80ed4639 --- /dev/null +++ b/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-bsp/device-tree/files/versal-openamp-overlay.dts @@ -0,0 +1,13 @@ +/* + * SPDX-License-Identifier: MIT + * + * dts overlay file for Versal OpenAMP + * + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + */ + +/dts-v1/; +/plugin/; + +#include "versal-openamp.dtsi" diff --git a/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-bsp/device-tree/files/versal-openamp.dtsi b/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-bsp/device-tree/files/versal-openamp.dtsi new file mode 100644 index 00000000..01e337c7 --- /dev/null +++ b/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-bsp/device-tree/files/versal-openamp.dtsi @@ -0,0 +1,150 @@ +/* + * SPDX-License-Identifier: MIT + * + * dts file for Versal OpenAMP + * + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + */ + +&{/} { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + rproc_0_reserved: rproc@3ed00000 { + no-map; + reg = <0x0 0x3ed00000 0x0 0x40000>; + }; + rpu0vdev0vring0: rpu0vdev0vring0@3ed40000 { + no-map; + reg = <0x0 0x3ed40000 0x0 0x4000>; + }; + rpu0vdev0vring1: rpu0vdev0vring1@3ed44000 { + no-map; + reg = <0x0 0x3ed44000 0x0 0x4000>; + }; + rpu0vdev0buffer: rpu0vdev0buffer@3ed48000 { + no-map; + reg = <0x0 0x3ed48000 0x0 0x100000>; + }; + rproc_1_reserved: rproc@3ef00000 { + no-map; + reg = <0x0 0x3ef00000 0x0 0x40000>; + }; + rpu1vdev0vring0: rpu1vdev0vring0@3ef40000 { + no-map; + reg = <0x0 0x3ef40000 0x0 0x4000>; + }; + rpu1vdev0vring1: rpu1vdev0vring1@3ef44000 { + no-map; + reg = <0x0 0x3ef44000 0x0 0x4000>; + }; + rpu1vdev0buffer: rpu1vdev0buffer@3ef48000 { + no-map; + compatible = "shared-dma-pool"; + reg = <0x0 0x3ef48000 0x0 0x100000>; + }; + }; + + tcm_0a: tcm_0a@ffe00000 { + no-map; + reg = <0x0 0xffe00000 0x0 0x10000>; + status = "okay"; + compatible = "mmio-sram"; + power-domain = <&versal_firmware 0x1831800b>; + }; + + tcm_0b: tcm_0b@ffe20000 { + no-map; + reg = <0x0 0xffe20000 0x0 0x10000>; + status = "okay"; + compatible = "mmio-sram"; + power-domain = <&versal_firmware 0x1831800c>; + }; + + tcm_1a: tcm_1a@ffe90000 { + no-map; + reg = <0x0 0xffe90000 0x0 0x10000>; + status = "okay"; + compatible = "mmio-sram"; + power-domain = <&versal_firmware 0x1831800d>; + }; + + tcm_1b: tcm_1b@ffeb0000 { + no-map; + reg = <0x0 0xffeb0000 0x0 0x10000>; + status = "okay"; + compatible = "mmio-sram"; + power-domain = <&versal_firmware 0x1831800e>; + }; + + rf5ss@ff9a0000 { + compatible = "xlnx,zynqmp-r5-remoteproc"; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + xlnx,cluster-mode = <1>; + reg = <0x0 0xff9a0000 0x0 0x10000>; + + r5f_0 { + compatible = "xilinx,r5f"; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + sram = <&tcm_0a>, <&tcm_0b>; + memory-region = <&rproc_0_reserved>, <&rpu0vdev0buffer>, <&rpu0vdev0vring0>, <&rpu0vdev0vring1>; + power-domain = <&versal_firmware 0x18110005>; + mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>; + mbox-names = "tx", "rx"; + }; + r5f_1 { + compatible = "xilinx,r5f"; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + sram = <&tcm_1a>, <&tcm_1b>; + memory-region = <&rproc_1_reserved>, <&rpu1vdev0buffer>, <&rpu1vdev0vring0>, <&rpu1vdev0vring1>; + power-domain = <&versal_firmware 0x18110006>; + mboxes = <&ipi_mailbox_rpu1 0>, <&ipi_mailbox_rpu1 1>; + mbox-names = "tx", "rx"; + }; + }; + + zynqmp_ipi1 { + compatible = "xlnx,zynqmp-ipi-mailbox"; + interrupt-parent = <&gic>; + interrupts = <0 33 4>; + xlnx,ipi-id = <5>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* APU<->RPU0 IPI mailbox controller */ + ipi_mailbox_rpu0: mailbox@ff990600 { + reg = <0xff3f0ac0 0x20>, + <0xff3f0ae0 0x20>, + <0xff3f0740 0x20>, + <0xff3f0760 0x20>; + reg-names = "local_request_region", + "local_response_region", + "remote_request_region", + "remote_response_region"; + #mbox-cells = <1>; + xlnx,ipi-id = <3>; + }; + /* APU<->RPU1 IPI mailbox controller */ + ipi_mailbox_rpu1: mailbox@ff990640 { + reg = <0xff3f0b00 0x20>, + <0xff3f0b20 0x20>, + <0xff3f0940 0x20>, + <0xff3f0960 0x20>; + reg-names = "local_request_region", + "local_response_region", + "remote_request_region", + "remote_response_region"; + #mbox-cells = <1>; + xlnx,ipi-id = <4>; + }; + }; +}; diff --git a/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-bsp/device-tree/files/zynq-openamp-overlay.dts b/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-bsp/device-tree/files/zynq-openamp-overlay.dts new file mode 100644 index 00000000..b5d238ff --- /dev/null +++ b/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-bsp/device-tree/files/zynq-openamp-overlay.dts @@ -0,0 +1,13 @@ +/* + * SPDX-License-Identifier: MIT + * + * dts overlay file for Zynq OpenAMP + * + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + */ + +/dts-v1/; +/plugin/; + +#include "zynq-openamp.dtsi" diff --git a/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-bsp/device-tree/files/zynq-openamp.dtsi b/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-bsp/device-tree/files/zynq-openamp.dtsi new file mode 100644 index 00000000..0e822202 --- /dev/null +++ b/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-bsp/device-tree/files/zynq-openamp.dtsi @@ -0,0 +1,43 @@ +/* + * SPDX-License-Identifier: MIT + * + * dts file for Zynq OpenAMP + * + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + */ + +&{/} { + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + vdev0vring0: vdev0vring0@3e800000 { + no-map; + compatible = "shared-dma-pool"; + reg = <0x3e800000 0x4000>; + }; + vdev0vring1: vdev0vring1@3e804000 { + no-map; + compatible = "shared-dma-pool"; + reg = <0x3e804000 0x4000>; + }; + vdev0buffer: vdev0buffer@3e808000 { + no-map; + compatible = "shared-dma-pool"; + reg = <0x3e808000 0x100000>; + }; + rproc_0_reserved: rproc@3e000000 { + no-map; + compatible = "shared-dma-pool"; + reg = <0x3e000000 0x800000>; + }; + }; + + remoteproc0: remoteproc@0 { + compatible = "xlnx,zynq_remoteproc"; + firmware = "firmware"; + memory-region = <&rproc_0_reserved>, <&vdev0buffer>, <&vdev0vring0>, <&vdev0vring1>; + interrupt-parent = <&intc>; + }; +}; diff --git a/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-bsp/device-tree/files/zynqmp-openamp-overlay.dts b/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-bsp/device-tree/files/zynqmp-openamp-overlay.dts new file mode 100644 index 00000000..da1d171e --- /dev/null +++ b/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-bsp/device-tree/files/zynqmp-openamp-overlay.dts @@ -0,0 +1,13 @@ +/* + * SPDX-License-Identifier: MIT + * + * dts overlay file for ZynqMP OpenAMP + * + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + */ + +/dts-v1/; +/plugin/; + +#include "zynqmp-openamp.dtsi" diff --git a/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-bsp/device-tree/files/zynqmp-openamp.dtsi b/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-bsp/device-tree/files/zynqmp-openamp.dtsi new file mode 100644 index 00000000..c8a60d81 --- /dev/null +++ b/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-bsp/device-tree/files/zynqmp-openamp.dtsi @@ -0,0 +1,93 @@ +/* + * SPDX-License-Identifier: MIT + * + * dts file for ZynqMP OpenAMP + * + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + */ + +&{/} { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + rpu0vdev0vring0: rpu0vdev0vring0@3ed40000 { + no-map; + reg = <0x0 0x3ed40000 0x0 0x4000>; + }; + rpu0vdev0vring1: rpu0vdev0vring1@3ed44000 { + no-map; + reg = <0x0 0x3ed44000 0x0 0x4000>; + }; + rpu0vdev0buffer: rpu0vdev0buffer@3ed48000 { + no-map; + reg = <0x0 0x3ed48000 0x0 0x100000>; + }; + rproc_0_reserved: rproc@3ed00000 { + no-map; + reg = <0x0 0x3ed00000 0x0 0x40000>; + }; + }; + + tcm_0a: tcm_0a@ffe00000 { + no-map; + reg = <0x0 0xffe00000 0x0 0x10000>; + status = "okay"; + compatible = "mmio-sram"; + power-domain = <&zynqmp_firmware 15>; + }; + + tcm_0b: tcm_0b@ffe20000 { + no-map; + reg = <0x0 0xffe20000 0x0 0x10000>; + status = "okay"; + compatible = "mmio-sram"; + power-domain = <&zynqmp_firmware 16>; + }; + + rf5ss@ff9a0000 { + compatible = "xlnx,zynqmp-r5-remoteproc"; + xlnx,cluster-mode = <1>; + ranges; + reg = <0x0 0xFF9A0000 0x0 0x10000>; + #address-cells = <0x2>; + #size-cells = <0x2>; + + r5f_0: r5f@0 { + compatible = "xilinx,r5f"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + sram = <&tcm_0a>, <&tcm_0b>; + memory-region = <&rproc_0_reserved>, <&rpu0vdev0buffer>, <&rpu0vdev0vring0>, <&rpu0vdev0vring1>; + power-domain = <&zynqmp_firmware 7>; + mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>; + mbox-names = "tx", "rx"; + }; + }; + + zynqmp_ipi1 { + compatible = "xlnx,zynqmp-ipi-mailbox"; + interrupt-parent = <&gic>; + interrupts = <0 29 4>; + xlnx,ipi-id = <7>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* APU<->RPU0 IPI mailbox controller */ + ipi_mailbox_rpu0: mailbox@ff990600 { + reg = <0xff990600 0x20>, + <0xff990620 0x20>, + <0xff9900c0 0x20>, + <0xff9900e0 0x20>; + reg-names = "local_request_region", + "local_response_region", + "remote_request_region", + "remote_response_region"; + #mbox-cells = <1>; + xlnx,ipi-id = <1>; + }; + }; +}; diff --git a/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-bsp/device-tree/open-amp-device-tree.bb b/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-bsp/device-tree/open-amp-device-tree.bb new file mode 100644 index 00000000..9f481fec --- /dev/null +++ b/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-bsp/device-tree/open-amp-device-tree.bb @@ -0,0 +1,54 @@ +SUMMARY = "OpenAMP Device Tree Overlay for Xilinx devices." +SECTION = "bsp" + +LICENSE = "MIT" +LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302" + +SRC_URI = " \ + file://zynq-openamp.dtsi \ + file://zynq-openamp-overlay.dts \ + file://zynqmp-openamp.dtsi \ + file://zynqmp-openamp-overlay.dts \ + file://versal-openamp.dtsi \ + file://versal-openamp-overlay.dts \ + file://versal-net-openamp.dtsi \ + file://versal-net-openamp-overlay.dts \ +" + +# We don't have anything to include from the kernel +KERNEL_INCLUDE = "" + +COMPATIBLE_MACHINE:zynq = "${MACHINE}" +COMPATIBLE_MACHINE:zynqmp = "${MACHINE}" +COMPATIBLE_MACHINE:versal = "${MACHINE}" +COMPATIBLE_MACHINE:versal-net = "${MACHINE}" + +inherit devicetree image-artifact-names features_check + +REQUIRED_DISTRO_FEATURES = "openamp" + +# We are not _THE_ virtual/dtb provider +PROVIDES:remove = "virtual/dtb" + +DEPENDS += "python3-dtc-native" + +S = "${WORKDIR}/source" + +# Set a default so something resolves +SOC_FAMILY ??= "SOC_FAMILY" + +do_configure:prepend() { + mkdir -p source + + if [ -e ${WORKDIR}/${MACHINE}-openamp-overlay.dts ]; then + install ${WORKDIR}/${MACHINE}-openamp.dtsi ${WORKDIR}/source/. || : + install ${WORKDIR}/${MACHINE}-openamp-overlay.dts ${WORKDIR}/source/openamp.dts + elif [ -e ${WORKDIR}/${SOC_FAMILY}-openamp-overlay.dts ]; then + install ${WORKDIR}/${SOC_FAMILY}-openamp.dtsi ${WORKDIR}/source/. || : + install ${WORKDIR}/${SOC_FAMILY}-openamp-overlay.dts ${WORKDIR}/source/openamp.dts + else + bbfatal "${MACHINE}-openamp-overlay.dts or ${SOC_FAMILY}-openamp-overlay.dts file is not available. Cannot automatically add OpenAMP dtbo file." + fi +} + +FILES:${PN} = "/boot/devicetree/openamp.dtbo" |