diff options
Diffstat (limited to 'recipes-kernel/linux/linux-yocto/qrb4210-dts')
6 files changed, 872 insertions, 0 deletions
diff --git a/recipes-kernel/linux/linux-yocto/qrb4210-dts/0001-arm64-dts-qcom-qrb4210-rb2-Enable-MPSS-and-Wi-Fi.patch b/recipes-kernel/linux/linux-yocto/qrb4210-dts/0001-arm64-dts-qcom-qrb4210-rb2-Enable-MPSS-and-Wi-Fi.patch new file mode 100644 index 0000000..80ad1e6 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qrb4210-dts/0001-arm64-dts-qcom-qrb4210-rb2-Enable-MPSS-and-Wi-Fi.patch @@ -0,0 +1,86 @@ +From ff753723bf3916770c1e2580fe1f34ad9d6f0283 Mon Sep 17 00:00:00 2001 +From: Konrad Dybcio <konrad.dybcio@linaro.org> +Date: Sat, 4 Nov 2023 21:56:35 +0100 +Subject: [PATCH] arm64: dts: qcom: qrb4210-rb2: Enable MPSS and Wi-Fi + +Enable the remote processors and tighten up the regulators to enable +Wi-Fi functionality on the RB2. + +For reference, the hw/sw identifies as: + +qmi chip_id 0x150 chip_family 0x4002 board_id 0xff soc_id 0x40670000 +qmi fw_version 0x337302d3 fw_build_timestamp 2023-01-06 01:50 +fw_build_id QC_IMAGE_VERSION_STRING=WLAN.HL.3.3.7.c2-00723-QCAHLSWMTPLZ-1 +wcn3990 hw1.0 target 0x00000008 chip_id 0x00000000 sub 0000:0000 +kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0 +firmware ver api 5 features wowlan,mgmt-tx-by-reference,non-bmi +crc32 b3d4b790 +htt-ver 3.114 wmi-op 4 htt-op 3 cal file max-sta 32 raw 0 hwcrypto 1 + +Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Link: https://lore.kernel.org/r/20231104-topic-rb2_wifi-v1-1-fd45ae535d2f@linaro.org +Signed-off-by: Bjorn Andersson <andersson@kernel.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git ff753723bf3916770c1e2580fe1f34ad9d6f0283] +--- + arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 24 ++++++++++++++++++++---- + 1 file changed, 20 insertions(+), 4 deletions(-) + +diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +index 33c312ae842e..7c19f874fa71 100644 +--- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts ++++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +@@ -281,6 +281,12 @@ &remoteproc_cdsp { + status = "okay"; + }; + ++&remoteproc_mpss { ++ firmware-name = "qcom/qrb4210/modem.mbn"; ++ ++ status = "okay"; ++}; ++ + &rpm_requests { + regulators { + compatible = "qcom,rpm-pm6125-regulators"; +@@ -347,8 +353,8 @@ vreg_l7a_1p256: l7 { + }; + + vreg_l8a_0p664: l8 { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <728000>; ++ regulator-min-microvolt = <640000>; ++ regulator-max-microvolt = <640000>; + }; + + vreg_l9a_1p8: l9 { +@@ -428,8 +434,8 @@ vreg_l22a_2p96: l22 { + }; + + vreg_l23a_3p3: l23 { +- regulator-min-microvolt = <3200000>; +- regulator-max-microvolt = <3400000>; ++ regulator-min-microvolt = <3312000>; ++ regulator-max-microvolt = <3312000>; + regulator-allow-set-load; + }; + +@@ -620,6 +626,16 @@ &usb_qmpphy { + status = "okay"; + }; + ++&wifi { ++ vdd-0.8-cx-mx-supply = <&vreg_l8a_0p664>; ++ vdd-1.8-xo-supply = <&vreg_l16a_1p3>; ++ vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; ++ vdd-3.3-ch0-supply = <&vreg_l23a_3p3>; ++ qcom,ath10k-calibration-variant = "Thundercomm_RB2"; ++ ++ status = "okay"; ++}; ++ + &xo_board { + clock-frequency = <19200000>; + }; +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-yocto/qrb4210-dts/0001-arm64-dts-qcom-sm6115-Add-UART3.patch b/recipes-kernel/linux/linux-yocto/qrb4210-dts/0001-arm64-dts-qcom-sm6115-Add-UART3.patch new file mode 100644 index 0000000..385e1b2 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qrb4210-dts/0001-arm64-dts-qcom-sm6115-Add-UART3.patch @@ -0,0 +1,66 @@ +From ba5f5610841fad3b15c69c6949ed6e19bd5b466e Mon Sep 17 00:00:00 2001 +From: Konrad Dybcio <konrad.dybcio@linaro.org> +Date: Mon, 27 Nov 2023 12:23:27 +0100 +Subject: [PATCH 1/2] arm64: dts: qcom: sm6115: Add UART3 + +Hook up UART3, usually used for communicating with a Bluetooth module. + +Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Link: https://lore.kernel.org/r/20231120-topic-rb2_bt-v2-1-4bbf266258ef@linaro.org +Signed-off-by: Bjorn Andersson <andersson@kernel.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git ba5f5610841fad3b15c69c6949ed6e19bd5b466e] +--- + arch/arm64/boot/dts/qcom/sm6115.dtsi | 30 ++++++++++++++++++++++++++++ + 1 file changed, 30 insertions(+) + +diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi +index 839c60351240..0d13d7bf6bd1 100644 +--- a/arch/arm64/boot/dts/qcom/sm6115.dtsi ++++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi +@@ -273,6 +273,25 @@ memory@80000000 { + reg = <0 0x80000000 0 0>; + }; + ++ qup_opp_table: opp-table-qup { ++ compatible = "operating-points-v2"; ++ ++ opp-75000000 { ++ opp-hz = /bits/ 64 <75000000>; ++ required-opps = <&rpmpd_opp_low_svs>; ++ }; ++ ++ opp-100000000 { ++ opp-hz = /bits/ 64 <100000000>; ++ required-opps = <&rpmpd_opp_svs>; ++ }; ++ ++ opp-128000000 { ++ opp-hz = /bits/ 64 <128000000>; ++ required-opps = <&rpmpd_opp_nom>; ++ }; ++ }; ++ + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; +@@ -1208,6 +1227,17 @@ spi3: spi@4a8c000 { + status = "disabled"; + }; + ++ uart3: serial@4a8c000 { ++ compatible = "qcom,geni-uart"; ++ reg = <0x0 0x04a8c000 0x0 0x4000>; ++ interrupts-extended = <&intc GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; ++ clock-names = "se"; ++ power-domains = <&rpmpd SM6115_VDDCX>; ++ operating-points-v2 = <&qup_opp_table>; ++ status = "disabled"; ++ }; ++ + i2c4: i2c@4a90000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a90000 0x0 0x4000>; +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-yocto/qrb4210-dts/0001-arm64-dts-qcom-sm6115-Hook-up-interconnects.patch b/recipes-kernel/linux/linux-yocto/qrb4210-dts/0001-arm64-dts-qcom-sm6115-Hook-up-interconnects.patch new file mode 100644 index 0000000..a3c3832 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qrb4210-dts/0001-arm64-dts-qcom-sm6115-Hook-up-interconnects.patch @@ -0,0 +1,475 @@ +From b3eaa47395b9d0fc593e7f8b8b0abb4c769ad30d Mon Sep 17 00:00:00 2001 +From: Konrad Dybcio <konrad.dybcio@linaro.org> +Date: Mon, 11 Dec 2023 10:23:59 +0100 +Subject: [PATCH] arm64: dts: qcom: sm6115: Hook up interconnects + +Add interconnect provider nodes and hook up interconnects to consumer +devices, including bwmon. + +Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Link: https://lore.kernel.org/r/20231209-topic-6115iccdt-v1-2-f62da62b7276@linaro.org +Signed-off-by: Bjorn Andersson <andersson@kernel.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git b3eaa47395b9d0fc593e7f8b8b0abb4c769ad30d] +--- + arch/arm64/boot/dts/qcom/sm6115.dtsi | 277 +++++++++++++++++++++++++++ + 1 file changed, 277 insertions(+) + +diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi +index 72a833b7cd83..160e098f1075 100644 +--- a/arch/arm64/boot/dts/qcom/sm6115.dtsi ++++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi +@@ -10,6 +10,8 @@ + #include <dt-bindings/dma/qcom-gpi.h> + #include <dt-bindings/firmware/qcom,scm.h> + #include <dt-bindings/gpio/gpio.h> ++#include <dt-bindings/interconnect/qcom,rpm-icc.h> ++#include <dt-bindings/interconnect/qcom,sm6115.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/qcom-rpmpd.h> + +@@ -264,6 +266,8 @@ firmware { + scm: scm { + compatible = "qcom,scm-sm6115", "qcom,scm"; + #reset-cells = <1>; ++ interconnects = <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + }; + }; + +@@ -878,6 +882,43 @@ usb_qmpphy: phy@1615000 { + status = "disabled"; + }; + ++ system_noc: interconnect@1880000 { ++ compatible = "qcom,sm6115-snoc"; ++ reg = <0x0 0x01880000 0x0 0x5f080>; ++ clocks = <&gcc GCC_SYS_NOC_CPUSS_AHB_CLK>, ++ <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, ++ <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, ++ <&rpmcc RPM_SMD_IPA_CLK>; ++ clock-names = "cpu_axi", ++ "ufs_axi", ++ "usb_axi", ++ "ipa"; ++ #interconnect-cells = <2>; ++ ++ clk_virt: interconnect-clk { ++ compatible = "qcom,sm6115-clk-virt"; ++ #interconnect-cells = <2>; ++ }; ++ ++ mmrt_virt: interconnect-mmrt { ++ compatible = "qcom,sm6115-mmrt-virt"; ++ #interconnect-cells = <2>; ++ }; ++ ++ mmnrt_virt: interconnect-mmnrt { ++ compatible = "qcom,sm6115-mmnrt-virt"; ++ #interconnect-cells = <2>; ++ }; ++ }; ++ ++ config_noc: interconnect@1900000 { ++ compatible = "qcom,sm6115-cnoc"; ++ reg = <0x0 0x01900000 0x0 0x6200>; ++ clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>; ++ clock-names = "usb_axi"; ++ #interconnect-cells = <2>; ++ }; ++ + qfprom@1b40000 { + compatible = "qcom,sm6115-qfprom", "qcom,qfprom"; + reg = <0x0 0x01b40000 0x0 0x7000>; +@@ -902,6 +943,60 @@ rng: rng@1b53000 { + clock-names = "core"; + }; + ++ pmu@1b8e300 { ++ compatible = "qcom,sm6115-cpu-bwmon", "qcom,sdm845-bwmon"; ++ reg = <0x0 0x01b8e300 0x0 0x600>; ++ interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; ++ ++ operating-points-v2 = <&cpu_bwmon_opp_table>; ++ interconnects = <&bimc MASTER_AMPSS_M0 RPM_ACTIVE_TAG ++ &bimc SLAVE_EBI_CH0 RPM_ACTIVE_TAG>; ++ ++ cpu_bwmon_opp_table: opp-table { ++ compatible = "operating-points-v2"; ++ ++ opp-0 { ++ opp-peak-kBps = <(200 * 4 * 1000)>; ++ }; ++ ++ opp-1 { ++ opp-peak-kBps = <(300 * 4 * 1000)>; ++ }; ++ ++ opp-2 { ++ opp-peak-kBps = <(451 * 4 * 1000)>; ++ }; ++ ++ opp-3 { ++ opp-peak-kBps = <(547 * 4 * 1000)>; ++ }; ++ ++ opp-4 { ++ opp-peak-kBps = <(681 * 4 * 1000)>; ++ }; ++ ++ opp-5 { ++ opp-peak-kBps = <(768 * 4 * 1000)>; ++ }; ++ ++ opp-6 { ++ opp-peak-kBps = <(1017 * 4 * 1000)>; ++ }; ++ ++ opp-7 { ++ opp-peak-kBps = <(1353 * 4 * 1000)>; ++ }; ++ ++ opp-8 { ++ opp-peak-kBps = <(1555 * 4 * 1000)>; ++ }; ++ ++ opp-9 { ++ opp-peak-kBps = <(1804 * 4 * 1000)>; ++ }; ++ }; ++ }; ++ + spmi_bus: spmi@1c40000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0 0x01c40000 0x0 0x1100>, +@@ -931,6 +1026,12 @@ tsens0: thermal-sensor@4411000 { + #thermal-sensor-cells = <1>; + }; + ++ bimc: interconnect@4480000 { ++ compatible = "qcom,sm6115-bimc"; ++ reg = <0x0 0x04480000 0x0 0x80000>; ++ #interconnect-cells = <2>; ++ }; ++ + rpm_msg_ram: sram@45f0000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x0 0x045f0000 0x0 0x7000>; +@@ -958,8 +1059,42 @@ sdhc_1: mmc@4744000 { + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "iface", "core", "xo", "ice"; + ++ power-domains = <&rpmpd SM6115_VDDCX>; ++ operating-points-v2 = <&sdhc1_opp_table>; ++ interconnects = <&system_noc MASTER_SDCC_1 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG ++ &config_noc SLAVE_SDCC_1 RPM_ALWAYS_TAG>; ++ interconnect-names = "sdhc-ddr", ++ "cpu-sdhc"; ++ + bus-width = <8>; + status = "disabled"; ++ ++ sdhc1_opp_table: opp-table { ++ compatible = "operating-points-v2"; ++ ++ opp-100000000 { ++ opp-hz = /bits/ 64 <100000000>; ++ required-opps = <&rpmpd_opp_low_svs>; ++ opp-peak-kBps = <250000 133320>; ++ opp-avg-kBps = <102400 65000>; ++ }; ++ ++ opp-192000000 { ++ opp-hz = /bits/ 64 <192000000>; ++ required-opps = <&rpmpd_opp_low_svs>; ++ opp-peak-kBps = <800000 300000>; ++ opp-avg-kBps = <204800 200000>; ++ }; ++ ++ opp-384000000 { ++ opp-hz = /bits/ 64 <384000000>; ++ required-opps = <&rpmpd_opp_svs_plus>; ++ opp-peak-kBps = <800000 300000>; ++ opp-avg-kBps = <204800 200000>; ++ }; ++ }; + }; + + sdhc_2: mmc@4784000 { +@@ -980,6 +1115,12 @@ sdhc_2: mmc@4784000 { + operating-points-v2 = <&sdhc2_opp_table>; + iommus = <&apps_smmu 0x00a0 0x0>; + resets = <&gcc GCC_SDCC2_BCR>; ++ interconnects = <&system_noc MASTER_SDCC_2 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG ++ &config_noc SLAVE_SDCC_2 RPM_ALWAYS_TAG>; ++ interconnect-names = "sdhc-ddr", ++ "cpu-sdhc"; + + bus-width = <4>; + qcom,dll-config = <0x0007642c>; +@@ -992,11 +1133,15 @@ sdhc2_opp_table: opp-table { + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmpd_opp_low_svs>; ++ opp-peak-kBps = <250000 133320>; ++ opp-avg-kBps = <261438 150000>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmpd_opp_nom>; ++ opp-peak-kBps = <800000 300000>; ++ opp-avg-kBps = <261438 300000>; + }; + }; + }; +@@ -1103,6 +1248,15 @@ i2c0: i2c@4a80000 { + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; ++ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG ++ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, ++ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; ++ interconnect-names = "qup-core", ++ "qup-config", ++ "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -1119,6 +1273,15 @@ spi0: spi@4a80000 { + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; ++ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG ++ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, ++ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; ++ interconnect-names = "qup-core", ++ "qup-config", ++ "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -1135,6 +1298,12 @@ i2c1: i2c@4a84000 { + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; ++ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG ++ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, ++ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -1151,6 +1320,15 @@ spi1: spi@4a84000 { + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; ++ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG ++ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, ++ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; ++ interconnect-names = "qup-core", ++ "qup-config", ++ "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -1167,6 +1345,15 @@ i2c2: i2c@4a88000 { + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; ++ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG ++ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, ++ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; ++ interconnect-names = "qup-core", ++ "qup-config", ++ "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -1183,6 +1370,15 @@ spi2: spi@4a88000 { + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; ++ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG ++ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, ++ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; ++ interconnect-names = "qup-core", ++ "qup-config", ++ "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -1199,6 +1395,15 @@ i2c3: i2c@4a8c000 { + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; ++ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG ++ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, ++ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; ++ interconnect-names = "qup-core", ++ "qup-config", ++ "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -1215,6 +1420,15 @@ spi3: spi@4a8c000 { + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, + <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; ++ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG ++ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, ++ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; ++ interconnect-names = "qup-core", ++ "qup-config", ++ "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -1228,6 +1442,12 @@ uart3: serial@4a8c000 { + clock-names = "se"; + power-domains = <&rpmpd SM6115_VDDCX>; + operating-points-v2 = <&qup_opp_table>; ++ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG ++ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; ++ interconnect-names = "qup-core", ++ "qup-config"; + status = "disabled"; + }; + +@@ -1242,6 +1462,15 @@ i2c4: i2c@4a90000 { + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; ++ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG ++ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, ++ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; ++ interconnect-names = "qup-core", ++ "qup-config", ++ "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -1258,6 +1487,15 @@ spi4: spi@4a90000 { + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, + <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; ++ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG ++ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, ++ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; ++ interconnect-names = "qup-core", ++ "qup-config", ++ "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -1269,6 +1507,12 @@ uart4: serial@4a90000 { + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; ++ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG ++ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; ++ interconnect-names = "qup-core", ++ "qup-config"; + status = "disabled"; + }; + +@@ -1283,6 +1527,15 @@ i2c5: i2c@4a94000 { + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; ++ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG ++ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, ++ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; ++ interconnect-names = "qup-core", ++ "qup-config", ++ "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -1299,6 +1552,15 @@ spi5: spi@4a94000 { + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; ++ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG ++ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, ++ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; ++ interconnect-names = "qup-core", ++ "qup-config", ++ "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -1330,6 +1592,14 @@ usb: usb@4ef8800 { + + resets = <&gcc GCC_USB30_PRIM_BCR>; + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; ++ /* TODO: USB<->IPA path */ ++ interconnects = <&system_noc MASTER_USB3 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG ++ &config_noc SLAVE_USB3 RPM_ALWAYS_TAG>; ++ interconnect-names = "usb-ddr", ++ "apps-usb"; ++ + qcom,select-utmi-as-pipe-clk; + status = "disabled"; + +@@ -1501,6 +1771,13 @@ mdss: display-subsystem@5e00000 { + iommus = <&apps_smmu 0x420 0x2>, + <&apps_smmu 0x421 0x0>; + ++ interconnects = <&mmrt_virt MASTER_MDP_PORT0 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG ++ &config_noc SLAVE_DISPLAY_CFG RPM_ALWAYS_TAG>; ++ interconnect-names = "mdp0-mem", ++ "cpu-cfg"; ++ + #address-cells = <2>; + #size-cells = <2>; + ranges; +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-yocto/qrb4210-dts/0002-arm64-dts-qcom-qrb4210-rb2-Enable-bluetooth.patch b/recipes-kernel/linux/linux-yocto/qrb4210-dts/0002-arm64-dts-qcom-qrb4210-rb2-Enable-bluetooth.patch new file mode 100644 index 0000000..d70ef6a --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qrb4210-dts/0002-arm64-dts-qcom-qrb4210-rb2-Enable-bluetooth.patch @@ -0,0 +1,162 @@ +From cab60b166575dd6db4c85487e87a9b677e04c153 Mon Sep 17 00:00:00 2001 +From: Konrad Dybcio <konrad.dybcio@linaro.org> +Date: Mon, 27 Nov 2023 12:23:28 +0100 +Subject: [PATCH 2/2] arm64: dts: qcom: qrb4210-rb2: Enable bluetooth + +Enable the QCA bluetooth on RB2. It identifies like the following: + +Bluetooth: hci0: QCA Product ID :0x0000000a +Bluetooth: hci0: QCA SOC Version :0x40020150 +Bluetooth: hci0: QCA ROM Version :0x00000201 +Bluetooth: hci0: QCA Patch Version:0x00000001 +Bluetooth: hci0: QCA controller version 0x01500201 + +Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Link: https://lore.kernel.org/r/20231120-topic-rb2_bt-v2-2-4bbf266258ef@linaro.org +Signed-off-by: Bjorn Andersson <andersson@kernel.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git cab60b166575dd6db4c85487e87a9b677e04c153] +--- + arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 87 +++++++++++++++++++++++- + 1 file changed, 86 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +index 9738c0dacd58..33c312ae842e 100644 +--- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts ++++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +@@ -15,6 +15,7 @@ / { + + aliases { + serial0 = &uart4; ++ serial1 = &uart3; + }; + + chosen { +@@ -352,7 +353,8 @@ vreg_l8a_0p664: l8 { + + vreg_l9a_1p8: l9 { + regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2000000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-allow-set-load; + }; + + vreg_l10a_1p8: l10 { +@@ -389,11 +391,13 @@ vreg_l15a_3p128: l15 { + vreg_l16a_1p3: l16 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; ++ regulator-allow-set-load; + }; + + vreg_l17a_1p3: l17 { + regulator-min-microvolt = <1152000>; + regulator-max-microvolt = <1384000>; ++ regulator-allow-set-load; + }; + + vreg_l18a_1p232: l18 { +@@ -426,6 +430,7 @@ vreg_l22a_2p96: l22 { + vreg_l23a_3p3: l23 { + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3400000>; ++ regulator-allow-set-load; + }; + + vreg_l24a_2p96: l24 { +@@ -487,6 +492,66 @@ &tlmm { + <56 3>, <61 2>, <64 1>, + <68 1>, <72 8>, <96 1>; + ++ uart3_default: uart3-default-state { ++ cts-pins { ++ pins = "gpio8"; ++ function = "qup3"; ++ drive-strength = <2>; ++ bias-bus-hold; ++ }; ++ ++ rts-pins { ++ pins = "gpio9"; ++ function = "qup3"; ++ drive-strength = <2>; ++ bias-disable; ++ }; ++ ++ tx-pins { ++ pins = "gpio10"; ++ function = "qup3"; ++ drive-strength = <2>; ++ bias-disable; ++ }; ++ ++ rx-pins { ++ pins = "gpio11"; ++ function = "qup3"; ++ drive-strength = <2>; ++ bias-pull-up; ++ }; ++ }; ++ ++ uart3_sleep: uart3-sleep-state { ++ cts-pins { ++ pins = "gpio8"; ++ function = "gpio"; ++ drive-strength = <2>; ++ bias-bus-hold; ++ }; ++ ++ rts-pins { ++ pins = "gpio9"; ++ function = "gpio"; ++ drive-strength = <2>; ++ bias-pull-down; ++ }; ++ ++ tx-pins { ++ pins = "gpio10"; ++ function = "gpio"; ++ drive-strength = <2>; ++ bias-pull-up; ++ }; ++ ++ rx-pins { ++ pins = "gpio11"; ++ function = "gpio"; ++ drive-strength = <2>; ++ bias-pull-up; ++ }; ++ }; ++ + lt9611_rst_pin: lt9611-rst-state { + pins = "gpio41"; + function = "gpio"; +@@ -508,6 +573,26 @@ sdc2_card_det_n: sd-card-det-n-state { + }; + }; + ++&uart3 { ++ interrupts-extended = <&intc GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, ++ <&tlmm 11 IRQ_TYPE_LEVEL_HIGH>; ++ pinctrl-0 = <&uart3_default>; ++ pinctrl-1 = <&uart3_sleep>; ++ pinctrl-names = "default", "sleep"; ++ status = "okay"; ++ ++ bluetooth { ++ compatible = "qcom,wcn3988-bt"; ++ ++ vddio-supply = <&vreg_l9a_1p8>; ++ vddxo-supply = <&vreg_l16a_1p3>; ++ vddrf-supply = <&vreg_l17a_1p3>; ++ vddch0-supply = <&vreg_l23a_3p3>; ++ enable-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; ++ max-speed = <3200000>; ++ }; ++}; ++ + &uart4 { + status = "okay"; + }; +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-yocto/qrb4210-dts/usb/0002-arm64-dts-qcom-qrb4210-rb2-Select-USB3-host-mode-by-.patch b/recipes-kernel/linux/linux-yocto/qrb4210-dts/usb/0002-arm64-dts-qcom-qrb4210-rb2-Select-USB3-host-mode-by-.patch new file mode 100644 index 0000000..15f9507 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qrb4210-dts/usb/0002-arm64-dts-qcom-qrb4210-rb2-Select-USB3-host-mode-by-.patch @@ -0,0 +1,30 @@ +From 89293aa2737299d021d42fef649bdcd191953a0b Mon Sep 17 00:00:00 2001 +From: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> +Date: Tue, 21 Nov 2023 13:22:49 +0200 +Subject: [PATCH 2/3] arm64: dts: qcom: qrb4210-rb2: Select USB3 host mode by + default + +The USB3 controller mode is selected by on-board DIP switches, and +by default it is set to the host mode, specify the selection. + +Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> +Upstream-Status: Pending +--- + arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +index 7c19f874fa71..97344508c94f 100644 +--- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts ++++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +@@ -609,6 +609,7 @@ &usb { + + &usb_dwc3 { + maximum-speed = "super-speed"; ++ dr_mode = "host"; + }; + + &usb_hsphy { +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-yocto/qrb4210-dts/usb/0003-arm64-dts-qcom-sm6115-Enable-USB3-SS-phy.patch b/recipes-kernel/linux/linux-yocto/qrb4210-dts/usb/0003-arm64-dts-qcom-sm6115-Enable-USB3-SS-phy.patch new file mode 100644 index 0000000..fd344bc --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qrb4210-dts/usb/0003-arm64-dts-qcom-sm6115-Enable-USB3-SS-phy.patch @@ -0,0 +1,53 @@ +From 3d1bd03aa758d8766f3d7e3cae8aa24d9fe0bf09 Mon Sep 17 00:00:00 2001 +From: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> +Date: Tue, 21 Nov 2023 13:20:18 +0200 +Subject: [PATCH 3/3] arm64: dts: qcom: sm6115: Enable USB3 SS phy + +There is no reason to limit USB3 controller to USB2 functionality, +moreover it fixes a contradiction with the selected super-speed +mode on RB2 board. Additionally specify the OTG function in the SoC +specific description. + +Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> +Upstream-Status: Pending +--- + arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 1 - + arch/arm64/boot/dts/qcom/sm6115.dtsi | 3 ++- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +index 97344508c94f..549f36276269 100644 +--- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts ++++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +@@ -608,7 +608,6 @@ &usb { + }; + + &usb_dwc3 { +- maximum-speed = "super-speed"; + dr_mode = "host"; + }; + +diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi +index ca49e8c7f6e6..3680dc203263 100644 +--- a/arch/arm64/boot/dts/qcom/sm6115.dtsi ++++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi +@@ -1607,7 +1607,6 @@ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, + interconnect-names = "usb-ddr", + "apps-usb"; + +- qcom,select-utmi-as-pipe-clk; + status = "disabled"; + + usb_dwc3: usb@4e00000 { +@@ -1622,6 +1621,8 @@ usb_dwc3: usb@4e00000 { + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; ++ maximum-speed = "super-speed"; ++ dr_mode = "otg"; + }; + }; + +-- +2.39.2 + |