diff options
Diffstat (limited to 'meta-r1000/recipes-kernel')
32 files changed, 2400 insertions, 0 deletions
diff --git a/meta-r1000/recipes-kernel/amd-spi/amd-spi_1.0.bb b/meta-r1000/recipes-kernel/amd-spi/amd-spi_1.0.bb new file mode 100644 index 00000000..b23e5ce6 --- /dev/null +++ b/meta-r1000/recipes-kernel/amd-spi/amd-spi_1.0.bb @@ -0,0 +1,16 @@ +DESCRIPTION = "This kernel module provides support for AMD SPI controller driver" +LICENSE = "BSD | GPLv2" +LIC_FILES_CHKSUM = "file://spi_amd.c;endline=29;md5=e9fdf6da58412e619d89ec9e135a1be3" + +inherit module + +SRC_URI = "file://Makefile \ + file://spi_amd.c \ + file://spi_amd.h \ + file://spirom.c \ + file://spirom.h \ + " + +S = "${WORKDIR}" + +# The inherit of module.bbclass will take care of the rest diff --git a/meta-r1000/recipes-kernel/amd-spi/files/Makefile b/meta-r1000/recipes-kernel/amd-spi/files/Makefile new file mode 100644 index 00000000..f778a69a --- /dev/null +++ b/meta-r1000/recipes-kernel/amd-spi/files/Makefile @@ -0,0 +1,14 @@ +obj-m := spi_amd.o spirom.o + +SRC := $(shell pwd) + +all: + $(MAKE) -C $(KERNEL_SRC) M=$(SRC) + +modules_install: + $(MAKE) -C $(KERNEL_SRC) M=$(SRC) modules_install + +clean: + rm -f *.o *~ core .depend .*.cmd *.ko *.mod.c + rm -f Module.markers Module.symvers modules.order + rm -rf .tmp_versions Modules.symvers diff --git a/meta-r1000/recipes-kernel/amd-spi/files/spi_amd.c b/meta-r1000/recipes-kernel/amd-spi/files/spi_amd.c new file mode 100644 index 00000000..998d9ea6 --- /dev/null +++ b/meta-r1000/recipes-kernel/amd-spi/files/spi_amd.c @@ -0,0 +1,479 @@ +/***************************************************************************** +* +* Copyright (c) 2013, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +***************************************************************************/ +#include <linux/init.h> +#include <linux/module.h> +#include <linux/pci.h> +#include <linux/spi/spi.h> +#include <linux/kthread.h> + +#include "spi_amd.h" + +struct amd_platform_data { + u8 chip_select; +}; + +struct amd_spi { + void __iomem *io_remap_addr; + unsigned long io_base_addr; + u32 rom_addr; + struct spi_master *master; + struct amd_platform_data controller_data; + struct task_struct *kthread_spi; + struct list_head msg_queue; + wait_queue_head_t wq; +}; + +static struct pci_device_id amd_spi_pci_device_id[] = { + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LPC_BRIDGE) }, + {} +}; +MODULE_DEVICE_TABLE(pci, amd_spi_pci_device_id); + +static inline u8 amd_spi_readreg8(struct spi_master *master, int idx) +{ + struct amd_spi *amd_spi = spi_master_get_devdata(master); + + return ioread8((u8 *)amd_spi->io_remap_addr + idx); +} + +static inline void amd_spi_writereg8(struct spi_master *master, int idx, + u8 val) +{ + struct amd_spi *amd_spi = spi_master_get_devdata(master); + + iowrite8(val, ((u8 *)amd_spi->io_remap_addr + idx)); +} + +static inline void amd_spi_setclear_reg8(struct spi_master *master, int idx, + u8 set, u8 clear) +{ + u8 tmp = amd_spi_readreg8(master, idx); + tmp = (tmp & ~clear) | set; + amd_spi_writereg8(master, idx, tmp); +} + +static inline u32 amd_spi_readreg32(struct spi_master *master, int idx) +{ + struct amd_spi *amd_spi = spi_master_get_devdata(master); + + return ioread32((u8 *)amd_spi->io_remap_addr + idx); +} + +static inline void amd_spi_writereg32(struct spi_master *master, int idx, + u32 val) +{ + struct amd_spi *amd_spi = spi_master_get_devdata(master); + + iowrite32(val, ((u8 *)amd_spi->io_remap_addr + idx)); +} + +static inline void amd_spi_setclear_reg32(struct spi_master *master, int idx, + u32 set, u32 clear) +{ + u32 tmp = amd_spi_readreg32(master, idx); + tmp = (tmp & ~clear) | set; + amd_spi_writereg32(master, idx, tmp); +} + +static void amd_spi_select_chip(struct spi_master *master) +{ + struct amd_spi *amd_spi = spi_master_get_devdata(master); + u8 chip_select = amd_spi->controller_data.chip_select; + + amd_spi_setclear_reg8(master, AMD_SPI_ALT_CS_REG, chip_select, + AMD_SPI_ALT_CS_MASK); +} + + +static void amd_spi_clear_fifo_ptr(struct spi_master *master) +{ + amd_spi_setclear_reg32(master, AMD_SPI_CTRL0_REG, AMD_SPI_FIFO_CLEAR, + AMD_SPI_FIFO_CLEAR); +} + +static void amd_spi_set_opcode(struct spi_master *master, u8 cmd_opcode) +{ + amd_spi_setclear_reg32(master, AMD_SPI_CTRL0_REG, cmd_opcode, + AMD_SPI_OPCODE_MASK); +} + +static inline void amd_spi_set_rx_count(struct spi_master *master, + u8 rx_count) +{ + amd_spi_setclear_reg8(master, AMD_SPI_RX_COUNT_REG, rx_count, 0xff); +} + +static inline void amd_spi_set_tx_count(struct spi_master *master, + u8 tx_count) +{ + amd_spi_setclear_reg8(master, AMD_SPI_TX_COUNT_REG, tx_count, 0xff); +} + +static void amd_spi_execute_opcode(struct spi_master *master) +{ + struct amd_spi *amd_spi = spi_master_get_devdata(master); + bool spi_busy; + + /* Set ExecuteOpCode bit in the CTRL0 register */ + amd_spi_setclear_reg32(master, AMD_SPI_CTRL0_REG, AMD_SPI_EXEC_CMD, + AMD_SPI_EXEC_CMD); + + /* poll for SPI bus to become idle */ + spi_busy = (ioread32((u8 *)amd_spi->io_remap_addr + + AMD_SPI_CTRL0_REG) & AMD_SPI_BUSY) == AMD_SPI_BUSY; + while (spi_busy) { + set_current_state(TASK_INTERRUPTIBLE); + schedule(); + set_current_state(TASK_RUNNING); + spi_busy = (ioread32((u8 *)amd_spi->io_remap_addr + + AMD_SPI_CTRL0_REG) & AMD_SPI_BUSY) == AMD_SPI_BUSY; + } +} + +/* Helper function */ +#ifdef CONFIG_SPI_DEBUG +static void amd_spi_dump_reg(struct spi_master *master) +{ + struct amd_spi *amd_spi = spi_master_get_devdata(master); + + printk(KERN_DEBUG DRIVER_NAME ": SPI CTRL 0 registers: 0x%.8x\n", + ioread32((u8 *)amd_spi->io_remap_addr + AMD_SPI_CTRL0_REG)); + /* + * We cannot read CTRL1 register, because reading it would + * inadvertently increment the FIFO pointer. + */ + printk(KERN_DEBUG DRIVER_NAME ": SPI ALT CS registers: 0x%.2x\n", + ioread8((u8 *)amd_spi->io_remap_addr + AMD_SPI_ALT_CS_REG)); + printk(KERN_DEBUG DRIVER_NAME ": SPI Tx Byte Count: 0x%.2x\n", + ioread8((u8 *)amd_spi->io_remap_addr + AMD_SPI_TX_COUNT_REG)); + printk(KERN_DEBUG DRIVER_NAME ": SPI Rx Byte Count: 0x%.2x\n", + ioread8((u8 *)amd_spi->io_remap_addr + AMD_SPI_RX_COUNT_REG)); + printk(KERN_DEBUG DRIVER_NAME ": SPI Status registers: 0x%.8x\n", + ioread32((u8 *)amd_spi->io_remap_addr + AMD_SPI_STATUS_REG)); +} +#else +static void amd_spi_dump_reg(struct spi_master *master) {} +#endif + + +static int amd_spi_master_setup(struct spi_device *spi) +{ + struct spi_master *master = spi->master; + struct amd_spi *amd_spi = spi_master_get_devdata(master); + + amd_spi->controller_data.chip_select = spi->chip_select; + + amd_spi_select_chip(master); + + return 0; +} + +static int amd_spi_master_transfer(struct spi_master *master, + struct spi_message *msg) +{ + struct amd_spi *amd_spi = spi_master_get_devdata(master); + + /* + * Add new message to the queue and let the kernel thread know + * about it. + */ + list_add_tail(&msg->queue, &amd_spi->msg_queue); + wake_up_interruptible(&amd_spi->wq); + + return 0; +} +static int amd_spi_thread(void *t) +{ + struct amd_spi *amd_spi = t; + struct spi_master *master = amd_spi->master; + struct spi_transfer *transfer = NULL; + struct spi_message *message = NULL; + int direction = 0,i = 0,saved_index = 0; + int opcode_found = 0,recv_flag = 0,tx_len = 0,rx_len = 0; + u8 cmd_opcode = 0; + long timeout = 0; + u8 *buffer = NULL; + + /* + * What we do here is actually pretty simple. We pick one message + * at a time from the message queue set up by the controller, and + * then process all the spi_transfers of that spi_message in one go. + * We then remove the message from the queue, and complete the + * transaction. This might not be the best approach, but this is how + * we chose to implement this. Note that out SPI controller has FIFO + * size of 70 bytes, but we consider it to contain a maximum of + * 64-bytes of data and 3-bytes of address. + */ + while (1) { + /* + * Let us wait on a wait queue till the message queue is empty. + */ + do { + timeout = wait_event_interruptible_timeout(amd_spi->wq, + !list_empty(&amd_spi->msg_queue),1000); + + /* check stop condition */ + if (kthread_should_stop()) { + set_current_state(TASK_RUNNING); + return 0; + } + } while(timeout == 0); + + /* + * Else, pull the very first message from the queue and process + * all transfers within that message. And process the messages + * in a pure linear fashion. We also remove the spi_message + * from the queue. + */ + message = list_entry(amd_spi->msg_queue.next, + struct spi_message, queue); + list_del_init(&message->queue); + + /* We store the CS# line to be used for this spi_message */ + amd_spi->controller_data.chip_select = + message->spi->chip_select; + + /* Setting all variables to default value. */ + direction = i = 0; + opcode_found = 0; + recv_flag = tx_len = rx_len = 0; + cmd_opcode = 0; + buffer = NULL; + saved_index = 0; + + amd_spi_select_chip(master); + + /* + * This loop extracts spi_transfers from the spi message, + * programs the command into command register. Pointer variable + * *buffer* points to either tx_buf or rx_buf of spi_transfer + * depending on direction of transfer. Also programs FIFO of + * controller if data has to be transmitted. + */ + list_for_each_entry(transfer, &message->transfers, + transfer_list) + { + if(transfer->rx_buf != NULL) + direction = RECEIVE; + else if(transfer->tx_buf != NULL) + direction = TRANSMIT; + + switch (direction) { + case TRANSMIT: + buffer = (u8 *)transfer->tx_buf; + + if(opcode_found != 1) { + /* Store no. of bytes to be sent into + * FIFO */ + tx_len = transfer->len - 1; + /* Store opcode */ + cmd_opcode = *(u8 *)transfer->tx_buf; + /* Pointing to start of TX data */ + buffer++; + /* Program the command register*/ + amd_spi_set_opcode(master, cmd_opcode); + opcode_found = 1; + } else { + /* Store no. of bytes to be sent into + * FIFO */ + tx_len = transfer->len; + } + + /* Write data into the FIFO. */ + for (i = 0; i < tx_len; i++) { + iowrite8(buffer[i], + ((u8 *)amd_spi->io_remap_addr + + AMD_SPI_FIFO_BASE + + i + saved_index)); + } + + /* Set no. of bytes to be transmitted */ + amd_spi_set_tx_count(master, + tx_len + saved_index); + + /* + * Saving the index, from where next + * spi_transfer's data will be stored in FIFO. + */ + saved_index = i; + break; + case RECEIVE: + /* Store no. of bytes to be received from + * FIFO */ + rx_len = transfer->len; + buffer = (u8 *)transfer->rx_buf; + recv_flag=1; + break; + } + } + + /* Set the RX count to the number of bytes to expect in + * response */ + amd_spi_set_rx_count(master, rx_len ); + amd_spi_clear_fifo_ptr(master); + amd_spi_dump_reg(master); + /* Executing command */ + amd_spi_execute_opcode(master); + amd_spi_dump_reg(master); + + if(recv_flag == 1) { + /* Read data from FIFO to receive buffer */ + for (i = 0; i < rx_len; i++) { + buffer[i] = ioread8((u8 *)amd_spi->io_remap_addr + + AMD_SPI_FIFO_BASE + + tx_len + i); + } + + recv_flag = 0; + } + + /* Update statistics */ + message->actual_length = tx_len + rx_len + 1 ; + /* complete the transaction */ + message->status = 0; + spi_finalize_current_message(master); + } + + return 0; +} + +static int amd_spi_pci_probe(struct pci_dev *pdev, + const struct pci_device_id *id) +{ + struct device *dev = &pdev->dev; + struct spi_master *master; + struct amd_spi *amd_spi; + u32 io_base_addr; + int err = 0; + + /* Allocate storage for spi_master and driver private data */ + master = spi_alloc_master(dev, sizeof(struct amd_spi)); + if (master == NULL) { + dev_err(dev, "Error allocating SPI master\n"); + return -ENOMEM; + } + + amd_spi = spi_master_get_devdata(master); + amd_spi->master = master; + + /* + * Lets first get the base address of SPI registers. The SPI Base + * Address is stored at offset 0xA0 into the LPC PCI configuration + * space. As per the specification, it is stored at bits 6:31 of the + * register. The address is aligned at 64-byte boundary, + * so we should just mask the lower 6 bits and get the address. + */ + pci_read_config_dword(pdev, AMD_PCI_LPC_SPI_BASE_ADDR_REG, + &io_base_addr); + amd_spi->io_base_addr = io_base_addr & AMD_SPI_BASE_ADDR_MASK; + amd_spi->io_remap_addr = ioremap_nocache(amd_spi->io_base_addr, + AMD_SPI_MEM_SIZE); + if (amd_spi->io_remap_addr == NULL) { + dev_err(dev, "ioremap of SPI registers failed\n"); + err = -ENOMEM; + goto err_free_master; + } + dev_dbg(dev, "io_base_addr: 0x%.8lx, io_remap_address: %p\n", + amd_spi->io_base_addr, amd_spi->io_remap_addr); + INIT_LIST_HEAD(&amd_spi->msg_queue); + init_waitqueue_head(&amd_spi->wq); + amd_spi->kthread_spi = kthread_run(amd_spi_thread, amd_spi, + "amd_spi_thread"); + + /* Now lets initialize the fields of spi_master */ + master->bus_num = 0; /* + * This should be the same as passed in + * spi_board_info structure + */ + master->num_chipselect = 4; /* Can be overwritten later during setup */ + master->mode_bits = 0; + master->flags = 0; + master->setup = amd_spi_master_setup; + master->transfer_one_message = amd_spi_master_transfer; + /* Register the controller with SPI framework */ + err = spi_register_master(master); + if (err) { + dev_err(dev, "error registering SPI controller\n"); + goto err_iounmap; + } + pci_set_drvdata(pdev, amd_spi); + + return 0; + +err_iounmap: + iounmap(amd_spi->io_remap_addr); +err_free_master: + spi_master_put(master); + + return 0; +} + +static void amd_spi_pci_remove(struct pci_dev *pdev) +{ + struct amd_spi *amd_spi = pci_get_drvdata(pdev); + + kthread_stop(amd_spi->kthread_spi); + iounmap(amd_spi->io_remap_addr); + spi_unregister_master(amd_spi->master); + spi_master_put(amd_spi->master); + pci_set_drvdata(pdev, NULL); +} + +static struct pci_driver amd_spi_pci_driver = { + .name = "amd_spi", + .id_table = amd_spi_pci_device_id, + .probe = amd_spi_pci_probe, + .remove = amd_spi_pci_remove, +}; + +static int __init amd_spi_init(void) +{ + int ret; + + pr_info("AMD SPI Driver v%s\n", SPI_VERSION); + + ret = pci_register_driver(&amd_spi_pci_driver); + if (ret) + return ret; + + return 0; +} +module_init(amd_spi_init); + +static void __exit amd_spi_exit(void) +{ + pci_unregister_driver(&amd_spi_pci_driver); +} +module_exit(amd_spi_exit); + +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_AUTHOR("Arindam Nath <arindam.nath@amd.com>"); +MODULE_AUTHOR("Sanjay Mehta <sanju.mehta@amd.com>"); +MODULE_DESCRIPTION("AMD SPI Master Controller Driver"); diff --git a/meta-r1000/recipes-kernel/amd-spi/files/spi_amd.h b/meta-r1000/recipes-kernel/amd-spi/files/spi_amd.h new file mode 100644 index 00000000..ec58b9a8 --- /dev/null +++ b/meta-r1000/recipes-kernel/amd-spi/files/spi_amd.h @@ -0,0 +1,28 @@ +#ifndef SPI_AMD_H +#define SPI_AMD_H + +#define DRIVER_NAME "spi_amd" +#define SPI_VERSION "1.0" + +#define AMD_SPI_CTRL0_REG 0x00 + #define AMD_SPI_EXEC_CMD (0x1 << 16) + #define AMD_SPI_OPCODE_MASK 0xFF + #define AMD_SPI_FIFO_CLEAR (0x1 << 20) + #define AMD_SPI_BUSY (0x1 << 31) +#define AMD_SPI_ALT_CS_REG 0x1D + #define AMD_SPI_ALT_CS_MASK 0x3 +#define AMD_SPI_FIFO_BASE 0x80 +#define AMD_SPI_TX_COUNT_REG 0x48 +#define AMD_SPI_RX_COUNT_REG 0x4B +#define AMD_SPI_STATUS_REG 0x4C + +#define AMD_PCI_LPC_SPI_BASE_ADDR_REG 0xA0 +#define AMD_SPI_BASE_ADDR_MASK ~0x3F +#define AMD_SPI_MEM_SIZE 200 + +#define PCI_DEVICE_ID_AMD_LPC_BRIDGE 0x790E + +#define TRANSMIT 1 +#define RECEIVE 2 + +#endif /* SPI_AMD_H */ diff --git a/meta-r1000/recipes-kernel/amd-spi/files/spirom.c b/meta-r1000/recipes-kernel/amd-spi/files/spirom.c new file mode 100644 index 00000000..cb5970ba --- /dev/null +++ b/meta-r1000/recipes-kernel/amd-spi/files/spirom.c @@ -0,0 +1,519 @@ +/***************************************************************************** +* +* spirom.c - SPI ROM client driver +* +* Copyright (c) 2014, Advanced Micro Devices, Inc. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +* +***************************************************************************/ +#include <linux/init.h> +#include <linux/module.h> +#include <linux/ioctl.h> +#include <linux/fs.h> +#include <linux/device.h> +#include <linux/err.h> +#include <linux/list.h> +#include <linux/errno.h> +#include <linux/mutex.h> +#include <linux/slab.h> +#include <linux/spi/spi.h> +#include <linux/pci.h> +#include <linux/delay.h> + +#include <linux/uaccess.h> + +#include "spirom.h" + +#define SPIROM_VERSION "0.2" + +/* + * SPI has a character major number assigned. We allocate minor numbers + * dynamically using a bitmask. You must use hotplug tools, such as udev + * (or mdev with busybox) to create and destroy the /dev/spiromB.C device + * nodes, since there is no fixed association of minor numbers with any + * particular SPI bus or device. + */ +#define SPIROM_MAJOR 153 /* assigned */ +#define N_SPI_MINORS 32 /* ... up to 256 */ + +#define SPI_BUS 0 +#define SPI_BUS_CS1 0 + +static unsigned long minors[N_SPI_MINORS / BITS_PER_LONG]; + + +struct spirom_data { + dev_t devt; + spinlock_t spi_lock; + struct spi_device *spi; + struct list_head device_entry; + struct completion done; + + struct mutex buf_lock; + unsigned users; +}; + +static LIST_HEAD(device_list); +static DEFINE_MUTEX(device_list_lock); + +/*-------------------------------------------------------------------------*/ + +/* + * We can't use the standard synchronous wrappers for file I/O; we + * need to protect against async removal of the underlying spi_device. + */ +static void spirom_complete(void *arg) +{ + complete(arg); +} + +static ssize_t +spirom_sync(struct spirom_data *spirom, struct spi_message *message) +{ + int status; + + message->complete = spirom_complete; + message->context = &spirom->done; + + spin_lock_irq(&spirom->spi_lock); + if (spirom->spi == NULL) + status = -ESHUTDOWN; + else + status = spi_async(spirom->spi, message); + spin_unlock_irq(&spirom->spi_lock); + + if (status == 0) { + /* + * There might be cases where the controller driver has been + * unloaded in the middle of a transaction. So we might end up + * in a situation where we will be waiting for an event which + * will never happen. So we provide a timeout of 1 second for + * situations like this. + */ + wait_for_completion_timeout(&spirom->done, HZ); + status = message->status; + if (status == 0) + status = message->actual_length; + } + return status; +} + +static int spirom_message(struct spirom_data *spirom, + struct spi_ioc_transfer *u_trans, unsigned long arg) +{ + struct spi_message msg; + struct spi_transfer *transfer; + u8 *buffer; + int status = u_trans->len; + + buffer = u_trans->buf; + spi_message_init(&msg); + + /* The very first spi_transfer will contain the command only */ + transfer = kzalloc(sizeof(struct spi_transfer), GFP_KERNEL); + if (!transfer) + return -ENOMEM; + + transfer->tx_buf = buffer; + transfer->len = 1; + buffer += transfer->len; + spi_message_add_tail(transfer, &msg); + + /* + * If the command expects an address as its argument, we populate + * it in the very next spi_transfer. + */ + if (u_trans->addr_present) { + transfer = kzalloc(sizeof(struct spi_transfer), GFP_KERNEL); + if (!transfer) + return -ENOMEM; + + transfer->tx_buf = buffer; + transfer->len = 3; // 3-byte address + buffer += transfer->len; + spi_message_add_tail(transfer, &msg); + } + + /* + * Next is data, which can have a maximum of 64-bytes, the size limited + * by the number of bytes that can stored in the controller FIFO. + */ + if (u_trans->len) { + transfer = kzalloc(sizeof(struct spi_transfer), GFP_KERNEL); + if (!transfer) + return -ENOMEM; + + if (u_trans->direction == TRANSMIT) + transfer->tx_buf = buffer; + else if (u_trans->direction == RECEIVE) + transfer->rx_buf = buffer; + + transfer->len = u_trans->len; + /* No need to increment buffer pointer */ + spi_message_add_tail(transfer, &msg); + } + + status = spirom_sync(spirom, &msg); + + if (u_trans->direction == RECEIVE) { + /* + * The received data should have been populated in + * u_trans->buf, so we just need to copy it into the + * user-space buffer. + */ + buffer = u_trans->buf; + if (u_trans->addr_present) { + buffer += 4; // 1-byte command and 3-byte address + if(__copy_to_user((u8 __user *) + (((struct spi_ioc_transfer *)arg)->buf) + 4, + buffer, u_trans->len)) { + status = -EFAULT; + } + } else { + buffer += 1; // 1-byte command only + if(__copy_to_user((u8 __user *) + (((struct spi_ioc_transfer *)arg)->buf) + 1, + buffer, u_trans->len)) { + status = -EFAULT; + } + } + } + + /* Done with everything, free the memory taken by spi_transfer */ + while (msg.transfers.next != &msg.transfers) { + transfer = list_entry(msg.transfers.next, struct spi_transfer, + transfer_list); + msg.transfers.next = transfer->transfer_list.next; + transfer->transfer_list.next->prev = &msg.transfers; + kfree(transfer); + } + + return status; +} + +static long +spirom_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) +{ + int err = 0; + int retval = 0; + struct spirom_data *spirom; + struct spi_device *spi; + u32 tmp; + struct spi_ioc_transfer *ioc; + + /* Check type and command number */ + if (_IOC_TYPE(cmd) != SPI_IOC_MAGIC) + return -ENOTTY; + + /* Check access direction once here; don't repeat below. + * IOC_DIR is from the user perspective, while access_ok is + * from the kernel perspective; so they look reversed. + */ + if (_IOC_DIR(cmd) & _IOC_READ) + err = !access_ok(VERIFY_WRITE, + (void __user *)arg, _IOC_SIZE(cmd)); + if (err == 0 && _IOC_DIR(cmd) & _IOC_WRITE) + err = !access_ok(VERIFY_READ, + (void __user *)arg, _IOC_SIZE(cmd)); + if (err) + return -EFAULT; + + /* guard against device removal before, or while, + * we issue this ioctl. + */ + spirom = filp->private_data; + spin_lock_irq(&spirom->spi_lock); + spi = spi_dev_get(spirom->spi); + spin_unlock_irq(&spirom->spi_lock); + + if (spi == NULL) + return -ESHUTDOWN; + + /* use the buffer lock here for triple duty: + * - prevent I/O (from us) so calling spi_setup() is safe; + * - prevent concurrent SPI_IOC_WR_* from morphing + * data fields while SPI_IOC_RD_* reads them; + * - SPI_IOC_MESSAGE needs the buffer locked "normally". + */ + mutex_lock(&spirom->buf_lock); + + /* segmented and/or full-duplex I/O request */ + if (_IOC_NR(cmd) != _IOC_NR(SPI_IOC_MESSAGE(0)) || + _IOC_DIR(cmd) !=_IOC_WRITE) { + retval = -ENOTTY; + goto out; + } + + tmp = sizeof(struct spi_ioc_transfer); + + /* copy into scratch area */ + ioc = kzalloc(tmp, GFP_KERNEL); + if (!ioc) { + retval = -ENOMEM; + goto out; + } + if (__copy_from_user(ioc, (struct spi_ioc_transfer __user *)arg, + tmp)) { + kfree(ioc); + retval = -EFAULT; + goto out; + } + + /* translate to spi_message, execute */ + retval = spirom_message(spirom, ioc, arg); + kfree(ioc); + +out: + mutex_unlock(&spirom->buf_lock); + spi_dev_put(spi); + return retval; +} + +static int spirom_open(struct inode *inode, struct file *filp) +{ + struct spirom_data *spirom; + int status = -ENXIO; + + mutex_lock(&device_list_lock); + + list_for_each_entry(spirom, &device_list, device_entry) { + if (spirom->devt == inode->i_rdev) { + status = 0; + break; + } + } + if (status == 0) { + if (status == 0) { + spirom->users++; + filp->private_data = spirom; + nonseekable_open(inode, filp); + } + } else + pr_debug("spirom: nothing for minor %d\n", iminor(inode)); + + mutex_unlock(&device_list_lock); + return status; +} + +static int spirom_release(struct inode *inode, struct file *filp) +{ + struct spirom_data *spirom; + int status = 0; + + mutex_lock(&device_list_lock); + spirom = filp->private_data; + filp->private_data = NULL; + + /* last close? */ + spirom->users--; + if (!spirom->users) { + int dofree; + + /* ... after we unbound from the underlying device? */ + spin_lock_irq(&spirom->spi_lock); + dofree = (spirom->spi == NULL); + spin_unlock_irq(&spirom->spi_lock); + + if (dofree) + kfree(spirom); + } + mutex_unlock(&device_list_lock); + + return status; +} + +static const struct file_operations spirom_fops = { + .owner = THIS_MODULE, + .unlocked_ioctl = spirom_ioctl, + .open = spirom_open, + .release = spirom_release, +}; + +static int __init add_spi_device_to_bus(void) +{ + struct spi_master *spi_master; + struct spi_device *spi_device; + struct spi_board_info spi_info; + + spi_master = spi_busnum_to_master(SPI_BUS); + if (!spi_master) { + printk(KERN_ALERT "Please make sure to \'modprobe " + "spi_amd\' driver first\n"); + return -1; + } + memset(&spi_info, 0, sizeof(struct spi_board_info)); + + strlcpy(spi_info.modalias, "spirom", SPI_NAME_SIZE); + spi_info.bus_num = SPI_BUS; //Bus number of SPI master + spi_info.chip_select = SPI_BUS_CS1; //CS on which SPI device is connected + + spi_device = spi_new_device(spi_master, &spi_info); + if (!spi_device) + return -ENODEV; + + return 0; +} + +/*-------------------------------------------------------------------------*/ + +/* The main reason to have this class is to make mdev/udev create the + * /dev/spiromB.C character device nodes exposing our userspace API. + * It also simplifies memory management. + */ + +static struct class *spirom_class; + +/*-------------------------------------------------------------------------*/ + +static int spirom_probe(struct spi_device *spi) +{ + struct spirom_data *spirom; + int status; + unsigned long minor; + + /* Allocate driver data */ + spirom = kzalloc(sizeof(*spirom), GFP_KERNEL); + if (!spirom) + return -ENOMEM; + + /* Initialize the driver data */ + spirom->spi = spi; + spin_lock_init(&spirom->spi_lock); + mutex_init(&spirom->buf_lock); + + INIT_LIST_HEAD(&spirom->device_entry); + init_completion(&spirom->done); + + /* If we can allocate a minor number, hook up this device. + * Reusing minors is fine so long as udev or mdev is working. + */ + mutex_lock(&device_list_lock); + minor = find_first_zero_bit(minors, N_SPI_MINORS); + if (minor < N_SPI_MINORS) { + struct device *dev; + + spirom->devt = MKDEV(SPIROM_MAJOR, minor); + dev = device_create(spirom_class, &spi->dev, spirom->devt, + spirom, "spirom%d.%d", + spi->master->bus_num, spi->chip_select); + status = IS_ERR(dev) ? PTR_ERR(dev) : 0; + } else { + dev_dbg(&spi->dev, "no minor number available!\n"); + status = -ENODEV; + } + if (status == 0) { + set_bit(minor, minors); + list_add(&spirom->device_entry, &device_list); + } + mutex_unlock(&device_list_lock); + + if (status == 0) + spi_set_drvdata(spi, spirom); + else + kfree(spirom); + + return status; +} + +static int spirom_remove(struct spi_device *spi) +{ + struct spirom_data *spirom = spi_get_drvdata(spi); + + /* make sure ops on existing fds can abort cleanly */ + spin_lock_irq(&spirom->spi_lock); + spirom->spi = NULL; + spi_set_drvdata(spi, NULL); + spin_unlock_irq(&spirom->spi_lock); + + /* prevent new opens */ + mutex_lock(&device_list_lock); + list_del(&spirom->device_entry); + clear_bit(MINOR(spirom->devt), minors); + device_destroy(spirom_class, spirom->devt); + if (spirom->users == 0) + kfree(spirom); + mutex_unlock(&device_list_lock); + + return 0; +} + +static struct spi_driver spirom_spi = { + .driver = { + .name = "spirom", + .owner = THIS_MODULE, + }, + .probe = spirom_probe, + .remove = spirom_remove, + + /* NOTE: suspend/resume methods are not necessary here. + * We don't do anything except pass the requests to/from + * the underlying controller. The refrigerator handles + * most issues; the controller driver handles the rest. + */ +}; + +/*-------------------------------------------------------------------------*/ + +static int __init spirom_init(void) +{ + int status; + + pr_info("AMD SPIROM Driver v%s\n", SPIROM_VERSION); + + /* Claim our 256 reserved device numbers. Then register a class + * that will key udev/mdev to add/remove /dev nodes. Last, register + * the driver which manages those device numbers. + */ + BUILD_BUG_ON(N_SPI_MINORS > 256); + status = register_chrdev(SPIROM_MAJOR, "spi", &spirom_fops); + if (status < 0) + return status; + + spirom_class = class_create(THIS_MODULE, "spirom"); + if (IS_ERR(spirom_class)) { + unregister_chrdev(SPIROM_MAJOR, spirom_spi.driver.name); + return PTR_ERR(spirom_class); + } + + status = spi_register_driver(&spirom_spi); + if (status < 0) { + class_destroy(spirom_class); + unregister_chrdev(SPIROM_MAJOR, spirom_spi.driver.name); + } + + status = add_spi_device_to_bus(); + if (status < 0) { + spi_unregister_driver(&spirom_spi); + class_destroy(spirom_class); + unregister_chrdev(SPIROM_MAJOR, spirom_spi.driver.name); + } + + return status; +} +module_init(spirom_init); + +static void __exit spirom_exit(void) +{ + spi_unregister_driver(&spirom_spi); + class_destroy(spirom_class); + unregister_chrdev(SPIROM_MAJOR, spirom_spi.driver.name); +} +module_exit(spirom_exit); + +MODULE_AUTHOR("Arindam Nath <arindam.nath@amd.com>"); +MODULE_DESCRIPTION("User mode SPI ROM interface"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("spi:spirom"); diff --git a/meta-r1000/recipes-kernel/amd-spi/files/spirom.h b/meta-r1000/recipes-kernel/amd-spi/files/spirom.h new file mode 100644 index 00000000..941b357a --- /dev/null +++ b/meta-r1000/recipes-kernel/amd-spi/files/spirom.h @@ -0,0 +1,53 @@ +#ifndef SPIROM_H +#define SPIROM_H + +#include <linux/types.h> + +/*---------------------------------------------------------------------------*/ + +/* IOCTL commands */ + +#define SPI_IOC_MAGIC 'k' + +#define TRANSMIT 1 +#define RECEIVE 2 + +/* + * struct spi_ioc_transfer - interface structure between application and ioctl + * + * @buf: Buffer to hold 1-byte command, 3-bytes address, and 64-byte data for + * transmit or receive. The internal FIFO of our controller can hold a + * maximum of 70 bytes, including the address. But here we assume the + * maximum data excluding address to be 64-bytes long. + * + * @direction: Direction of data transfer, either TRANSMIT or RECEIVE. + * + * @len: Length of data excluding command and address. + * + * @addr_present: Flag to indicate whether 'buf' above contains an address. + */ +struct spi_ioc_transfer { + __u8 buf[64 + 1 + 3]; + __u8 direction; + __u8 len; + __u8 addr_present; +}; + +/* not all platforms use <asm-generic/ioctl.h> or _IOC_TYPECHECK() ... */ +#define SPI_MSGSIZE(N) \ + ((((N)*(sizeof (struct spi_ioc_transfer))) < (1 << _IOC_SIZEBITS)) \ + ? ((N)*(sizeof (struct spi_ioc_transfer))) : 0) +#define SPI_IOC_MESSAGE(N) _IOW(SPI_IOC_MAGIC, 0, char[SPI_MSGSIZE(N)]) + +/* SPI ROM command codes */ +#define ROM_WREN 0x06 +#define ROM_WRDI 0x04 +#define ROM_RDSR 0x05 +#define ROM_RDID 0x9F +#define ROM_CHIP_ERASE 0x60 +#define ROM_SECTOR_ERASE 0x20 +#define ROM_BLOCK_ERASE 0xD8 +#define ROM_READ 0x03 +#define ROM_WRITE 0x02 + +#endif /* SPIROM_H */ diff --git a/meta-r1000/recipes-kernel/amd-wdt/amd-wdt_1.0.bb b/meta-r1000/recipes-kernel/amd-wdt/amd-wdt_1.0.bb new file mode 100644 index 00000000..edaecf5a --- /dev/null +++ b/meta-r1000/recipes-kernel/amd-wdt/amd-wdt_1.0.bb @@ -0,0 +1,14 @@ +DESCRIPTION = "This kernel module provides support for AMD Watchdog driver" +LICENSE = "BSD | GPLv2" +LIC_FILES_CHKSUM = "file://amd_wdt.c;endline=29;md5=8e7a9706367d146e5073510a6e176dc2" + +inherit module + +SRC_URI = "file://Makefile \ + file://amd_wdt.c \ + file://amd_wdt.h \ + " + +S = "${WORKDIR}" + +# The inherit of module.bbclass will take care of the rest diff --git a/meta-r1000/recipes-kernel/amd-wdt/files/Makefile b/meta-r1000/recipes-kernel/amd-wdt/files/Makefile new file mode 100644 index 00000000..36b32f87 --- /dev/null +++ b/meta-r1000/recipes-kernel/amd-wdt/files/Makefile @@ -0,0 +1,14 @@ +obj-m := amd_wdt.o + +SRC := $(shell pwd) + +all: + $(MAKE) -C $(KERNEL_SRC) M=$(SRC) + +modules_install: + $(MAKE) -C $(KERNEL_SRC) M=$(SRC) modules_install + +clean: + rm -f *.o *~ core .depend .*.cmd *.ko *.mod.c + rm -f Module.markers Module.symvers modules.order + rm -rf .tmp_versions Modules.symvers diff --git a/meta-r1000/recipes-kernel/amd-wdt/files/amd_wdt.c b/meta-r1000/recipes-kernel/amd-wdt/files/amd_wdt.c new file mode 100755 index 00000000..94c3f576 --- /dev/null +++ b/meta-r1000/recipes-kernel/amd-wdt/files/amd_wdt.c @@ -0,0 +1,423 @@ +/***************************************************************************** +* +* Copyright (c) 2014, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +***************************************************************************/ +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/types.h> +#include <linux/watchdog.h> +#include <linux/init.h> +#include <linux/pci.h> +#include <linux/ioport.h> +#include <linux/platform_device.h> +#include <linux/io.h> + +#include "amd_wdt.h" + +/* internal variables */ +static u32 wdtbase_phys; +static void __iomem *wdtbase; +static DEFINE_SPINLOCK(wdt_lock); +static struct pci_dev *amd_wdt_pci; + +/* watchdog platform device */ +static struct platform_device *amd_wdt_platform_device; + +/* module parameters */ +static int heartbeat = AMD_WDT_DEFAULT_TIMEOUT; +module_param(heartbeat, int, 0); +MODULE_PARM_DESC(heartbeat, "Watchdog timeout in frequency units. " + "(default=" __MODULE_STRING(WATCHDOG_HEARTBEAT) ")"); + +static char frequency[MAX_LENGTH] = "1s"; +module_param_string(frequency, frequency, MAX_LENGTH, 0); +MODULE_PARM_DESC(frequency, "Watchdog timer frequency units (32us, " + "10ms, 100ms, 1s). (default=1s)"); + +static bool nowayout = WATCHDOG_NOWAYOUT; +module_param(nowayout, bool, 0); +MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started" + " (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); + +static char action[MAX_LENGTH] = "reboot"; +module_param_string(action, action, MAX_LENGTH, 0); +MODULE_PARM_DESC(action, "Watchdog action (reboot/shutdown). (default=reboot) "); + +/* + * Watchdog specific functions + */ +static int amd_wdt_set_timeout(struct watchdog_device *wdt_dev, unsigned int t) +{ + unsigned long flags; + + /* + * In ideal cases the limits will be checked by Watchdog core itself, + * but there might be cases when we call this function directly from + * somewhere else. So check the limits here. + */ + if (t < AMD_WDT_MIN_TIMEOUT) + heartbeat = t = AMD_WDT_MIN_TIMEOUT; + else if (t > AMD_WDT_MAX_TIMEOUT) + heartbeat = t = AMD_WDT_MAX_TIMEOUT; + + /* Write new timeout value to watchdog */ + spin_lock_irqsave(&wdt_lock, flags); + writel(t, AMD_WDT_COUNT(wdtbase)); + spin_unlock_irqrestore(&wdt_lock, flags); + + wdt_dev->timeout = t; + + return 0; +} + +static int amd_wdt_ping(struct watchdog_device *wdt_dev) +{ + u32 val; + unsigned long flags; + + /* Trigger watchdog */ + spin_lock_irqsave(&wdt_lock, flags); + + val = readl(AMD_WDT_CONTROL(wdtbase)); + val |= AMD_WDT_TRIGGER_BIT; + writel(val, AMD_WDT_CONTROL(wdtbase)); + + spin_unlock_irqrestore(&wdt_lock, flags); + + return 0; +} + +static int amd_wdt_start(struct watchdog_device *wdt_dev) +{ + u32 val; + unsigned long flags; + + /* Enable the watchdog timer */ + spin_lock_irqsave(&wdt_lock, flags); + + val = readl(AMD_WDT_CONTROL(wdtbase)); + val |= AMD_WDT_START_STOP_BIT; + writel(val, AMD_WDT_CONTROL(wdtbase)); + + spin_unlock_irqrestore(&wdt_lock, flags); + + /* Trigger the watchdog timer */ + amd_wdt_ping(wdt_dev); + + return 0; +} + +static int amd_wdt_stop(struct watchdog_device *wdt_dev) +{ + u32 val; + unsigned long flags; + + /* Disable the watchdog timer */ + spin_lock_irqsave(&wdt_lock, flags); + + val = readl(AMD_WDT_CONTROL(wdtbase)); + val &= ~AMD_WDT_START_STOP_BIT; + writel(val, AMD_WDT_CONTROL(wdtbase)); + + spin_unlock_irqrestore(&wdt_lock, flags); + + return 0; +} + +static unsigned int amd_wdt_get_timeleft(struct watchdog_device *wdt_dev) +{ + u32 val; + unsigned long flags; + + spin_lock_irqsave(&wdt_lock, flags); + val = readl(AMD_WDT_COUNT(wdtbase)); + spin_unlock_irqrestore(&wdt_lock, flags); + + /* Mask out the upper 16-bits and return */ + return val & AMD_WDT_COUNT_MASK; +} + +static unsigned int amd_wdt_status(struct watchdog_device *wdt_dev) +{ + return wdt_dev->status; +} + +static struct watchdog_ops amd_wdt_ops = { + .owner = THIS_MODULE, + .start = amd_wdt_start, + .stop = amd_wdt_stop, + .ping = amd_wdt_ping, + .status = amd_wdt_status, + .set_timeout = amd_wdt_set_timeout, + .get_timeleft = amd_wdt_get_timeleft, +}; +static struct watchdog_info amd_wdt_info = { + .options = WDIOF_SETTIMEOUT | + WDIOF_MAGICCLOSE | + WDIOF_KEEPALIVEPING, + .firmware_version = 0, + .identity = WDT_MODULE_NAME, +}; + +static struct watchdog_device amd_wdt_dev = { + .info = &amd_wdt_info, + .ops = &amd_wdt_ops, +}; + +/* + * The PCI Device ID table below is used to identify the platform + * the driver is supposed to work for. Since this is a platform + * device, we need a way for us to be able to find the correct + * platform when the driver gets loaded, otherwise we should + * bail out. + */ +static const struct pci_device_id amd_wdt_pci_tbl[] = { + { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CARRIZO_SMBUS, PCI_ANY_ID, + PCI_ANY_ID, }, + { 0, }, +}; +MODULE_DEVICE_TABLE(pci, amd_wdt_pci_tbl); + +static unsigned char amd_wdt_setupdevice(void) +{ + struct pci_dev *dev = NULL; + u32 val; + + /* Match the PCI device */ + for_each_pci_dev(dev) { + if (pci_match_id(amd_wdt_pci_tbl, dev) != NULL) { + amd_wdt_pci = dev; + break; + } + } + + if (!amd_wdt_pci) + return 0; + + /* Watchdog Base Address starts from ACPI MMIO Base Address + 0xB00 */ + wdtbase_phys = AMD_ACPI_MMIO_BASE + AMD_WDT_MEM_MAP_OFFSET; + if (!request_mem_region_exclusive(wdtbase_phys, AMD_WDT_MEM_MAP_SIZE, + "AMD Watchdog")) { + pr_err("mmio address 0x%04x already in use\n", wdtbase_phys); + goto exit; + } + + wdtbase = ioremap(wdtbase_phys, AMD_WDT_MEM_MAP_SIZE); + if (!wdtbase) { + pr_err("failed to get wdtbase address\n"); + goto unreg_mem_region; + } + + /* Enable watchdog timer and decode bit */ + outb(AMD_PM_WATCHDOG_EN_REG, AMD_IO_PM_INDEX_REG); + val = inb(AMD_IO_PM_DATA_REG); + val |= AMD_PM_WATCHDOG_TIMER_EN; + outb(val, AMD_IO_PM_DATA_REG); + + /* Set the watchdog timer resolution */ + outb(AMD_PM_WATCHDOG_CONFIG_REG, AMD_IO_PM_INDEX_REG); + val = inb(AMD_IO_PM_DATA_REG); + /* Clear the previous frequency setting, if any */ + val &= ~AMD_PM_WATCHDOG_CONFIG_MASK; + + /* + * Now set the frequency depending on the module load parameter. + * In case the user passes an invalid argument, we consider the + * frequency to be of 1 second resolution. + */ + if (strncmp(frequency, "32us", 4) == 0) + val |= AMD_PM_WATCHDOG_32USEC_RES; + else if (strncmp(frequency, "10ms", 4) == 0) + val |= AMD_PM_WATCHDOG_10MSEC_RES; + else if (strncmp(frequency, "100ms", 5) == 0) + val |= AMD_PM_WATCHDOG_100MSEC_RES; + else { + val |= AMD_PM_WATCHDOG_1SEC_RES; + if (strncmp(frequency, "1s", 2) != 0) + strncpy(frequency, "1s", 2); + } + + outb(val, AMD_IO_PM_DATA_REG); + + /* Check to see if last reboot was due to watchdog timeout */ + val = readl(AMD_WDT_CONTROL(wdtbase)); + + + /* Clear out the old status */ + + /* + * Set the watchdog action depending on module load parameter. + * + * If action is specified anything other than reboot or shutdown, + * we default it to reboot. + */ + if (strncmp(action, "shutdown", 8) == 0) + val |= AMD_WDT_ACTION_RESET_BIT; + else { + val &= ~AMD_WDT_ACTION_RESET_BIT; + /* The statement below is required for when the action + * is set anything other than reboot. + */ + if (strncmp(action, "reboot", 6) != 0) + strncpy(action, "reboot", 6); + } + + writel(val, AMD_WDT_CONTROL(wdtbase)); + + return 1; + +unreg_mem_region: + release_mem_region(wdtbase_phys, AMD_WDT_MEM_MAP_SIZE); +exit: + return 0; +} + +static int amd_wdt_init(struct platform_device *dev) +{ + int ret; + u32 val; + + /* Identify our device and initialize watchdog hardware */ + if (!amd_wdt_setupdevice()) + return -ENODEV; + val = readl(AMD_WDT_CONTROL(wdtbase)); + if (val & AMD_WDT_FIRED_BIT) + amd_wdt_dev.bootstatus |= WDIOF_CARDRESET; + else + amd_wdt_dev.bootstatus &= ~WDIOF_CARDRESET; + + pr_info("Watchdog reboot %sdetected\n", + (val & AMD_WDT_FIRED_BIT) ? "" : "not "); + + /* Clear out the old status */ + val |= AMD_WDT_FIRED_BIT; + writel(val, AMD_WDT_CONTROL(wdtbase)); + + amd_wdt_dev.timeout = heartbeat; + amd_wdt_dev.min_timeout = AMD_WDT_MIN_TIMEOUT; + amd_wdt_dev.max_timeout = AMD_WDT_MAX_TIMEOUT; + watchdog_set_nowayout(&amd_wdt_dev, nowayout); + + /* Make sure watchdog is not running */ + amd_wdt_stop(&amd_wdt_dev); + + /* Set Watchdog timeout */ + amd_wdt_set_timeout(&amd_wdt_dev, heartbeat); + + ret = watchdog_register_device(&amd_wdt_dev); + if (ret != 0) { + pr_err("Watchdog timer: cannot register watchdog device" + " (err=%d)\n", ret); + goto exit; + } + + pr_info("initialized (0x%p). (timeout=%d units) (frequency=%s) " + "(nowayout=%d) (action=%s)\n", wdtbase, heartbeat, frequency, + nowayout, action); + + return 0; + +exit: + iounmap(wdtbase); + release_mem_region(wdtbase_phys, AMD_WDT_MEM_MAP_SIZE); + return ret; +} + +static void amd_wdt_cleanup(void) +{ + /* Stop the timer before we leave */ + if (!nowayout) + amd_wdt_stop(NULL); + + watchdog_unregister_device(&amd_wdt_dev); + iounmap(wdtbase); + release_mem_region(wdtbase_phys, AMD_WDT_MEM_MAP_SIZE); +} + +static int amd_wdt_remove(struct platform_device *dev) +{ + if (wdtbase) + amd_wdt_cleanup(); + + return 0; +} + +static void amd_wdt_shutdown(struct platform_device *dev) +{ + amd_wdt_stop(NULL); +} + +static struct platform_driver amd_wdt_driver = { + .probe = amd_wdt_init, + .remove = amd_wdt_remove, + .shutdown = amd_wdt_shutdown, + .driver = { + .owner = THIS_MODULE, + .name = WDT_MODULE_NAME, + }, +}; + +static int __init amd_wdt_init_module(void) +{ + int err; + + pr_info("AMD WatchDog Timer Driver v%s\n", WDT_VERSION); + + err = platform_driver_register(&amd_wdt_driver); + if (err) + return err; + + amd_wdt_platform_device = platform_device_register_simple( + WDT_MODULE_NAME, -1, NULL, 0); + if (IS_ERR(amd_wdt_platform_device)) { + err = PTR_ERR(amd_wdt_platform_device); + goto unreg_platform_driver; + } + + return 0; + +unreg_platform_driver: + platform_driver_unregister(&amd_wdt_driver); + return err; +} + +static void __exit amd_wdt_cleanup_module(void) +{ + platform_device_unregister(amd_wdt_platform_device); + platform_driver_unregister(&amd_wdt_driver); + pr_info("AMD Watchdog Module Unloaded\n"); +} + +module_init(amd_wdt_init_module); +module_exit(amd_wdt_cleanup_module); + +MODULE_AUTHOR("Arindam Nath <arindam.nath@amd.com>"); +MODULE_DESCRIPTION("Watchdog timer driver for AMD chipsets"); +MODULE_LICENSE("Dual BSD/GPL"); diff --git a/meta-r1000/recipes-kernel/amd-wdt/files/amd_wdt.h b/meta-r1000/recipes-kernel/amd-wdt/files/amd_wdt.h new file mode 100644 index 00000000..855e6810 --- /dev/null +++ b/meta-r1000/recipes-kernel/amd-wdt/files/amd_wdt.h @@ -0,0 +1,46 @@ +#ifndef _AMD_WDT_H_ +#define _AMD_WDT_H_ + +/* Module and version information */ +#define WDT_VERSION "1.0" +#define WDT_MODULE_NAME "AMD watchdog timer" +#define WDT_DRIVER_NAME WDT_MODULE_NAME ", v" WDT_VERSION + +#define AMD_WDT_DEFAULT_TIMEOUT 60 /* 60 units default heartbeat. */ +#define AMD_WDT_MIN_TIMEOUT 0x0001 /* minimum timeout value */ +#define AMD_WDT_MAX_TIMEOUT 0xFFFF /* maximum timeout value */ +#define MAX_LENGTH (8 + 1) /* shutdown has 8 characters + NULL character */ + +/* Watchdog register definitions */ +#define AMD_ACPI_MMIO_BASE 0xFED80000 +#define AMD_WDT_MEM_MAP_OFFSET 0xB00 +#define AMD_WDT_MEM_MAP_SIZE 0x100 + +#define AMD_WDT_CONTROL(base) ((base) + 0x00) /* Watchdog Control */ + #define AMD_WDT_START_STOP_BIT (1 << 0) + #define AMD_WDT_FIRED_BIT (1 << 1) + #define AMD_WDT_ACTION_RESET_BIT (1 << 2) + #define AMD_WDT_DISABLE_BIT (1 << 3) + /* 6:4 bits Reserved */ + #define AMD_WDT_TRIGGER_BIT (1 << 7) +#define AMD_WDT_COUNT(base) ((base) + 0x04) /* Watchdog Count */ + #define AMD_WDT_COUNT_MASK 0xFFFF + +#define AMD_PM_WATCHDOG_EN_REG 0x00 + #define AMD_PM_WATCHDOG_TIMER_EN (0x01 << 7) + +#define AMD_PM_WATCHDOG_CONFIG_REG 0x03 + #define AMD_PM_WATCHDOG_32USEC_RES 0x0 + #define AMD_PM_WATCHDOG_10MSEC_RES 0x1 + #define AMD_PM_WATCHDOG_100MSEC_RES 0x2 + #define AMD_PM_WATCHDOG_1SEC_RES 0x3 +#define AMD_PM_WATCHDOG_CONFIG_MASK 0x3 + +/* IO port address for indirect access using ACPI PM registers */ +#define AMD_IO_PM_INDEX_REG 0xCD6 +#define AMD_IO_PM_DATA_REG 0xCD7 + +#define AMD_ACPI_MMIO_ADDR_MASK ~0x1FFF +#define PCI_DEVICE_ID_AMD_CARRIZO_SMBUS 0x790B + +#endif /* _AMD_WDT_H_ */ diff --git a/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware.bb b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware.bb new file mode 100644 index 00000000..93fbfc8d --- /dev/null +++ b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware.bb @@ -0,0 +1,35 @@ +DESCRIPTION = "These binaries provide kernel support for newer AMD GPUs" +SECTION = "kernel" +LICENSE = "Firmware-amd" + +SRC_URI = "file://raven2_asd.bin \ + file://raven2_ce.bin \ + file://raven2_gpu_info.bin \ + file://raven2_me.bin \ + file://raven2_mec2.bin \ + file://raven2_mec.bin \ + file://raven2_pfp.bin \ + file://raven2_rlc.bin \ + file://raven2_sdma1.bin \ + file://raven2_sdma.bin \ + file://raven2_vcn.bin \ + file://LICENSE" + +LIC_FILES_CHKSUM = "file://LICENSE;md5=07b0c31777bd686d8e1609c6940b5e74" + +S = "${WORKDIR}" + +# Since, no binaries are generated for a specific target, +# inherit allarch to simply populate prebuilt binaries +inherit allarch + +do_compile() { + : +} + +do_install() { + install -v -m 444 -D ${S}/LICENSE ${D}/lib/firmware/amdgpu/LICENSE + install -v -m 0644 ${S}/*.bin ${D}/lib/firmware/amdgpu +} + +FILES_${PN} = "/lib/firmware/*" diff --git a/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/LICENSE b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/LICENSE new file mode 100644 index 00000000..fe3780b3 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/LICENSE @@ -0,0 +1,51 @@ +Copyright (C) 2009-2014 Advanced Micro Devices, Inc. All rights reserved. + +REDISTRIBUTION: Permission is hereby granted, free of any license fees, +to any person obtaining a copy of this microcode (the "Software"), to +install, reproduce, copy and distribute copies, in binary form only, of +the Software and to permit persons to whom the Software is provided to +do the same, provided that the following conditions are met: + +No reverse engineering, decompilation, or disassembly of this Software +is permitted. + +Redistributions must reproduce the above copyright notice, this +permission notice, and the following disclaimers and notices in the +Software documentation and/or other materials provided with the +Software. + +DISCLAIMER: THE USE OF THE SOFTWARE IS AT YOUR SOLE RISK. THE SOFTWARE +IS PROVIDED "AS IS" AND WITHOUT WARRANTY OF ANY KIND AND COPYRIGHT +HOLDER AND ITS LICENSORS EXPRESSLY DISCLAIM ALL WARRANTIES, EXPRESS AND +IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +COPYRIGHT HOLDER AND ITS LICENSORS DO NOT WARRANT THAT THE SOFTWARE WILL +MEET YOUR REQUIREMENTS, OR THAT THE OPERATION OF THE SOFTWARE WILL BE +UNINTERRUPTED OR ERROR-FREE. THE ENTIRE RISK ASSOCIATED WITH THE USE OF +THE SOFTWARE IS ASSUMED BY YOU. FURTHERMORE, COPYRIGHT HOLDER AND ITS +LICENSORS DO NOT WARRANT OR MAKE ANY REPRESENTATIONS REGARDING THE USE +OR THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, +ACCURACY, RELIABILITY, CURRENTNESS, OR OTHERWISE. + +DISCLAIMER: UNDER NO CIRCUMSTANCES INCLUDING NEGLIGENCE, SHALL COPYRIGHT +HOLDER AND ITS LICENSORS OR ITS DIRECTORS, OFFICERS, EMPLOYEES OR AGENTS +("AUTHORIZED REPRESENTATIVES") BE LIABLE FOR ANY INCIDENTAL, INDIRECT, +SPECIAL OR CONSEQUENTIAL DAMAGES (INCLUDING DAMAGES FOR LOSS OF BUSINESS +PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, AND THE +LIKE) ARISING OUT OF THE USE, MISUSE OR INABILITY TO USE THE SOFTWARE, +BREACH OR DEFAULT, INCLUDING THOSE ARISING FROM INFRINGEMENT OR ALLEGED +INFRINGEMENT OF ANY PATENT, TRADEMARK, COPYRIGHT OR OTHER INTELLECTUAL +PROPERTY RIGHT EVEN IF COPYRIGHT HOLDER AND ITS AUTHORIZED +REPRESENTATIVES HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. IN +NO EVENT SHALL COPYRIGHT HOLDER OR ITS AUTHORIZED REPRESENTATIVES TOTAL +LIABILITY FOR ALL DAMAGES, LOSSES, AND CAUSES OF ACTION (WHETHER IN +CONTRACT, TORT (INCLUDING NEGLIGENCE) OR OTHERWISE) EXCEED THE AMOUNT OF +US$10. + +Notice: The Software is subject to United States export laws and +regulations. You agree to comply with all domestic and international +export laws and regulations that apply to the Software, including but +not limited to the Export Administration Regulations administered by the +U.S. Department of Commerce and International Traffic in Arm Regulations +administered by the U.S. Department of State. These laws include +restrictions on destinations, end users and end use. diff --git a/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_asd.bin b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_asd.bin Binary files differnew file mode 100644 index 00000000..186cb5b4 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_asd.bin diff --git a/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_ce.bin b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_ce.bin Binary files differnew file mode 100644 index 00000000..015bb206 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_ce.bin diff --git a/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_gpu_info.bin b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_gpu_info.bin Binary files differnew file mode 100644 index 00000000..4c361f50 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_gpu_info.bin diff --git a/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_me.bin b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_me.bin Binary files differnew file mode 100644 index 00000000..b2e0ec2d --- /dev/null +++ b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_me.bin diff --git a/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_mec.bin b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_mec.bin Binary files differnew file mode 100644 index 00000000..5b68507f --- /dev/null +++ b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_mec.bin diff --git a/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_mec2.bin b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_mec2.bin Binary files differnew file mode 100644 index 00000000..5b68507f --- /dev/null +++ b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_mec2.bin diff --git a/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_pfp.bin b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_pfp.bin Binary files differnew file mode 100644 index 00000000..17597231 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_pfp.bin diff --git a/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_rlc.bin b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_rlc.bin Binary files differnew file mode 100644 index 00000000..af7d365a --- /dev/null +++ b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_rlc.bin diff --git a/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_sdma.bin b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_sdma.bin Binary files differnew file mode 100644 index 00000000..80e4fb65 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_sdma.bin diff --git a/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_sdma1.bin b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_sdma1.bin Binary files differnew file mode 100644 index 00000000..d86fc166 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_sdma1.bin diff --git a/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_vcn.bin b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_vcn.bin Binary files differnew file mode 100644 index 00000000..f20b5512 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_vcn.bin diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-extra-config.cfg b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-extra-config.cfg new file mode 100644 index 00000000..11400909 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-extra-config.cfg @@ -0,0 +1,416 @@ +CONFIG_PERF_EVENTS_INTEL_UNCORE=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_PGTABLE_LEVELS=4 +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_USELIB=y +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y +CONFIG_SRCU=y +# CONFIG_TASKS_RCU is not set +CONFIG_RCU_KTHREAD_PRIO=0 +# CONFIG_RCU_EXPEDITE_BOOT is not set +CONFIG_BUILD_BIN2C=y +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 +CONFIG_PAGE_COUNTER=y +CONFIG_BPF=y +CONFIG_MULTIUSER=y +CONFIG_SGETMASK_SYSCALL=y +CONFIG_SYSFS_SYSCALL=y +# CONFIG_BPF_SYSCALL is not set +CONFIG_ADVISE_SYSCALLS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_ARCH_HUGE_VMAP=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +# CONFIG_MODULE_COMPRESS is not set +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_ARCH_USE_QUEUE_RWLOCK=y +CONFIG_QUEUE_RWLOCK=y +CONFIG_X86_FEATURE_NAMES=y +# CONFIG_X86_GOLDFISH is not set +CONFIG_IOSF_MBI=m +# CONFIG_IOSF_MBI_DEBUG is not set +CONFIG_X86_VSYSCALL_EMULATION=y +CONFIG_X86_DIRECT_GBPAGES=y +CONFIG_MEMORY_BALLOON=y +# CONFIG_ZSWAP is not set +# CONFIG_ZPOOL is not set +# CONFIG_ZBUD is not set +CONFIG_GENERIC_EARLY_IOREMAP=y +# CONFIG_X86_PMEM_LEGACY is not set +# CONFIG_X86_INTEL_MPX is not set +# CONFIG_EFI_MIXED is not set +CONFIG_HAVE_LIVEPATCH=y +# CONFIG_LIVEPATCH is not set +CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y +CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y +CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y +CONFIG_ACPI_HOTPLUG_IOAPIC=y +# CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set +CONFIG_HAVE_ACPI_APEI=y +CONFIG_HAVE_ACPI_APEI_NMI=y +# CONFIG_PMIC_OPREGION is not set +CONFIG_PCI_BUS_ADDR_T_64BIT=y +CONFIG_PMC_ATOM=y +CONFIG_NET_UDP_TUNNEL=m +# CONFIG_NET_FOU is not set +# CONFIG_NET_FOU_IP_TUNNELS is not set +# CONFIG_GENEVE is not set +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_BRIDGE_NETFILTER=m +CONFIG_NF_NAT_REDIRECT=m +# CONFIG_NETFILTER_XT_NAT is not set +# CONFIG_NF_LOG_ARP is not set +# CONFIG_NF_LOG_IPV4 is not set +CONFIG_NF_REJECT_IPV4=m +CONFIG_NF_NAT_IPV4=m +# CONFIG_NF_NAT_MASQUERADE_IPV4 is not set +CONFIG_NF_NAT_PROTO_GRE=m +CONFIG_NF_NAT_PPTP=m +CONFIG_NF_NAT_H323=m +# CONFIG_IP_NF_NAT is not set +# CONFIG_NF_REJECT_IPV6 is not set +# CONFIG_NF_LOG_IPV6 is not set +CONFIG_TIPC_MEDIA_UDP=y +# CONFIG_NET_ACT_VLAN is not set +# CONFIG_NET_ACT_BPF is not set +# CONFIG_NET_ACT_CONNMARK is not set +# CONFIG_MPLS is not set +# CONFIG_NET_SWITCHDEV is not set +# CONFIG_MAC80211_RC_MINSTREL_VHT is not set +CONFIG_UEVENT_HELPER=y +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_ALLOW_DEV_COREDUMP=y +# CONFIG_FENCE_TRACE is not set +# CONFIG_BLK_DEV_PMEM is not set +# CONFIG_INTEL_MEI_TXE is not set +# CONFIG_INTEL_MIC_BUS is not set +# CONFIG_ECHO is not set +# CONFIG_CXL_BASE is not set +# CONFIG_SCSI_MQ_DEFAULT is not set +# CONFIG_SCSI_AM53C974 is not set +# CONFIG_SCSI_WD719X is not set +# CONFIG_DM_MQ_DEFAULT is not set +# CONFIG_DM_ERA is not set +# CONFIG_DM_LOG_WRITES is not set +# CONFIG_IPVLAN is not set +# CONFIG_NET_VENDOR_AGERE is not set +# CONFIG_ET131X is not set +# CONFIG_ALTERA_TSE is not set +# CONFIG_BCMGENET is not set +# CONFIG_CX_ECAT is not set +# CONFIG_FM10K is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_SXGBE_ETH is not set +# CONFIG_TI_CPSW_ALE is not set +# CONFIG_BCM7XXX_PHY is not set +CONFIG_MARVELL_PHY=y +# CONFIG_MDIO_BCM_UNIMAC is not set +CONFIG_USB_NET_DRIVERS=y +# CONFIG_ATH9K_DYNACK is not set +# CONFIG_ATH9K_CHANNEL_CONTEXT is not set +CONFIG_ATH9K_PCOEM=y +CONFIG_BRCMFMAC_PROTO_BCDC=y +# CONFIG_BRCMFMAC_PCIE is not set +# CONFIG_RTL8723BE is not set +# CONFIG_RTL8192EE is not set +# CONFIG_RTL8821AE is not set +# CONFIG_RSI_91X is not set +# CONFIG_MOUSE_PS2_FOCALTECH is not set +# CONFIG_MOUSE_ELAN_I2C is not set +# CONFIG_TABLET_SERIAL_WACOM4 is not set +# CONFIG_TOUCHSCREEN_GOODIX is not set +# CONFIG_TOUCHSCREEN_ELAN is not set +# CONFIG_TOUCHSCREEN_SX8654 is not set +CONFIG_DEVMEM=y +CONFIG_SERIAL_EARLYCON=y +# CONFIG_SERIAL_8250_FINTEK is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_IPMI_SSIF is not set +# CONFIG_TCG_CRB is not set +# CONFIG_TCG_TIS_ST33ZP24 is not set +# CONFIG_XILLYBUS is not set +CONFIG_ACPI_I2C_OPREGION=y +# CONFIG_I2C_SLAVE is not set +# CONFIG_SPI_CADENCE is not set +# CONFIG_SPMI is not set +# CONFIG_PINCTRL_BAYTRAIL is not set +# CONFIG_PINCTRL_CHERRYVIEW is not set +# CONFIG_PINCTRL_SUNRISEPOINT is not set +CONFIG_GPIOLIB_IRQCHIP=y +# CONFIG_GPIO_DWAPB is not set +# CONFIG_GPIO_F7188X is not set +# CONFIG_GPIO_ICH is not set +# CONFIG_GPIO_LYNXPOINT is not set +# CONFIG_GPIO_SCH311X is not set +# CONFIG_GPIO_ADP5588 is not set +# CONFIG_GPIO_BT8XX is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_SENSORS_APPLESMC is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_G762 is not set +# CONFIG_SENSORS_I5500 is not set +# CONFIG_SENSORS_CORETEMP is not set +# CONFIG_SENSORS_POWR1220 is not set +# CONFIG_SENSORS_LTC2945 is not set +# CONFIG_SENSORS_LTC4151 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4222 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LTC4260 is not set +# CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX16065 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX1668 is not set +# CONFIG_SENSORS_MAX197 is not set +# CONFIG_SENSORS_MAX6639 is not set +# CONFIG_SENSORS_MAX6642 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_MAX6697 is not set +# CONFIG_SENSORS_HTU21 is not set +# CONFIG_SENSORS_MCP3021 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_NTC_THERMISTOR is not set +# CONFIG_SENSORS_NCT6683 is not set +# CONFIG_SENSORS_NCT6775 is not set +# CONFIG_SENSORS_NCT7802 is not set +# CONFIG_SENSORS_NCT7904 is not set +# CONFIG_SENSORS_SHTC1 is not set +# CONFIG_SENSORS_SMM665 is not set +# CONFIG_SENSORS_ADC128D818 is not set +# CONFIG_SENSORS_TMP103 is not set +# CONFIG_THERMAL_GOV_BANG_BANG is not set +# CONFIG_INTEL_SOC_DTS_THERMAL is not set +# CONFIG_INT340X_THERMAL is not set +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_CADENCE_WATCHDOG is not set +CONFIG_BCMA_DRIVER_PCI=y +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_AXP20X is not set +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_INTEL_QUARK_I2C_GPIO is not set +# CONFIG_INTEL_SOC_PMIC is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RTSX_USB is not set +# CONFIG_MFD_RN5T618 is not set +# CONFIG_MFD_SKY81452 is not set +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MEDIA_SDR_SUPPORT is not set +# CONFIG_USB_GSPCA_DTCS033 is not set +# CONFIG_USB_GSPCA_TOUPTEK is not set +# CONFIG_DRM_I2C_ADV7511 is not set +# CONFIG_DRM_AMD_POWERPLAY is not set +# CONFIG_DRM_VGEM is not set +CONFIG_FB_CMDLINE=y +CONFIG_HDMI=y +CONFIG_DUMMY_CONSOLE_COLUMNS=80 +CONFIG_DUMMY_CONSOLE_ROWS=25 +CONFIG_SND_DMAENGINE_PCM=m +# CONFIG_SND_SE6X is not set +CONFIG_SND_HDA=y +CONFIG_SND_HDA_PREALLOC_SIZE=64 +# CONFIG_SND_HDA_CODEC_CA0132_DSP is not set +CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0 +CONFIG_SND_HDA_CORE=y +# CONFIG_SND_BCD2000 is not set +# CONFIG_SND_USB_POD is not set +# CONFIG_SND_USB_PODHD is not set +# CONFIG_SND_USB_TONEPORT is not set +# CONFIG_SND_USB_VARIAX is not set +CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +# CONFIG_SND_SOC_FSL_ASRC is not set +# CONFIG_SND_SOC_FSL_SAI is not set +# CONFIG_SND_SOC_FSL_SSI is not set +# CONFIG_SND_SOC_FSL_SPDIF is not set +# CONFIG_SND_SOC_FSL_ESAI is not set +# CONFIG_SND_SOC_IMX_AUDMUX is not set +# CONFIG_SND_SOC_INTEL_BYTCR_RT5640_MACH is not set +# CONFIG_SND_SOC_QCOM is not set +# CONFIG_SND_SOC_XTFPGA_I2S is not set +# CONFIG_SND_SOC_ADAU1701 is not set +# CONFIG_SND_SOC_AK4104 is not set +# CONFIG_SND_SOC_AK4554 is not set +# CONFIG_SND_SOC_AK4642 is not set +# CONFIG_SND_SOC_AK5386 is not set +# CONFIG_SND_SOC_ALC5623 is not set +# CONFIG_SND_SOC_CS35L32 is not set +# CONFIG_SND_SOC_CS42L51_I2C is not set +# CONFIG_SND_SOC_CS42L52 is not set +# CONFIG_SND_SOC_CS42L56 is not set +# CONFIG_SND_SOC_CS42L73 is not set +# CONFIG_SND_SOC_CS4265 is not set +# CONFIG_SND_SOC_CS4270 is not set +# CONFIG_SND_SOC_CS4271_I2C is not set +# CONFIG_SND_SOC_CS4271_SPI is not set +# CONFIG_SND_SOC_CS42XX8_I2C is not set +# CONFIG_SND_SOC_HDMI_CODEC is not set +# CONFIG_SND_SOC_ES8328 is not set +# CONFIG_SND_SOC_PCM1681 is not set +# CONFIG_SND_SOC_PCM1792A is not set +# CONFIG_SND_SOC_PCM512x_I2C is not set +# CONFIG_SND_SOC_PCM512x_SPI is not set +# CONFIG_SND_SOC_RT5631 is not set +# CONFIG_SND_SOC_RT5677_SPI is not set +# CONFIG_SND_SOC_SGTL5000 is not set +# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set +# CONFIG_SND_SOC_SPDIF is not set +# CONFIG_SND_SOC_SSM2602_SPI is not set +# CONFIG_SND_SOC_SSM2602_I2C is not set +# CONFIG_SND_SOC_SSM4567 is not set +# CONFIG_SND_SOC_STA32X is not set +# CONFIG_SND_SOC_STA350 is not set +# CONFIG_SND_SOC_TAS2552 is not set +# CONFIG_SND_SOC_TAS5086 is not set +# CONFIG_SND_SOC_TFA9879 is not set +# CONFIG_SND_SOC_TLV320AIC23_I2C is not set +# CONFIG_SND_SOC_TLV320AIC23_SPI is not set +# CONFIG_SND_SOC_TLV320AIC31XX is not set +# CONFIG_SND_SOC_TLV320AIC3X is not set +# CONFIG_SND_SOC_TS3A227E is not set +# CONFIG_SND_SOC_WM8510 is not set +# CONFIG_SND_SOC_WM8523 is not set +# CONFIG_SND_SOC_WM8580 is not set +# CONFIG_SND_SOC_WM8711 is not set +# CONFIG_SND_SOC_WM8728 is not set +# CONFIG_SND_SOC_WM8731 is not set +# CONFIG_SND_SOC_WM8737 is not set +# CONFIG_SND_SOC_WM8741 is not set +# CONFIG_SND_SOC_WM8750 is not set +# CONFIG_SND_SOC_WM8753 is not set +# CONFIG_SND_SOC_WM8770 is not set +# CONFIG_SND_SOC_WM8776 is not set +# CONFIG_SND_SOC_WM8804_I2C is not set +# CONFIG_SND_SOC_WM8804_SPI is not set +# CONFIG_SND_SOC_WM8903 is not set +# CONFIG_SND_SOC_WM8962 is not set +# CONFIG_SND_SOC_WM8978 is not set +# CONFIG_SND_SOC_TPA6130A2 is not set +# CONFIG_USB_OTG_FSM is not set +CONFIG_USB_XHCI_PCI=y +# CONFIG_USB_MAX3421_HCD is not set +# CONFIG_USB_UAS is not set +# CONFIG_USBIP_CORE is not set +# CONFIG_USB_ISP1760 is not set +# CONFIG_USB_LINK_LAYER_TEST is not set +# CONFIG_USB_CHAOSKEY is not set +# CONFIG_USB_LED_TRIG is not set +# CONFIG_MMC_USDHI6ROL0 is not set +# CONFIG_MMC_TOSHIBA_PCI is not set +# CONFIG_LEDS_CLASS_FLASH is not set +# CONFIG_LEDS_LP8860 is not set +# CONFIG_LEDS_PM8941_WLED is not set +# CONFIG_EDAC_IE31200 is not set +# CONFIG_RTC_DRV_ABB5ZES3 is not set +# CONFIG_RTC_DRV_ABX80X is not set +# CONFIG_RTC_DRV_PCF85063 is not set +# CONFIG_RTC_DRV_DS1343 is not set +# CONFIG_RTC_DRV_DS1347 is not set +# CONFIG_RTC_DRV_MCP795 is not set +# CONFIG_RTC_DRV_DS1685_FAMILY is not set +# CONFIG_RTC_DRV_DS2404 is not set +# CONFIG_RTC_DRV_XGENE is not set +CONFIG_VIRTIO_PCI_LEGACY=y +# CONFIG_VIRTIO_INPUT is not set +# CONFIG_R8723AU is not set +# CONFIG_FB_SM750 is not set +# CONFIG_GS_FPGABOOT is not set +# CONFIG_CRYPTO_SKEIN is not set +# CONFIG_UNISYSSPAR is not set +# CONFIG_FB_TFT is not set +CONFIG_I2O=m +CONFIG_I2O_LCT_NOTIFY_ON_CHANGES=y +CONFIG_I2O_EXT_ADAPTEC=y +CONFIG_I2O_EXT_ADAPTEC_DMA64=y +CONFIG_I2O_CONFIG=m +CONFIG_I2O_CONFIG_OLD_IOCTL=y +# CONFIG_I2O_BUS is not set +CONFIG_I2O_BLOCK=m +CONFIG_I2O_SCSI=m +CONFIG_I2O_PROC=m +# CONFIG_DELL_SMO8800 is not set +# CONFIG_TOSHIBA_HAPS is not set +# CONFIG_COMMON_CLK_PXA is not set +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_ATMEL_PIT is not set +# CONFIG_SH_TIMER_CMT is not set +# CONFIG_SH_TIMER_MTU2 is not set +# CONFIG_SH_TIMER_TMU is not set +# CONFIG_EM_TIMER_STI is not set +# CONFIG_SOC_TI is not set +# CONFIG_PM_DEVFREQ_EVENT is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_MCB is not set +CONFIG_RAS=y +# CONFIG_THUNDERBOLT is not set +# CONFIG_ANDROID is not set +CONFIG_EFI_RUNTIME_WRAPPERS=y +# CONFIG_EXT4_ENCRYPTION is not set +# CONFIG_F2FS_FS is not set +# CONFIG_FS_DAX is not set +# CONFIG_OVERLAY_FS is not set +CONFIG_KERNFS=y +CONFIG_EFIVAR_FS=m +# CONFIG_SQUASHFS_LZ4 is not set +# CONFIG_PSTORE_PMSG is not set +# CONFIG_AUFS_XATTR is not set +# CONFIG_NFSD_PNFS is not set +CONFIG_GRACE_PERIOD=y +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_DEBUG_INFO_SPLIT is not set +# CONFIG_DEBUG_INFO_DWARF4 is not set +# CONFIG_GDB_SCRIPTS is not set +# CONFIG_PAGE_OWNER is not set +# CONFIG_PAGE_EXTENSION is not set +CONFIG_HAVE_ARCH_KASAN=y +# CONFIG_KASAN is not set +CONFIG_KASAN_SHADOW_OFFSET=0xdffffc0000000000 +# CONFIG_SCHED_STACK_END_CHECK is not set +# CONFIG_DEBUG_TIMEKEEPING is not set +# CONFIG_LOCK_TORTURE_TEST is not set +# CONFIG_DEBUG_PI_LIST is not set +# CONFIG_PROVE_RCU is not set +# CONFIG_TORTURE_TEST is not set +# CONFIG_TRACEPOINT_BENCHMARK is not set +# CONFIG_TRACE_ENUM_MAP_FILE is not set +# CONFIG_TEST_HEXDUMP is not set +# CONFIG_TEST_RHASHTABLE is not set +# CONFIG_TEST_LKM is not set +# CONFIG_TEST_BPF is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_MEMTEST is not set +CONFIG_INTEGRITY=y +# CONFIG_INTEGRITY_SIGNATURE is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_MCRYPTD is not set +CONFIG_CRYPTO_GCM=m +CONFIG_CRYPTO_GHASH=m +# CONFIG_CRYPTO_SHA1_MB is not set +# CONFIG_CRYPTO_DES3_EDE_X86_64 is not set +# CONFIG_CRYPTO_DRBG_MENU is not set +# CONFIG_CRYPTO_USER_API_RNG is not set +# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set +CONFIG_KVM_COMPAT=y +# CONFIG_HAVE_ARCH_BITREVERSE is not set +CONFIG_RATIONAL=y +CONFIG_ARCH_HAS_FAST_MULTIPLIER=y +# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set +CONFIG_HAS_IOPORT_MAP=y +CONFIG_GLOB=y +# CONFIG_GLOB_SELFTEST is not set +CONFIG_ARCH_HAS_SG_CHAIN=y +CONFIG_MICROCODE_EARLY=y +# CONFIG_MICROCODE_INTEL_EARLY is not set +# CONFIG_PINMUX is not set +# CONFIG_PAGE_TABLE_ISOLATION is not set diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-gpu-config.cfg b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-gpu-config.cfg new file mode 100644 index 00000000..6cdacf5d --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-gpu-config.cfg @@ -0,0 +1,8 @@ +CONFIG_DRM_AMDGPU=m +CONFIG_DRM_AMDGPU_CIK=y +CONFIG_DRM_AMDGPU_USERPTR=y +CONFIG_HSA_AMD=y +CONFIG_DRM_AMD_DC=y +CONFIG_DRM_AMD_DC_DCN1_0=y +CONFIG_SND_SOC_AMD_ACP=m +CONFIG_SND_SOC_AMD_CZ_RT286_MACH=m diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-standard-only.cfg b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-standard-only.cfg new file mode 100644 index 00000000..bfc1701d --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-standard-only.cfg @@ -0,0 +1,3 @@ +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y +CONFIG_X86_POWERNOW_K8=y diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-user-config.cfg b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-user-config.cfg new file mode 100644 index 00000000..63234d47 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-user-config.cfg @@ -0,0 +1,204 @@ +CONFIG_GPIO_DEVRES=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_ACPI=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_GENERIC=m +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_SPIDEV=m +CONFIG_I2C_CHARDEV=m +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_PIIX4=m +CONFIG_IGB=m +CONFIG_SENSORS_K10TEMP=m +CONFIG_X86_MCE=y +CONFIG_X86_MCE_AMD=y +CONFIG_SND_USB=y +CONFIG_SND_HWDEP=y +CONFIG_SND_JACK=y +CONFIG_SND_SEQ_HRTIMER_DEFAULT=y +CONFIG_SND_HDA_RECONFIG=y +CONFIG_SND_HDA_INPUT_BEEP_MODE=1 +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SERIAL_NONSTANDARD=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_8250_NR_UARTS=16 +CONFIG_SERIAL_8250_RUNTIME_UARTS=8 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_RSA=y +CONFIG_X86_AMD_PLATFORM_DEVICE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_RCU_FAST_NO_HZ=y +CONFIG_CGROUP_PERF=y +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BLK_DEV_THROTTLING=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_CFQ_GROUP_IOSCHED=y +CONFIG_DEFAULT_DEADLINE=y +CONFIG_DEFAULT_IOSCHED="deadline" +CONFIG_PROCESSOR_SELECT=y +CONFIG_GART_IOMMU=y +CONFIG_CALGARY_IOMMU=y +CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT=y +CONFIG_NR_CPUS=24 +CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y +CONFIG_X86_MCE_INJECT=m +CONFIG_MICROCODE=y +CONFIG_X86_MSR=m +CONFIG_X86_CPUID=m +CONFIG_NUMA=y +CONFIG_AMD_NUMA=y +CONFIG_X86_64_ACPI_NUMA=y +CONFIG_NODES_SPAN_OTHER_NODES=y +CONFIG_NODES_SHIFT=6 +CONFIG_ARCH_MEMORY_PROBE=y +CONFIG_NEED_MULTIPLE_NODES=y +CONFIG_MEMORY_ISOLATION=y +CONFIG_HAVE_BOOTMEM_INFO_NODE=y +CONFIG_MEMORY_HOTPLUG=y +CONFIG_MEMORY_HOTPLUG_SPARSE=y +CONFIG_MEMORY_HOTREMOVE=y +CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y +CONFIG_NEED_BOUNCE_POOL=y +CONFIG_MMU_NOTIFIER=y +CONFIG_KSM=y +CONFIG_MEMORY_FAILURE=y +CONFIG_CLEANCACHE=y +CONFIG_FRONTSWAP=y +CONFIG_KEXEC=y +CONFIG_CRASH_DUMP=y +CONFIG_PHYSICAL_ALIGN=0x1000000 +CONFIG_COMPAT_VDSO=y +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +CONFIG_USE_PERCPU_NUMA_NODE_ID=y +CONFIG_ARCH_HIBERNATION_HEADER=y +CONFIG_HIBERNATE_CALLBACKS=y +CONFIG_HIBERNATION=y +CONFIG_PM_STD_PARTITION="" +CONFIG_PM_TRACE=y +CONFIG_PM_TRACE_RTC=y +CONFIG_ACPI_VIDEO=m +CONFIG_ACPI_NUMA=y +CONFIG_ACPI_SBS=m +CONFIG_ACPI_HED=y +CONFIG_ACPI_BGRT=y +CONFIG_ACPI_APEI=y +CONFIG_ACPI_APEI_GHES=y +CONFIG_ACPI_APEI_PCIEAER=y +CONFIG_ACPI_APEI_MEMORY_FAILURE=y +CONFIG_ACPI_APEI_EINJ=m +CONFIG_ACPI_APEI_ERST_DEBUG=m +CONFIG_SFI=y +CONFIG_CPU_FREQ_STAT_DETAILS=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_X86_PCC_CPUFREQ=m +CONFIG_X86_SPEEDSTEP_CENTRINO=y +CONFIG_X86_P4_CLOCKMOD=m +CONFIG_X86_SPEEDSTEP_LIB=m +CONFIG_PCI_MMCONFIG=y +CONFIG_PCI_REALLOC_ENABLE_AUTO=y +CONFIG_PCI_STUB=m +CONFIG_PCI_ATS=y +CONFIG_PCI_IOV=y +CONFIG_PCI_PRI=y +CONFIG_PCI_PASID=y +CONFIG_HOTPLUG_PCI_CPCI=y +CONFIG_HOTPLUG_PCI_CPCI_GENERIC=m +CONFIG_HOTPLUG_PCI_SHPC=m +CONFIG_X86_SYSFB=y +CONFIG_NET_SCH_FQ=m +CONFIG_ENCLOSURE_SERVICES=m +CONFIG_EEPROM_LEGACY=m +CONFIG_SATA_AHCI_PLATFORM=m +CONFIG_E1000=m +CONFIG_E1000E=m +CONFIG_SERIAL_8250_DETECT_IRQ=y +CONFIG_IPMI_HANDLER=m +CONFIG_HW_RANDOM_TPM=m +CONFIG_NVRAM=m +CONFIG_HANGCHECK_TIMER=m +CONFIG_TCG_TPM=y +CONFIG_GPIO_GENERIC_PLATFORM=m +CONFIG_SENSORS_K8TEMP=m +CONFIG_SENSORS_FAM15H_POWER=m +CONFIG_SENSORS_ACPI_POWER=m +CONFIG_AGP_AMD64=y +CONFIG_VGA_SWITCHEROO=y +CONFIG_VIDEO_OUTPUT_CONTROL=m +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_OHCI_HCD_PCI=m +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_MMC_SPI=m +CONFIG_EDAC=y +CONFIG_EDAC_LEGACY_SYSFS=y +CONFIG_EDAC_DECODE_MCE=y +CONFIG_EDAC_MCE_INJ=m +CONFIG_EDAC_MM_EDAC=m +CONFIG_EDAC_AMD64=m +CONFIG_SYNC_FILE=y +CONFIG_SW_SYNC=y +CONFIG_AUXDISPLAY=y +CONFIG_IOMMU_API=y +CONFIG_AMD_IOMMU=y +CONFIG_AMD_IOMMU_STATS=y +CONFIG_AMD_IOMMU_V2=m +CONFIG_DMAR_TABLE=y +CONFIG_IRQ_REMAP=y +CONFIG_PM_DEVFREQ=y +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y +CONFIG_DEVFREQ_GOV_PERFORMANCE=y +CONFIG_DEVFREQ_GOV_POWERSAVE=y +CONFIG_DEVFREQ_GOV_USERSPACE=y +CONFIG_MEMORY=y +CONFIG_EDD=y +CONFIG_EDD_OFF=y +CONFIG_DMI_SYSFS=m +CONFIG_EFI_VARS=y +CONFIG_EFI_VARS_PSTORE=y +CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y +CONFIG_EFI_RUNTIME_MAP=y +CONFIG_UEFI_CPER=y +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y +CONFIG_PROC_VMCORE=y +CONFIG_HUGETLBFS=y +CONFIG_HUGETLB_PAGE=y +CONFIG_PSTORE=y +CONFIG_SECURITYFS=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_INTERVAL_TREE=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_BLOCK_BOUNCE=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_PINCTRL_AMD=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_SND_DESIGNWARE_I2S=m +CONFIG_SND_SIMPLE_CARD=m +CONFIG_GPIO_ML_IOH=m +CONFIG_I2C_DESIGNWARE_CORE=y +CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_I2C_DESIGNWARE_PCI=m +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_DEBUG_RODATA is not set +CONFIG_DRM_AMD_ACP=y +CONFIG_SND_SOC=m +CONFIG_SND_SOC_AMD_ACP3x=m +CONFIG_FB_SIMPLE=y +CONFIG_LOGO=y +CONFIG_AMD_XGBE=y +CONFIG_AMD_XGBE_DCB=y +CONFIG_AMD_XGBE_HAVE_ECC=y diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-user-features.scc b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-user-features.scc new file mode 100644 index 00000000..e69de29b --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-user-features.scc diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-user-patches.scc b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-user-patches.scc new file mode 100755 index 00000000..e69de29b --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-user-patches.scc diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000.cfg b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000.cfg new file mode 100644 index 00000000..bd600b86 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000.cfg @@ -0,0 +1,61 @@ +CONFIG_PRINTK=y + +# Basic hardware support for the box - network, USB, PCI, sound +CONFIG_NETDEVICES=y +CONFIG_ATA=y +CONFIG_ATA_GENERIC=y +CONFIG_ATA_SFF=y +CONFIG_PCI=y +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PCI=y +CONFIG_USB_SUPPORT=y +CONFIG_USB=y +CONFIG_R8169=y +CONFIG_R8168=y +CONFIG_PATA_SCH=y +CONFIG_USB_EHCI_HCD=y +CONFIG_PCIEPORTBUS=y +CONFIG_NET=y +CONFIG_USB_UHCI_HCD=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y + +# Make sure these are on, otherwise the bootup won't be fun +CONFIG_EXT3_FS=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_MODULES=y +CONFIG_SHMEM=y +CONFIG_TMPFS=y +CONFIG_PACKET=y + +CONFIG_I2C=y +CONFIG_AGP=y +CONFIG_PM=y +CONFIG_ACPI=y +CONFIG_INPUT=y + +# Needed for booting (and using) USB memory sticks +CONFIG_BLK_DEV_LOOP=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y + +CONFIG_RD_GZIP=y + +# Filesystems +CONFIG_EXT2_FS_SECURITY=y +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +CONFIG_NFSD_V4=y +CONFIG_QFMT_V2 +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +CONFIG_QUOTA_TREE=m +CONFIG_QUOTACTL=y +CONFIG_SQUASHFS=y +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_ZLIB=y +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-r1000_4.14.inc b/meta-r1000/recipes-kernel/linux/linux-yocto-r1000_4.14.inc new file mode 100644 index 00000000..11c54127 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-r1000_4.14.inc @@ -0,0 +1,13 @@ +FILESEXTRAPATHS_prepend := "${THISDIR}/linux-yocto-${LINUX_VERSION}:" + +SRC_URI_append_r1000 += "file://r1000-user-features.scc \ + file://r1000-user-patches.scc \ + file://r1000.cfg \ + file://r1000-user-config.cfg \ + file://r1000-gpu-config.cfg \ + file://r1000-extra-config.cfg \ +" + +KERNEL_FEATURES_append_r1000 = " cfg/sound.scc" + +COMPATIBLE_MACHINE_r1000 = "r1000" diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto_4.14.bbappend b/meta-r1000/recipes-kernel/linux/linux-yocto_4.14.bbappend new file mode 100644 index 00000000..d71129e0 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto_4.14.bbappend @@ -0,0 +1,3 @@ +require linux-yocto-r1000_4.14.inc + +SRC_URI_append_r1000 += "file://r1000-standard-only.cfg" |