diff options
Diffstat (limited to 'meta-r1000')
70 files changed, 5319 insertions, 0 deletions
diff --git a/meta-r1000/COPYING.MIT b/meta-r1000/COPYING.MIT new file mode 100644 index 00000000..89de3547 --- /dev/null +++ b/meta-r1000/COPYING.MIT @@ -0,0 +1,17 @@ +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. diff --git a/meta-r1000/README.md b/meta-r1000/README.md new file mode 100644 index 00000000..1b84a912 --- /dev/null +++ b/meta-r1000/README.md @@ -0,0 +1,16 @@ +# meta-amd/meta-r1000 + +This is the location for AMD R1000 BSP. + +Please see the README file contained in the root meta-amd directory +for general information and usage details. + +## Dependencies + +This layer depends on: + +[bitbake](https://github.com/openembedded/bitbake) layer, +[oe-core](https://github.com/openembedded/openembedded-core) layer, +[meta-oe](https://github.com/openembedded/meta-openembedded) layer, +[meta-python](https://github.com/openembedded/meta-openembedded/meta-python) layer, +meta-amd/common layer diff --git a/meta-r1000/binary/.gitignore b/meta-r1000/binary/.gitignore new file mode 100644 index 00000000..e69de29b --- /dev/null +++ b/meta-r1000/binary/.gitignore diff --git a/meta-r1000/conf/layer.conf b/meta-r1000/conf/layer.conf new file mode 100644 index 00000000..8c1dfe61 --- /dev/null +++ b/meta-r1000/conf/layer.conf @@ -0,0 +1,13 @@ +# We have a conf and classes directory, add to BBPATH +BBPATH .= ":${LAYERDIR}" + +# We have a recipes-* directories, add to BBFILES +BBFILES += "${LAYERDIR}/recipes-*/*/*.bb \ + ${LAYERDIR}/recipes-*/*/*.bbappend" + +BBFILE_COLLECTIONS += "r1000" +BBFILE_PATTERN_r1000 = "^${LAYERDIR}/" +BBFILE_PRIORITY_r1000 = "14" +LAYERSERIES_COMPAT_r1000 = "sumo" + +LAYERDEPENDS_r1000 = "amd openembedded-layer meta-python" diff --git a/meta-r1000/conf/local.conf.append.r1000 b/meta-r1000/conf/local.conf.append.r1000 new file mode 100644 index 00000000..0ce2e809 --- /dev/null +++ b/meta-r1000/conf/local.conf.append.r1000 @@ -0,0 +1,12 @@ +# MEL supports various components that can be enabled by setting the corresponding +# INCLUDE_<component> to "yes". +# Following is a list of <components> that can be enabled if you want them to be +# installed/available on your image. +# Please change the required INCLUDE_<component> to "yes" before building an image, or +# generating an ADE that can be used to develop apps for these components (if applicable): +# +# - OPENCL - The Open Computing Language. +# Framework for writing programs that execute across heterogeneous platforms consisting +# of CPUs, GPUs, DSPs, FPGAs and other processors or hardware accelerators. +# +INCLUDE_OPENCL ??= "no" diff --git a/meta-r1000/conf/machine/include/tune-r1000.inc b/meta-r1000/conf/machine/include/tune-r1000.inc new file mode 100644 index 00000000..1ac8e610 --- /dev/null +++ b/meta-r1000/conf/machine/include/tune-r1000.inc @@ -0,0 +1,15 @@ +DEFAULTTUNE ?= "dbfp5" + +require conf/machine/include/x86/arch-x86.inc +require conf/machine/include/x86-base.inc +# AMD DB-FP5 64bit (r1000) +TUNEVALID[dbfp5] = "Enable AMD DB-FP5 (64 bit) specific processor optimizations" +TUNECONFLICTS[dbfp5] = "m32 mx32" +TUNE_CCARGS .= "${@bb.utils.contains("TUNE_FEATURES", "dbfp5", " -march=znver1", "", d)}" + +# Extra tune selections +AVAILTUNES += "dbfp5" +TUNE_FEATURES_tune-dbfp5 = "m64 dbfp5" +BASE_LIB_tune-dbfp5 = "lib64" +TUNE_PKGARCH_tune-dbfp5 = "dbfp5" +PACKAGE_EXTRA_ARCHS_tune-dbfp5 = "${TUNE_PKGARCH_tune-dbfp5}" diff --git a/meta-r1000/conf/machine/r1000.conf b/meta-r1000/conf/machine/r1000.conf new file mode 100644 index 00000000..70f9c113 --- /dev/null +++ b/meta-r1000/conf/machine/r1000.conf @@ -0,0 +1,51 @@ +#@TYPE: Machine +#@NAME: r1000 + +#@DESCRIPTION: Machine configuration for r1000 systems + +# BSP and PATCH versions for MEL releases +BSP_VERSION = "0" +PATCH_VERSION = "0" + +PREFERRED_PROVIDER_virtual/kernel ?= "linux-yocto" +PREFERRED_VERSION_linux-yocto ?= "4.14%" + +require conf/machine/include/tune-r1000.inc + +# Add machine specific AMD features and feature pkgs here +VULKAN_PKGS_r1000 = "amdvlk glslang spirv-tools vulkan-loader-layers rgp" +AMD_PLATFORM_SPECIFIC_PKGS_r1000 += " \ + ${@bb.utils.contains('INCLUDE_OPENCL', 'yes', 'opencl', '', d)} \ + " + +include conf/machine/include/amd-common-configurations.inc +include conf/machine/include/amd-customer-configurations.inc + +# GPU +XSERVER_X86_GPU = "xf86-video-amd \ + ${@bb.utils.contains('DISTRO_FEATURES', 'opengl', 'mesa-driver-radeonsi', '', d)} \ + " + +XSERVER ?= "${XSERVER_X86_BASE} \ + ${XSERVER_X86_EXT} \ + ${XSERVER_X86_FBDEV} \ + ${XSERVER_X86_MODESETTING} \ + ${XSERVER_X86_GPU} \ + " + +KERNEL_MODULE_AUTOLOAD += "snd-soc-acp-pcm snd-soc-acp-rt286-mach amdgpu" +MACHINE_EXTRA_RRECOMMENDS += "amdgpu-firmware grub-efi" +MACHINE_EXTRA_RRECOMMENDS_remove = "rtc-test smbus-test grub" + +# Setup a getty on all serial ports +SERIAL_CONSOLES ?= "115200;ttyS4 115200;ttyS5" + +# Enable the kernel console on ttyS4/USB0 as well +KERNEL_SERIAL_CONSOLE ?= "console=ttyS4,115200n8" + +TOOLCHAIN_HOST_TASK_append_mel = " ${@bb.utils.contains('INCLUDE_VULKAN', 'yes', "nativesdk-glslang", "", d)}" + +MACHINEOVERRIDES =. "amd:amdx86:amdgpu:" + +# Metadata used by CodeBench for the ADE +ADE_CB_CPU = "general.cpu.zen" diff --git a/meta-r1000/recipes-applications/gpio-test/files/gpio-test.c b/meta-r1000/recipes-applications/gpio-test/files/gpio-test.c new file mode 100755 index 00000000..3b05e28b --- /dev/null +++ b/meta-r1000/recipes-applications/gpio-test/files/gpio-test.c @@ -0,0 +1,523 @@ +/***************************************************************************** +* +* Copyright (c) 2017, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +***************************************************************************/ +#include <unistd.h> +#include <stdio.h> +#include <stdlib.h> +#include <fcntl.h> +#include <signal.h> +#include <errno.h> +#include <string.h> + +#include <readline/readline.h> +#include <sys/types.h> +#include <sys/wait.h> +#include <sys/ioctl.h> + +#include "gpio-test.h" + +#define GPIO_APP_VERSION "0.2" +#define AMD_GPIO_NUM_PINS 256 +static int gpio_in_use[AMD_GPIO_NUM_PINS]; + +char *show_prompt(void) +{ + return "$ "; +} + +void sighandler(int sig) +{ + printf("\n%s", show_prompt()); +} + +void show_license(void) +{ + printf("/*****************************************************************************\n" + "*\n" + "* Copyright (c) 2017, Advanced Micro Devices, Inc.\n" + "* All rights reserved.\n" + "*\n" + "* Redistribution and use in source and binary forms, with or without\n" + "* modification, are permitted provided that the following conditions are met:\n" + "* * Redistributions of source code must retain the above copyright\n" + "* notice, this list of conditions and the following disclaimer.\n" + "* * Redistributions in binary form must reproduce the above copyright\n" + "* notice, this list of conditions and the following disclaimer in the\n" + "* documentation and/or other materials provided with the distribution.\n" + "* * Neither the name of Advanced Micro Devices, Inc. nor the names of\n" + "* its contributors may be used to endorse or promote products derived\n" + "* from this software without specific prior written permission.\n" + "*\n" + "* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n" + "* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n" + "* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n" + "* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY\n" + "* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n" + "* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n" + "* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n" + "* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n" + "* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n" + "* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n" + "*\n" + "*\n" + "***************************************************************************/\n"); +} + +void print_usage() +{ + printf("\nCommands Supported ->\n"); + printf(" getgpiomode <gpio> : Gets the mode of GPIO pin\n"); + printf(" setgpiomode <gpio> <in/out/high/low> : Sets the mode of GPIO pin to input or output(high/low)\n"); + printf(" getgpiovalue <gpio> : Gets the value of GPIO pin\n"); + printf(" setgpiovalue <gpio> <high/low> : Sets the value of GPO pin to high or low\n"); + printf(" getnumgpio : Gets the number of GPIO pins supported\n"); + printf(" getgpiobase : Gets the number of first GPIO pin\n"); + printf(" getgpioname : Gets the name of GPIO driver currently in use\n"); + printf(" dmesg : Displays the kernel log messages related to GPIO\n"); + printf(" license : Displays the terms of LICENSE for this application\n"); + printf(" help : Displays help text\n"); + printf(" exit : Exits the application\n\n"); +} + +void parse_cmd(const char *cmdline) +{ + int fd; + + if (strncmp(cmdline, "help", 4) == 0) + print_usage(); + else if (strncmp(cmdline, "getnumgpio", 10) == 0) { + int fd; + char ngpio[3 + 1]; + + memset(ngpio, '\0', (3 + 1)); + fd = open("/sys/class/gpio/gpiochip256/ngpio", O_RDONLY); + if (fd < 0) { + printf("\nPlease make sure AMD GPIO driver is loaded\n"); + exit(EXIT_FAILURE); + } + + /* Value read from the file is ASCII text */ + if(read(fd, ngpio, 3) < 0) + perror("Cannot read number of GPIO pins"); + + printf("\nThe maximum number of GPIO pins supported is %d\n", atoi(ngpio)); + close(fd); + } else if (strncmp(cmdline, "getgpiobase", 11) == 0) { + int fd; + char gpiobase[3 + 1]; + + memset(gpiobase, '\0', (3 + 1)); + fd = open("/sys/class/gpio/gpiochip256/base", O_RDONLY); + if (fd < 0) { + printf("\nPlease make sure AMD GPIO driver is loaded\n"); + exit(EXIT_FAILURE); + } + + if(read(fd, gpiobase, 3) < 0) + perror("Cannot read GPIO base"); + + printf("\nGPIO pin numbering starts from %d\n", atoi(gpiobase)); + close(fd); + } else if (strncmp(cmdline, "getgpioname", 11) == 0) { + int fd; + char gpioname[10 + 1]; /* Max 10 characters + NULL character */ + + /* Zero initialize gpioname array */ + memset(gpioname, '\0', sizeof(gpioname)); + + fd = open("/sys/class/gpio/gpiochip256/label", O_RDONLY); + if (fd < 0) { + printf("\nPlease make sure AMD GPIO driver is loaded\n"); + exit(EXIT_FAILURE); + } + + if(read(fd, gpioname, 10) < 0) + perror("Cannot read GPIO driver name"); + + printf("\nGPIO driver loaded is %s\n", gpioname); + close(fd); + } else if (strncmp(cmdline, "getgpiovalue", 12) == 0) { + int fd; + int gpio_num; + char gpio[3 + 1]; + char pathname[80]; + int ret = 0; + + /* Lets point to the end of first token */ + if (sscanf(cmdline, "getgpiovalue %d", &gpio_num) < 1) { + printf("Invalid inputs, please try again\n\n"); + return; + } + + fd = open("/sys/class/gpio/export", O_WRONLY); + if (fd < 0) { + if (errno == EACCES) + printf("\nYou do not have correct permission, please run as root\n"); + else + perror("Error opening /sys/class/gpio/export"); + + exit(EXIT_FAILURE); + } + + memset(gpio, '\0', (3 + 1)); + if (snprintf(gpio, (3 + 1), "%d", gpio_num) < 1) { + printf("Invalid inputs, please try again\n"); + close(fd); + return; + } + + ret = write(fd, gpio, strlen(gpio)); + /* + * There can be two situations -> + * 1) The GPIO is being exported for the first time. + * 2) The GPIO is being exported again. + * In the first case, the write to file descriptor should + * succeed, and we should still fall into the if clause. + * + * In the second case, write will fail and errno will be + * set to EBUSY, since the GPIO pin is already exported. + * Rest all is error. + */ + if((ret >= 0) || ((ret < 0) && (errno == EBUSY))) { + /* Close the last file descriptor */ + close(fd); + + memset(pathname, '\0', sizeof(pathname)); + sprintf(pathname, "/sys/class/gpio/gpio%d/value", gpio_num); + + fd = open(pathname, O_RDONLY); + if (fd < 0) + perror("GPIO read error"); + else { + char value[1 + 1]; + + memset(value, '\0', 2); + ret = read(fd, value, 1); + if (ret < 0) + perror("Cannot read GPIO pin"); + + printf("\nGPIO pin %d is at \"%s\"\n", gpio_num, + (strncmp(value, "1", 1) == 0) ? "high" : "low"); + + close(fd); + + /* + * Mark the GPIO as already exported, so that we can use + * unexport them during exit. + */ + gpio_in_use[gpio_num] = 1; + } + } else { + if (errno == EINVAL) + printf("\nGPIO number is reserved\n"); + else + perror("Error exporting GPIO number"); + + close(fd); + } + } else if (strncmp(cmdline, "getgpiomode", 11) == 0) { + int fd; + int gpio_num; + char gpio[3 + 1]; + char pathname[80]; + int ret = 0; + + /* Lets point to the end of first token */ + if (sscanf(cmdline, "getgpiomode %d", &gpio_num) < 1) { + printf("Invalid inputs, please try again\n\n"); + return; + } + + fd = open("/sys/class/gpio/export", O_WRONLY); + if (fd < 0) { + if (errno == EACCES) + printf("\nYou do not have correct permission, please run as root\n"); + else + perror("Error opening /sys/class/gpio/export"); + + exit(EXIT_FAILURE); + } + + memset(gpio, '\0', (3 + 1)); + if (snprintf(gpio, (3 + 1), "%d", gpio_num) < 1) { + printf("Invalid inputs, please try again\n"); + close(fd); + return; + } + + ret = write(fd, gpio, strlen(gpio)); + /* + * There can be two situations -> + * 1) The GPIO is being exported for the first time. + * 2) The GPIO is being exported again. + * In the first case, the write to file descriptor should + * succeed, and we should still fall into the if clause. + * + * In the second case, write will fail and errno will be + * set to EBUSY, since the GPIO pin is already exported. + * Rest all is error. + */ + if((ret >= 0) || ((ret < 0) && (errno == EBUSY))) { + /* Close the last file descriptor */ + close(fd); + + memset(pathname, '\0', sizeof(pathname)); + sprintf(pathname, "/sys/class/gpio/gpio%d/direction", gpio_num); + + fd = open(pathname, O_RDONLY); + if (fd < 0) + perror("GPIO read error"); + else { + char mode[3 + 1]; + int c, i = 0; + + memset(mode, '\0', (3 + 1)); + ret = read(fd, mode, 3); + if (ret < 0) + perror("Cannot read GPIO pin"); + + printf("\nGPIO pin %d is in \"%s\" mode\n", gpio_num, + (strncmp(mode, "in", 2) == 0) ? "input" : "output"); + + close(fd); + + /* + * Mark the GPIO as already exported, so that we can use + * unexport them during exit. + */ + gpio_in_use[gpio_num] = 1; + } + } else { + if (errno == EINVAL) + printf("\nGPIO number is reserved \n"); + else + perror("Error exporting GPIO number"); + + close(fd); + } + } else if (strncmp(cmdline, "setgpiomode", 11) == 0) { + int fd; + int gpio_num; + char mode[3 + 1]; + char gpio[3 + 1]; + int ret; + + memset(mode, (3 + 1), 0); + if (sscanf(cmdline, "setgpiomode %d %s", &gpio_num, mode) < 2) { + printf("Invalid inputs, please try again\n\n"); + return; + } + + memset(gpio, '\0', (3 + 1)); + if (snprintf(gpio, (3 + 1), "%d", gpio_num) < 1) { + printf("Invalid inputs, please try again\n"); + return; + } + + fd = open("/sys/class/gpio/export", O_WRONLY); + if (fd < 0) { + if (errno == EACCES) + printf("\nYou do not have correct permission, please run as root\n"); + else + perror("Error opening /sys/class/gpio/export"); + + exit(EXIT_FAILURE); + } + + ret = write(fd, gpio, strlen(gpio)); + if((ret >= 0) || ((ret < 0) && (errno == EBUSY))) { + char pathname[80]; + + /* Close the last file descriptor */ + close(fd); + + memset(pathname, '\0', sizeof(pathname)); + sprintf(pathname, "/sys/class/gpio/gpio%d/direction", gpio_num); + + fd = open(pathname, O_WRONLY); + if (fd < 0) + perror("GPIO read error"); + else { + /* Sanity check */ + if ((strncmp(mode, "in", 2) == 0) || + (strncmp(mode, "out", 3) == 0) || + (strncmp(mode, "high", 4) == 0) || + (strncmp(mode, "low", 3) == 0)) { + /* Write mode into /sys/.../direction file */ + ret = write(fd, mode, strlen(mode)); + if (ret < 0) + perror("Error writing GPIO mode"); + } else + printf("\nInvalid GPIO mode, please try again\n"); + + close(fd); + + /* + * Mark the GPIO as exported, so that we can use + * unexport them during exit. + */ + gpio_in_use[gpio_num] = 1; + } + } else { + if (errno == EINVAL) + printf("\nGPIO number is reserved\n"); + else + perror("Error exporting GPIO number"); + + close(fd); + } + } else if (strncmp(cmdline, "setgpiovalue", 12) == 0) { + int fd; + int gpio_num; + char gpio[3 + 1]; + char value[4 + 1]; + int ret; + + memset(value, (4 + 1), 0); + if (sscanf(cmdline, "setgpiovalue %d %s", &gpio_num, value) < 2) { + printf("Invalid inputs, please try again\n\n"); + return; + } + + memset(gpio, '\0', (3 + 1)); + if (snprintf(gpio, (3 + 1), "%d", gpio_num) < 1) { + printf("Invalid inputs, please try again\n"); + return; + } + + fd = open("/sys/class/gpio/export", O_WRONLY); + if (fd < 0) { + if (errno == EACCES) + printf("\nYou do not have correct permission, please run as root\n"); + else + perror("Error opening /sys/class/gpio/export"); + + exit(EXIT_FAILURE); + } + + ret = write(fd, gpio, strlen(gpio)); + if((ret >= 0) || ((ret < 0) && (errno == EBUSY))) { + char pathname[80]; + + /* Close the last file descriptor */ + close(fd); + + memset(pathname, '\0', sizeof(pathname)); + sprintf(pathname, "/sys/class/gpio/gpio%d/value", gpio_num); + + fd = open(pathname, O_WRONLY); + if (fd < 0) + perror("GPIO read error"); + else { + if (strncmp(value, "high", 4) == 0) + value[0] = '1'; + else if (strncmp(value, "low", 3) == 0) + value[0] = '0'; + else { + printf("\nInvalid input, please try again...\n"); + return; + } + + /* Write mode into /sys/.../direction file */ + ret = write(fd, value, 1); + if (ret < 0) + perror("Error writing GPIO mode"); + + close(fd); + + /* + * Mark the GPIO as exported, so that we can use + * unexport them during exit. + */ + gpio_in_use[gpio_num] = 1; + } + } else { + if (errno == EINVAL) + printf("\nGPIO number is reserved\n"); + else + perror("Error exporting GPIO number"); + + close(fd); + } + } else if (strncmp(cmdline, "dmesg", 5) == 0) { + if (system("dmesg | grep GPIO") < 0) + perror("Error executing \'dmesg | grep GPIO\'"); + } else if (strncmp(cmdline, "license", 7) == 0) { + show_license(); + } else if (strncmp(cmdline, "exit", 4) == 0) { + int i; + int ret; + char gpio[3 + 1]; + printf("\nExiting...\n"); + for (i = 0; i < AMD_GPIO_NUM_PINS; i++) { + if (gpio_in_use[i]) { + int fd; + fd = open("/sys/class/gpio/unexport", O_WRONLY); + if (fd < 0) { + printf("\nPlease make sure AMD GPIO driver is loaded\n"); + exit(EXIT_FAILURE); + } + memset(gpio, '\0', (3 + 1)); + snprintf(gpio, (3 + 1), "%d", i); + ret = write(fd, gpio, strlen(gpio)); + if (ret < 0) + perror("Error writing to /sys/class/gpio/unexport"); + } + } + exit(EXIT_SUCCESS); + } else { + printf("\nUnknown command\n"); + print_usage(); + } +} + +int main(void) +{ + char *cmdline= NULL; + + printf("GPIO sample application version: %s\n", GPIO_APP_VERSION); + printf("Copyright (c) 2017, Advanced Micro Devices, Inc.\n" + "This sample application comes with ABSOLUTELY NO WARRANTY;\n" + "This is free software, and you are welcome to redistribute it\n" + "under certain conditions; type `license' for details.\n\n"); + + /* Handler for Ctrl+C */ + signal(SIGINT, sighandler); + + while (1) { + cmdline = readline(show_prompt()); + parse_cmd(cmdline); + /* Free the memory malloc'ed by readline */ + free(cmdline); + cmdline = NULL; + } + + /* Should never reach here */ + return 0; +} diff --git a/meta-r1000/recipes-applications/gpio-test/files/gpio-test.h b/meta-r1000/recipes-applications/gpio-test/files/gpio-test.h new file mode 100755 index 00000000..af9c3b68 --- /dev/null +++ b/meta-r1000/recipes-applications/gpio-test/files/gpio-test.h @@ -0,0 +1,17 @@ +#ifndef _GPIO_TEST_H_ +#define _GPIO_TEST_H_ + + + +/* IOCTL numbers */ + +typedef struct { + int offset; + int value; +}debug_data; + +#define GPIO_TEST_IOC_MAGIC 'k' +#define GPIO_IOC_SWCTRLIN _IOW(GPIO_TEST_IOC_MAGIC, 1, debug_data) +#define GPIO_IOC_SWCTRLEN _IOW(GPIO_TEST_IOC_MAGIC, 2, debug_data) + +#endif /* _GPIO_TEST_H_ */ diff --git a/meta-r1000/recipes-applications/gpio-test/gpio-test_1.0.bb b/meta-r1000/recipes-applications/gpio-test/gpio-test_1.0.bb new file mode 100755 index 00000000..ae24dca9 --- /dev/null +++ b/meta-r1000/recipes-applications/gpio-test/gpio-test_1.0.bb @@ -0,0 +1,23 @@ +DESCRIPTION = "Sample application for AMD GPIO driver" +SECTION = "applications" +LICENSE = "BSD" +DEPENDS = "readline" +LIC_FILES_CHKSUM = "file://gpio-test.c;endline=29;md5=e41081b7b159d3f22320c8622cb2d356" + +SRC_URI = "\ + file://gpio-test.c \ + file://gpio-test.h \ + " + +TARGET_CC_ARCH += "${LDFLAGS}" + +S = "${WORKDIR}" + +do_compile() { + ${CC} gpio-test.c -o gpio-test -lreadline +} + +do_install() { + install -d ${D}${bindir} + install -m 0755 gpio-test ${D}${bindir} +} diff --git a/meta-r1000/recipes-applications/spi-test/files/spirom-test.c b/meta-r1000/recipes-applications/spi-test/files/spirom-test.c new file mode 100644 index 00000000..22c90036 --- /dev/null +++ b/meta-r1000/recipes-applications/spi-test/files/spirom-test.c @@ -0,0 +1,798 @@ +/***************************************************************************** +* +* Copyright (c) 2014, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +***************************************************************************/ +#include <stdint.h> +#include <unistd.h> +#include <stdio.h> +#include <stdlib.h> +#include <fcntl.h> +#include <string.h> +#include <dirent.h> +#include <signal.h> + +#include <sys/types.h> +#include <sys/ioctl.h> +#include <sys/stat.h> + +#include <readline/readline.h> + +#include "spirom.h" + +#define SPI_APP_VERSION "1.0" + +static int device_opened = 0; +static char filename[20]; +static int fd = -1; + +char *show_prompt(void) +{ + return "$ "; +} + +void sighandler(int sig) +{ + /* Do nothing. That is the idea. */ +} + +void show_license(void) +{ + printf("/*****************************************************************************\n" + "*\n" + "* Copyright (c) 2014, Advanced Micro Devices, Inc.\n" + "* All rights reserved.\n" + "*\n" + "* Redistribution and use in source and binary forms, with or without\n" + "* modification, are permitted provided that the following conditions are met:\n" + "* * Redistributions of source code must retain the above copyright\n" + "* notice, this list of conditions and the following disclaimer.\n" + "* * Redistributions in binary form must reproduce the above copyright\n" + "* notice, this list of conditions and the following disclaimer in the\n" + "* documentation and/or other materials provided with the distribution.\n" + "* * Neither the name of Advanced Micro Devices, Inc. nor the names of\n" + "* its contributors may be used to endorse or promote products derived\n" + "* from this software without specific prior written permission.\n" + "*\n" + "* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n" + "* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n" + "* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n" + "* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY\n" + "* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n" + "* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n" + "* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n" + "* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n" + "* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n" + "* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n" + "*\n" + "*\n" + "***************************************************************************/\n"); +} + +void print_usage(void) +{ + printf("\nCommands Supported ->\n"); + printf(" enumerate : List all SPI device nodes available\n"); + printf(" setdevice <dev_id> : Set the SPI device number to access\n"); + printf(" wren : Enable Write operation on SPI device\n"); + printf(" wrdi : Disable Write operation on SPI device\n"); + printf(" chiperase : Erase entire ROM chip\n"); + printf(" rdsr : Read status register of ROM device\n"); + printf(" rdid : Read device identification string\n"); + printf(" sectorerase <addr> <num_sectors> : Erase a fixed number of sectors starting at the address\n" + " specified\n"); + printf(" blockerase <addr> <num_blocks> : Erase a fixed number of blocks starting at the address\n" + " specified\n"); + printf(" read <addr> <num_bytes> <filename> : Read a fixed number of bytes starting at address\n" + " specified, and output the contents into file\n"); + printf(" write <addr> <num_bytes> <filename> : Read a fixed number of bytes from file and output\n" + " the contents to the device starting at the address\n" + " specified\n"); + printf(" license : Displays the terms of LICENSE for this application\n"); + printf(" help : Displays help text\n"); + printf(" exit : Exits the application\n\n"); +} + +void parse_cmd(const char *cmdline) +{ + struct spi_ioc_transfer tr; + unsigned int bytes_chunks; + unsigned int remaining_bytes; + int addr; + int ret; + + if (strncmp(cmdline, "enumerate", 9) == 0) { + DIR *dir; + struct dirent *dir_entry; + int device_found = 0; + + /* Get the directory handle */ + if ((dir = opendir("/dev")) == NULL) { + printf("\n\nFailed to open directory /dev. Probably you " + "do not have right privilege!\n\n"); + exit(EXIT_FAILURE); + } + + /* Iterate over all the directory entries */ + while ((dir_entry = readdir(dir)) != NULL) { + /* + * If the file is a character device, and its signature + * matches spirom, then we print the corresponding file. + */ + if ((dir_entry->d_type == DT_CHR) && + (strncmp(dir_entry->d_name, "spirom", 6) == 0)) { + printf("/dev/%s\n", dir_entry->d_name); + device_found = 1; + } + } + + printf("\n"); + + /* + * In case we did not find even a single entry, we print a + * message and exit. + */ + if (!device_found) { + printf("\n\nNo spirom device nodes found, load spirom " + "kernel module and try again\n\n"); + exit(EXIT_FAILURE); + } + } else if (strncmp(cmdline, "setdevice", 9) == 0) { + char input[2 + 1]; + int file_desc; + + cmdline += 10; + memset(input, 0, 3); + if (sscanf(cmdline, "%s", input) < 1) { + printf("\nInvalid inputs, please try again\n\n"); + return; + } + + memset(filename, 0, 20); + snprintf(filename, 19, "/dev/spirom%s", input); + file_desc = open(filename, O_RDWR); + if (file_desc < 0) { + printf("\nError opening file %s\n\n", filename); + return; + } + + /* Once we have validated inputs, we store them into the global + * variables used at other places in the program. + */ + fd = file_desc; + device_opened = 1; + printf("\nSPI device set to /dev/spirom%s\n\n", input); + } else if (strncmp(cmdline, "wren", 4) == 0) { + if (!device_opened) { + printf("\nSPI device needs to be set before you can " + "perform this operation\n\n"); + return; + } + + /* command without data */ + tr.buf[0] = ROM_WREN; + tr.direction = 0; + tr.len = 0; + tr.addr_present = 0; + + ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 1) + printf("\nError executing WREN command\n\n"); + else + printf("\n...WREN completed successfully\n\n"); + } else if (strncmp(cmdline, "wrdi", 4) == 0) { + if (!device_opened) { + printf("\nSPI device needs to be set before you can " + "perform this operation\n\n"); + return; + } + + /* command without data */ + tr.buf[0] = ROM_WRDI; + tr.direction = 0; + tr.len = 0; + tr.addr_present = 0; + + ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 1) + printf("\nError executing WRDI command\n\n"); + else + printf("\n...WRDI completed successfully\n\n"); + } else if (strncmp(cmdline, "chiperase", 9) == 0) { + if (!device_opened) { + printf("\nSPI device needs to be set before you can " + "perform this operation\n\n"); + return; + } + + tr.buf[0] = ROM_RDSR; + tr.direction = RECEIVE; + tr.addr_present = 0; + tr.len = 1; + + ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 1) { + printf("\nError executing RDSR command\n\n");; + return; + } else if ((tr.buf[1] & 0x02) == 0x00) { + printf("\nCannot execute CHIPERASE command, write is disabled\n\n"); + return; + } + + /* Command without data */ + tr.buf[0] = ROM_CHIP_ERASE; + tr.direction = 0; + tr.len = 0; + tr.addr_present = 0; + ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 1) { + printf("\nError executing CHIPERASE command\n\n"); + return; + } + + printf("\n\nCHIPERASE operation in progress, please do not " + " stop in between.\n\n"); + + /* Make sure WIP has been reset */ + while (1) { + memset(&tr, 0, sizeof(struct spi_ioc_transfer)); + tr.buf[0] = ROM_RDSR; + tr.direction = RECEIVE; + tr.addr_present = 0; + tr.len = 1; + + ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 1) { + printf("\nError executing RDSR command\n\n"); + return; + } + + if ((tr.buf[1] & 0x01) == 0x00) + break; + } + + printf("\n\n...CHIPERASE completed successfully\n\n"); + /* Restore signal handler to default */ + } else if (strncmp(cmdline, "rdsr", 4) == 0) { + if (!device_opened) { + printf("\nSPI device needs to be set before you can " + "perform this operation\n\n"); + return; + } + + /* Command with response */ + tr.buf[0] = ROM_RDSR; + tr.direction = RECEIVE; + tr.addr_present = 0; + tr.len = 1; + + ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 1) { + printf("\nError executing RDSR command\n\n"); + return; + } + + /* + * The 1-byte response will be stored in tr.buf, + * so print it out + */ + printf("\nRDSR command returned: 0x%.2x\n\n", tr.buf[1]); + } else if (strncmp(cmdline, "rdid", 4) == 0) { + if (!device_opened) { + printf("\nSPI device needs to be set before you can " + "perform this operation\n\n"); + return; + } + + /* Command with response */ + tr.buf[0] = ROM_RDID; + tr.direction = RECEIVE; + tr.addr_present = 0; + tr.len = 3; + + ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 1) { + printf("\nError executing RDID command\n\n"); + return; + } + + /* + * The 3-bytes response will be stored in tr.buf, + * so print it out + */ + printf("\nRDID command returned: 0x%.2x%.2x%.2x\n", tr.buf[1], + tr.buf[2], tr.buf[3]); + } else if (strncmp(cmdline, "sectorerase", 11) == 0) { + int nsectors; + int i; + + if (!device_opened) { + printf("\nSPI device needs to be set before you can " + "perform this operation\n\n"); + return; + } + + cmdline += 12; + if (sscanf(cmdline, "0x%x 0x%x", &addr, &nsectors) < 2) { + printf("\nInvalid inputs, please try again\n\n"); + return; + } + + tr.buf[0] = ROM_RDSR; + tr.direction = RECEIVE; + tr.addr_present = 0; + tr.len = 1; + + ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 1) { + printf("\nError executing RDSR command\n\n"); + return; + } else if ((tr.buf[1] & 0x02) == 0x00) { + printf("\nCannot execute SECTORERASE command, write is disabled\n\n"); + return; + } + + printf("\n\nSECTORERASE operation in progress, please do not " + " stop in between.\n\n"); + + for (i = 0; i < nsectors; i++) { + /* Write Enable before Sector Erase */ + tr.buf[0] = ROM_WREN; + tr.direction = 0; + tr.len = 0; + tr.addr_present = 0; + ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 1) { + printf("\nError executing WREN command\n\n"); + return; + } + + /* Command with address but no data */ + memset(&tr, 0, sizeof(struct spi_ioc_transfer)); + tr.buf[0] = ROM_SECTOR_ERASE; + tr.buf[3] = addr & 0xff; + tr.buf[2] = (addr >> 8) & 0xff; + tr.buf[1] = (addr >> 16) & 0xff; + tr.addr_present = 1; + tr.direction = 0; + tr.len = 0; + + ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 1) { + printf("\nError executing SECTORERASE command\n\n"); + return; + } + + /* point to the next 4k sector */ + addr += 4 * 1024; + + /* + * Before the next loop, we need to make sure that WIP + * bit in the output of RDSR has been reset. + */ + while (1) { + memset(&tr, 0, sizeof(struct spi_ioc_transfer)); + tr.buf[0] = ROM_RDSR; + tr.direction = RECEIVE; + tr.addr_present = 0; + tr.len = 1; + + ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 1) { + printf("\nError executing RDSR command\n\n"); + return; + } + + if ((tr.buf[1] & 0x01) == 0x00) + break; + } + } + + printf("\n\n...SECTORERASE completed successfully\n\n"); + } else if (strncmp(cmdline, "blockerase", 10) == 0) { + int nblocks; + int i; + + if (!device_opened) { + printf("\nSPI device needs to be set before you can " + "perform this operation\n\n"); + return; + } + + cmdline += 11; + if (sscanf(cmdline, "0x%x 0x%x", &addr, &nblocks) < 2) { + printf("\nInvalid inputs, please try again\n\n"); + return; + } + + tr.buf[0] = ROM_RDSR; + tr.direction = RECEIVE; + tr.addr_present = 0; + tr.len = 1; + + ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 1) { + printf("\nError executing RDSR command\n\n"); + return; + } else if ((tr.buf[1] & 0x02) == 0x00) { + printf("\nError executing BLOCKERASE command, write is disabled\n\n"); + return; + } + + printf("\n\nBLOCKERASE operation in progress, please do not " + " stop in between.\n\n"); + + for (i = 0; i < nblocks; i++) { + /* Write Enable before Block Erase */ + tr.buf[0] = ROM_WREN; + tr.direction = 0; + tr.len = 0; + tr.addr_present = 0; + ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 1) { + printf("\nError executing WREN command\n\n"); + return; + } + + /* Command with address but no data */ + memset(&tr, 0, sizeof(struct spi_ioc_transfer)); + tr.buf[0] = ROM_BLOCK_ERASE; + tr.buf[3] = addr & 0xff; + tr.buf[2] = (addr >> 8) & 0xff; + tr.buf[1] = (addr >> 16) & 0xff; + tr.addr_present = 1; + tr.direction = 0; + tr.len = 0; + + ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 1) { + printf("\nError executing BLOCKERASE command\n\n"); + return; + } + + /* point to the next 64k block */ + addr += 64 * 1024; + + /* + * Before the next loop, we need to make sure that WIP + * bit in the output of RDSR has been reset. + */ + while (1) { + memset(&tr, 0, sizeof(struct spi_ioc_transfer)); + tr.buf[0] = ROM_RDSR; + tr.direction = RECEIVE; + tr.addr_present = 0; + tr.len = 1; + + ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 1) { + printf("\nError executing RDSR command\n\n"); + return; + } + + if ((tr.buf[1] & 0x01) == 0x00) + break; + } + } + + printf("\n\n...BLOCKERASE completed successfully\n\n"); + } else if (strncmp(cmdline, "read", 4) == 0) { + int nbytes; + int outfile_fd; + int i; + + if (!device_opened) { + printf("\nSPI device needs to be set before you can " + "perform this operation\n\n"); + return; + } + + cmdline += 5; + memset(filename, 0, 20); + if (sscanf(cmdline, "0x%x 0x%x %s", &addr, &nbytes, filename) < 3) { + printf("\nInvalid inputs, please try again\n\n"); + return; + } + + /* + * Open the output file for writing. Create a new file if not + * there, and empty the file before writing if file already + * exists. + */ + outfile_fd = open(filename, O_WRONLY | O_CREAT | O_TRUNC, 0644); + if (outfile_fd < 0) { + printf("\nError opening file %s for writing\n\n", filename); + return; + } + + /* + * We will break down the bytes to be received in chunks of + * of 64-bytes. Data might not be a even multiple of 64. So + * in that case, we will have some remaining bytes <4. We + * handle that separately. + */ + bytes_chunks = nbytes / 64; + remaining_bytes = nbytes % 64; + + printf("\n\nREAD operation in progress.\n\n"); + + for (i = 0; i < bytes_chunks; i++) { + /* Command with address and data */ + memset(&tr, 0, sizeof(struct spi_ioc_transfer)); + tr.buf[0] = ROM_READ; + tr.direction = RECEIVE; + /* + * We will store the address into the buffer in little + * endian order. + */ + tr.buf[3] = addr & 0xff; + tr.buf[2] = (addr >> 8) & 0xff; + tr.buf[1] = (addr >> 16) & 0xff; + tr.len = 64; + tr.addr_present = 1; + + ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 1) { + printf("\nError executing READ command\n\n"); + return; + } + + /* Write the data read to output file */ + if (write(outfile_fd, &tr.buf[4], tr.len) < 0) { + printf("\nError writing to file %s\n\n", filename); + return; + } + addr += 64; + } + + if (remaining_bytes) { + memset(&tr, 0, sizeof(struct spi_ioc_transfer)); + tr.buf[0] = ROM_READ; + tr.direction = RECEIVE; + tr.buf[3] = addr & 0xff; + tr.buf[2] = (addr >> 8) & 0xff; + tr.buf[1] = (addr >> 16) & 0xff; + tr.len = remaining_bytes; + tr.addr_present = 1; + + ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 1) { + printf("\nError executing READ command\n\n"); + return; + } + + if (write(outfile_fd, &tr.buf[4], tr.len) < 0) { + printf("\nError writing to file %s\n\n", filename); + return; + } + } + + printf("\n\n...READ completed successfully\n\n"); + close(outfile_fd); + } else if (strncmp(cmdline, "write", 5) == 0) { + int nbytes; + int infile_fd; + int i; + + if (!device_opened) { + printf("\nSPI device needs to be set before you can " + "perform this operation\n\n"); + return; + } + + cmdline += 6; + memset(filename, 0, 20); + if (sscanf(cmdline, "0x%x 0x%x %s", &addr, &nbytes, filename) < 3) { + printf("\nInvalid inputs, please try again\n\n"); + return; + } + + /* Open the input file for reading*/ + infile_fd = open(filename, O_RDONLY); + if (infile_fd < 0) { + printf("\nError opening file %s for reading\n\n", filename); + return; + } + + /* + * We will break down the bytes to be transmitted in chunks of + * of 64-bytes. Like for read, we might not have data in an + * even multiple of 64 bytes. So we will handle the remaining + * bytes in the end. + */ + tr.buf[0] = ROM_RDSR; + tr.direction = RECEIVE; + tr.addr_present = 0; + tr.len = 1; + + ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 1) { + printf("\nError executing RDSR command\n\n"); + return; + } else if ((tr.buf[1] & 0x02) == 0x00) { + printf("\nCannot execute WRITE command, write is disabled\n\n"); + return; + } + + bytes_chunks = nbytes / 64; + remaining_bytes = nbytes % 64; + + printf("\n\nWRITE operation in progress, please do not " + " stop in between.\n\n"); + + for (i = 0; i < bytes_chunks; i++) { + tr.buf[0] = ROM_WREN; + tr.direction = 0; + tr.len = 0; + tr.addr_present = 0; + ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 1) { + printf("\nError executing WREN command\n\n"); + return; + } + + /* Command with data and address */ + memset(&tr, 0, sizeof(struct spi_ioc_transfer)); + tr.buf[0] = ROM_WRITE; + tr.direction = TRANSMIT; + /* + * We will store the address into the buffer in little + * endian order. + */ + tr.buf[3] = addr & 0xff; + tr.buf[2] = (addr >> 8) & 0xff; + tr.buf[1] = (addr >> 16) & 0xff; + tr.len = 64; + tr.addr_present = 1; + + /* Read 64 bytes from input file to buffer */ + if (read(infile_fd, &tr.buf[4], tr.len) < 0) { + printf("\nError reading from file %s\n\n", filename); + return; + } + + ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 1) { + printf("\nError executing WRITE command\n\n"); + return; + } + + addr += 64; + + /* + * Before the next loop, we need to make sure that WIP + * bit in the output of RDSR has been reset. + */ + while (1) { + memset(&tr, 0, sizeof(struct spi_ioc_transfer)); + tr.buf[0] = ROM_RDSR; + tr.direction = RECEIVE; + tr.addr_present = 0; + tr.len = 1; + + ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 1) { + printf("\nError executing RDSR command\n\n"); + return; + } + + if ((tr.buf[1] & 0x01) == 0x00) + break; + } + } + + if (remaining_bytes) { + tr.buf[0] = ROM_WREN; + tr.direction = 0; + tr.len = 0; + tr.addr_present = 0; + ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 1) { + printf("\nError executing WREN command\n\n"); + return; + } + + memset(&tr, 0, sizeof(struct spi_ioc_transfer)); + tr.buf[0] = ROM_WRITE; + tr.direction = TRANSMIT; + tr.buf[3] = addr & 0xff; + tr.buf[2] = (addr >> 8) & 0xff; + tr.buf[1] = (addr >> 16) & 0xff; + tr.len = remaining_bytes; + tr.addr_present = 1; + + if (read(infile_fd, &tr.buf[4], tr.len) < 0) { + printf("\nError reading from file %s\n\n", filename); + return; + } + + ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 1) { + printf("\nError executing WRITE command\n\n"); + return; + } + + while (1) { + memset(&tr, 0, sizeof(struct spi_ioc_transfer)); + tr.buf[0] = ROM_RDSR; + tr.direction = RECEIVE; + tr.addr_present = 0; + tr.len = 1; + + ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 1) { + printf("\nError executing RDSR command\n\n"); + return; + } + + if ((tr.buf[1] & 0x01) == 0x00) + break; + } + } + + printf("\n\n...WRITE completed successfully\n\n"); + close(infile_fd); + } else if (strncmp(cmdline, "license", 7) == 0) { + show_license(); + } else if (strncmp(cmdline, "exit", 4) == 0) { + printf("\nExiting...\n"); + close(fd); + exit(EXIT_SUCCESS); + } else if (strncmp(cmdline, "help", 4) == 0) { + print_usage(); + } else { + printf("\nUnknown command\n"); + print_usage(); + } +} + +int main(void) +{ + char *cmdline= NULL; + + printf("SPI sample application version: %s\n", SPI_APP_VERSION); + printf("Copyright (c) 2014, Advanced Micro Devices, Inc.\n" + "This sample application comes with ABSOLUTELY NO WARRANTY;\n" + "This is free software, and you are welcome to redistribute it\n" + "under certain conditions; type `license` for details.\n\n"); + + /* Set the signal handler */ + signal(SIGINT, sighandler); + + while (1) { + cmdline = readline(show_prompt()); + parse_cmd(cmdline); + /* Free the memory malloc'ed by readline */ + free(cmdline); + } + + /* Restore the default signal handler */ + signal(SIGINT, SIG_DFL); + + /* Should never reach here */ + return 0; +} diff --git a/meta-r1000/recipes-applications/spi-test/files/spirom.h b/meta-r1000/recipes-applications/spi-test/files/spirom.h new file mode 100644 index 00000000..f599925f --- /dev/null +++ b/meta-r1000/recipes-applications/spi-test/files/spirom.h @@ -0,0 +1,53 @@ +#ifndef SPIROM_H +#define SPIROM_H + +#include <linux/types.h> + +/*---------------------------------------------------------------------------*/ + +/* IOCTL commands */ + +#define SPI_IOC_MAGIC 'k' + +#define TRANSMIT 1 +#define RECEIVE 2 + +/* + * struct spi_ioc_transfer - interface structure between application and ioctl + * + * @buf: Buffer to hold 1-byte command, 3-bytes address, and 4-byte data for + * transmit or receive. The internal FIFO of our controller can hold a + * maximum of 8 bytes, including the address. But here we assume the + * maximum data excluding address to be 4-bytes long. + * + * @direction: Direction of data transfer, either TRANSMIT or RECEIVE. + * + * @len: Length of data excluding command and address. + * + * @addr_present: Flag to indicate whether 'buf' above contains an address. + */ +struct spi_ioc_transfer { + __u8 buf[64 + 1 + 3]; + __u8 direction; + __u8 len; + __u8 addr_present; +}; + +/* not all platforms use <asm-generic/ioctl.h> or _IOC_TYPECHECK() ... */ +#define SPI_MSGSIZE(N) \ + ((((N)*(sizeof (struct spi_ioc_transfer))) < (1 << _IOC_SIZEBITS)) \ + ? ((N)*(sizeof (struct spi_ioc_transfer))) : 0) +#define SPI_IOC_MESSAGE(N) _IOW(SPI_IOC_MAGIC, 0, char[SPI_MSGSIZE(N)]) + +/* SPI ROM command codes */ +#define ROM_WREN 0x06 +#define ROM_WRDI 0x04 +#define ROM_RDSR 0x05 +#define ROM_RDID 0x9F +#define ROM_CHIP_ERASE 0x60 +#define ROM_SECTOR_ERASE 0x20 +#define ROM_BLOCK_ERASE 0xD8 +#define ROM_READ 0x03 +#define ROM_WRITE 0x02 + +#endif /* SPIROM_H */ diff --git a/meta-r1000/recipes-applications/spi-test/spi-test_1.0.bb b/meta-r1000/recipes-applications/spi-test/spi-test_1.0.bb new file mode 100644 index 00000000..764f112a --- /dev/null +++ b/meta-r1000/recipes-applications/spi-test/spi-test_1.0.bb @@ -0,0 +1,22 @@ +DESCRIPTION = "Sample application for AMD SPI driver" +SECTION = "applications" +LICENSE = "BSD" +DEPENDS = "readline" +LIC_FILES_CHKSUM = "file://spirom-test.c;endline=29;md5=8e7a9706367d146e5073510a6e176dc2" + +SRC_URI = "file://spirom-test.c \ + file://spirom.h \ + " + +S = "${WORKDIR}" + +TARGET_CC_ARCH += "${LDFLAGS}" + +do_compile() { + ${CC} spirom-test.c -o spirom-test -lreadline +} + +do_install() { + install -d ${D}${bindir} + install -m 0755 spirom-test ${D}${bindir} +} diff --git a/meta-r1000/recipes-bsp/formfactor/formfactor/r1000/machconfig b/meta-r1000/recipes-bsp/formfactor/formfactor/r1000/machconfig new file mode 100644 index 00000000..28ca080e --- /dev/null +++ b/meta-r1000/recipes-bsp/formfactor/formfactor/r1000/machconfig @@ -0,0 +1,3 @@ +# Assume a USB mouse and keyboard are connected +HAVE_TOUCHSCREEN=n +HAVE_KEYBOARD=y diff --git a/meta-r1000/recipes-bsp/formfactor/formfactor_0.0.bbappend b/meta-r1000/recipes-bsp/formfactor/formfactor_0.0.bbappend new file mode 100644 index 00000000..6d4804d1 --- /dev/null +++ b/meta-r1000/recipes-bsp/formfactor/formfactor_0.0.bbappend @@ -0,0 +1,2 @@ +FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:" + diff --git a/meta-r1000/recipes-core/packagegroups/packagegroup-multimedia-risky.bbappend b/meta-r1000/recipes-core/packagegroups/packagegroup-multimedia-risky.bbappend new file mode 100644 index 00000000..123508ed --- /dev/null +++ b/meta-r1000/recipes-core/packagegroups/packagegroup-multimedia-risky.bbappend @@ -0,0 +1 @@ +RDEPENDS_${PN}_append_r1000 = " ffmpeg" diff --git a/meta-r1000/recipes-devtools/glslang/glslang/0002-spirv-do-not-install-conflicting-headers.patch b/meta-r1000/recipes-devtools/glslang/glslang/0002-spirv-do-not-install-conflicting-headers.patch new file mode 100644 index 00000000..69e64060 --- /dev/null +++ b/meta-r1000/recipes-devtools/glslang/glslang/0002-spirv-do-not-install-conflicting-headers.patch @@ -0,0 +1,30 @@ +From 1823de236f38fc7eb7caedec666c9dde956832cd Mon Sep 17 00:00:00 2001 +From: Awais Belal <awais_belal@mentor.com> +Date: Wed, 31 May 2017 13:04:42 +0500 +Subject: [PATCH] spirv: do not install conflicting headers + +These headers are already provided by the +spirv-tools package so there's no need of +installing them here again. + +Signed-off-by: Awais Belal <awais_belal@mentor.com> +--- + SPIRV/CMakeLists.txt | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/SPIRV/CMakeLists.txt b/SPIRV/CMakeLists.txt +index aaf11780..d5c43723 100755 +--- a/SPIRV/CMakeLists.txt ++++ b/SPIRV/CMakeLists.txt +@@ -12,8 +12,6 @@ set(SPVREMAP_SOURCES + + set(HEADERS + bitutils.h +- spirv.hpp +- GLSL.std.450.h + GLSL.ext.KHR.h + GlslangToSpv.h + hex_float.h +-- +2.11.1 + diff --git a/meta-r1000/recipes-devtools/glslang/glslang_git.bb b/meta-r1000/recipes-devtools/glslang/glslang_git.bb new file mode 100644 index 00000000..bc749b40 --- /dev/null +++ b/meta-r1000/recipes-devtools/glslang/glslang_git.bb @@ -0,0 +1,23 @@ +SUMMARY = "An OpenGL and OpenGL ES shader front end and validator." +DESCRIPTION = "Glslang is the official reference compiler front end \ + for the OpenGL ES and OpenGL shading languages. It \ + implements a strict interpretation of the specifications \ + for these languages. It is open and free for anyone to use, \ + either from a command line or programmatically." +SECTION = "graphics" +HOMEPAGE = "https://www.khronos.org/opengles/sdk/tools/Reference-Compiler" + +inherit cmake + +LICENSE = "BSD" +LIC_FILES_CHKSUM = "file://glslang/Include/Types.h;beginline=1;endline=36;md5=9dbd36d87d27a0c98a6f4d72afaa9cf8" + +S = "${WORKDIR}/git" + +SRCREV = "2651ccaec8170b3257642b3c438f50dc4f181fdd" +SRC_URI = "git://github.com/KhronosGroup/glslang \ + file://0002-spirv-do-not-install-conflicting-headers.patch" + +FILES_${PN} += "${libdir}/*" + +BBCLASSEXTEND = "native nativesdk" diff --git a/meta-r1000/recipes-devtools/rgp/files/License.rtf b/meta-r1000/recipes-devtools/rgp/files/License.rtf new file mode 100644 index 00000000..0bcb1a27 --- /dev/null +++ b/meta-r1000/recipes-devtools/rgp/files/License.rtf @@ -0,0 +1,748 @@ +{\rtf1\adeflang1025\ansi\ansicpg1252\uc1\adeff0\deff0\stshfdbch0\stshfloch0\stshfhich0\stshfbi0\deflang1033\deflangfe1033\themelang1033\themelangfe0\themelangcs0{\fonttbl{\f0\fbidi \froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;}{\f1\fbidi \fswiss\fcharset0\fprq2{\*\panose 020b0604020202020204}Arial;}
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+THEREOF, (COLLECTIVELY "SOFTWARE") UNTIL YOU HAVE CAREFULLY READ AND AGREED TO THE FOLLOWING TERMS AND CONDITIONS. THIS IS A LEGAL AGREEMENT ("AGREEMENT") BETWEEN YOU (EITHER AN INDIVIDUAL OR AN ENTITY) ("YOU}{\rtlch\fcs1 \af0\afs18 \ltrch\fcs0
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+a condition of use, modification or distribution, that any resulting software must be (a) disclosed or distributed in source code form; (b) licensed for the purpose of making derivative works; or (c) redistributable at no charge.
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+ means all copyrights, trademarks, trade secrets, patents, mask works, and all related, similar, or other intellectual property rights recognized in any jurisdiction worldwide, including all applications and registrations with respect thereto.
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+\b\f37\fs20\cf0\insrsid15347899\charrsid15953908 1.}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \b\f37\fs20\cf0\insrsid2256315\charrsid15953908 4}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\cf0\insrsid15347899\charrsid15953908 \tab }{\rtlch\fcs1 \af37\afs20
+\ltrch\fcs0 \f37\fs20\insrsid13580638\charrsid15953908 \'93}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \b\f37\fs20\insrsid2182777\charrsid15953908 Object Code}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid13580638\charrsid15953908 \'94}{\rtlch\fcs1
+\af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid2182777\charrsid15953908 }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid16065812\charrsid15953908 means machine readable computer programming code files, which is not in a human readable form.}{
+\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid2182777\charrsid15953908
+\par }\pard\plain \ltrpar\s27\qj \li0\ri0\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid4329051 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af37
+\ltrch\fcs0 \f37\insrsid4329051\charrsid15953908
+\par }\pard\plain \ltrpar\s28\qj \li0\ri0\widctlpar\wrapdefault\faauto\rin0\lin0\itap0\pararsid8474037 \rtlch\fcs1 \af40\afs24\alang1025 \ltrch\fcs0 \f40\fs24\cf1\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\b\f37\fs20\insrsid2182777\charrsid15953908 2.}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \b\f37\fs20\insrsid15347899\charrsid15953908 \tab }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \b\f37\fs20\insrsid15164937\charrsid15953908 LICENSE}{\rtlch\fcs1 \af37\afs20
+\ltrch\fcs0 \b\f37\fs20\insrsid2182777\charrsid15953908 . }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid15347899\charrsid15953908 Subject to the terms and conditions of this Agreement, AMD hereby grants }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid3610293\charrsid15953908 You}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid15347899\charrsid15953908 a non-exclusive, royalty-free, revocable, non-transferable, limited, copyright license to}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid3634846\charrsid15953908 :
+\par }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid3610981\charrsid15953908 }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid3634846\charrsid15953908
+\par {\listtext\pard\plain\ltrpar \s28 \rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\cf1\insrsid3634846\charrsid15953908 \hich\af37\dbch\af0\loch\f37 a)\tab}}\pard \ltrpar
+\s28\qj \fi-360\li1080\ri0\widctlpar\wrapdefault\faauto\ls13\rin0\lin1080\itap0\pararsid3634846 {\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid3634846\charrsid15953908 install, use and copy the }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid8792582\charrsid15953908 Software}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid3634846\charrsid15953908 for internal use only at }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid3610293\charrsid15953908 Your }{\rtlch\fcs1
+\af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid3634846\charrsid15953908 sites solely for the purpose of evaluating the }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid8792582\charrsid15953908 Software}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid3634846\charrsid15953908 for use with AMD\rquote s products as used with }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid3610293\charrsid15953908 Your}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid3634846\charrsid15953908
+ products; and
+\par }\pard \ltrpar\s28\qj \li1080\ri0\widctlpar\wrapdefault\faauto\rin0\lin1080\itap0\pararsid9581323 {\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\expnd0\expndtw-3\insrsid3634846\charrsid15953908
+\par {\listtext\pard\plain\ltrpar \s28 \rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\cf1\insrsid5986648\charrsid15953908 \hich\af37\dbch\af0\loch\f37 b)\tab}}\pard \ltrpar
+\s28\qj \fi-360\li1080\ri0\widctlpar\wrapdefault\faauto\ls13\rin0\lin1080\itap0\pararsid9581323 {\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid5986648\charrsid15953908 distribute}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid2571866\charrsid15953908 and sublicense}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid5986648\charrsid15953908 the }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid8792582\charrsid15953908 Software}{\rtlch\fcs1
+\af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid2571866\charrsid15953908 to customers and end users}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid8474037\charrsid15953908 (}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid11292190\charrsid15953908 collectively}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid6625424\charrsid15953908 ,}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid11292190\charrsid15953908 }{\rtlch\fcs1 \af37\afs20
+\ltrch\fcs0 \f37\fs20\insrsid8474037\charrsid15953908 \'93Distribution Channel\'94)}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid2571866\charrsid15953908 for use }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid10360060\charrsid15953908
+with AMD products when incorporated within}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid2571866\charrsid15953908 }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid3610293\charrsid15953908 Your}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid2571866\charrsid15953908 }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid3610981\charrsid15953908 p}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid2571866\charrsid15953908 roducts. }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid1924963\charrsid15953908 Such distribution may be made }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid5986648\charrsid15953908 through multiple tiers of distribution}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid8474037\charrsid15953908 , only subject to an end user license agreement that meet }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid539192\charrsid15953908 the requirements in section 2}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid2886127\charrsid15953908 .}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid539192\charrsid15953908 1}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid5588138\charrsid15953908 . }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\expnd0\expndtw-3\insrsid1791298\charrsid15953908
+\par }\pard \ltrpar\s28\qj \li0\ri0\widctlpar\wrapdefault\faauto\rin0\lin0\itap0\pararsid8474037 {\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\expnd0\expndtw-3\insrsid8474037\charrsid15953908
+\par }\pard \ltrpar\s28\qj \li0\ri0\widctlpar\wrapdefault\faauto\rin0\lin0\itap0\pararsid4329051 {\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \b\f37\fs20\insrsid539192\charrsid15953908 2.1}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid8474037\charrsid15953908
+\tab }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \b\f37\fs20\insrsid1791298\charrsid15953908 End User License Agreement}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid1791298\charrsid15953908 .}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid8474037\charrsid15953908 \~ Distribution of }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid8792582\charrsid15953908 Software}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid8474037\charrsid15953908 by }{\rtlch\fcs1
+\af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid3610293\charrsid15953908 You}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid8474037\charrsid15953908 and }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid8792582\charrsid15953908 Your}{\rtlch\fcs1
+\af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid8474037\charrsid15953908 Distribution C}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid1791298\charrsid15953908 hannel will be pu}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid5588138\charrsid15953908 rsuant to an enforceable end user}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid1791298\charrsid15953908 license agreement}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid5390130\charrsid15953908 (
+\'93End User License Agreement\'94)}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid5588138\charrsid15953908 with}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid1791298\charrsid15953908 }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid5588138\charrsid15953908 terms and conditions }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid5390130\charrsid15953908 that at a minimum are }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid1791298\charrsid15953908
+substantially similar to those set forth in Section }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid8474037\charrsid15953908 3}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid5390130\charrsid15953908 and the following}{\rtlch\fcs1
+\af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid1791298\charrsid15953908 : (a) prohibition on transfer or duplication of the }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid8792582\charrsid15953908 Software}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid1791298\charrsid15953908 (except for reasonable backup); }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid11292190\charrsid15953908 (b}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid1791298\charrsid15953908
+) prohibitions on reverse engineering (unless }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid11292190\charrsid15953908 allowed }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid1791298\charrsid15953908
+by law for interoperability), disassembly or de-compilation of the }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid8792582\charrsid15953908 Software}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid1791298\charrsid15953908
+; (d) disclaimer, to the extent permitted by applicable law,}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid11292190\charrsid15953908 of}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid1791298\charrsid15953908 }{\rtlch\fcs1 \af37\afs20
+\ltrch\fcs0 \f37\fs20\insrsid3610293\charrsid15953908 You }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid1791298\charrsid15953908 and }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid8792582\charrsid15953908 Your}{\rtlch\fcs1 \af37\afs20
+\ltrch\fcs0 \f37\fs20\insrsid1791298\charrsid15953908 licensors\rquote liability for any damages, whether}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid11292190\charrsid15953908 punitive,}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid2905745\charrsid15953908 direct,}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid1791298\charrsid15953908 incidental,}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid11292190\charrsid15953908 indirect, special}{\rtlch\fcs1
+\af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid1791298\charrsid15953908 or consequential}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid11292190\charrsid15953908 damages}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid1791298\charrsid15953908
+, arising from the use of}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid11292190\charrsid15953908 , or distribution of}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid1791298\charrsid15953908 the }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid8792582\charrsid15953908 Software}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid1791298\charrsid15953908
+; (f) requirement that the end user comply fully with all relevant export laws and regulations of the United States and other applicable export and import laws; and (g) notification to the end user that the }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid8792582\charrsid15953908 Software}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid1791298\charrsid15953908 is subject to a restricted license and can only be used in conjunction with the intended AMD products.\~ }{\rtlch\fcs1
+\af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid3610293\charrsid15953908 You}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid1791298\charrsid15953908 will be financially responsible for all claims and damages to AMD caused by a breach of this Section 2.}{
+\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid539192\charrsid15953908 1}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid1791298\charrsid15953908 . AMD is a }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid5390130\charrsid15953908 t
+hird party beneficiary of any End User License A}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid1791298\charrsid15953908 greement.}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid4329051\charrsid15953908
+\par }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid1390833\charrsid15953908
+\par }\pard \ltrpar\s28\qj \li0\ri0\widctlpar\wrapdefault\faauto\rin0\lin0\itap0\pararsid16479123 {\rtlch\fcs1 \ab\af37\afs20 \ltrch\fcs0 \b\f37\fs20\insrsid2886127\charrsid15953908 3}{\rtlch\fcs1 \ab\af37\afs20 \ltrch\fcs0
+\b\f37\fs20\insrsid16479123\charrsid15953908 .\tab RESTRICTIONS. }{\rtlch\fcs1 \ab\af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid16479123\charrsid15953908 Except for the limited license }{\rtlch\fcs1 \ab\af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid11292190\charrsid15953908 expressly }{\rtlch\fcs1 \ab\af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid16479123\charrsid15953908 granted }{\rtlch\fcs1 \ab\af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid11292190\charrsid15953908 in Section 2 }{
+\rtlch\fcs1 \ab\af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid16479123\charrsid15953908 herein, }{\rtlch\fcs1 \ab\af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid3610293\charrsid15953908 You}{\rtlch\fcs1 \ab\af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid16479123\charrsid15953908 }{\rtlch\fcs1 \ab\af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid11292190\charrsid15953908 h}{\rtlch\fcs1 \ab\af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid5074736\charrsid15953908 ave}{\rtlch\fcs1 \ab\af37\afs20
+\ltrch\fcs0 \f37\fs20\insrsid11292190\charrsid15953908 }{\rtlch\fcs1 \ab\af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid16479123\charrsid15953908 no other rights in the }{\rtlch\fcs1 \ab\af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid8792582\charrsid15953908 Software}
+{\rtlch\fcs1 \ab\af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid16479123\charrsid15953908 , whether express, implied, ari}{\rtlch\fcs1 \ab\af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid1311139\charrsid15953908 sing by estoppel or otherwise. }{\rtlch\fcs1
+\ab\af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid16479123\charrsid15953908 Further }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid16479123\charrsid15953908 restrictions regarding }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid3610293\charrsid15953908 Your }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid16479123\charrsid15953908 use of the }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid8792582\charrsid15953908 Software}{\rtlch\fcs1 \af37\afs20
+\ltrch\fcs0 \f37\fs20\insrsid16479123\charrsid15953908 }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid10845177\charrsid15953908 are set forth below}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid16479123\charrsid15953908 . }{\rtlch\fcs1
+\af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid10845177\charrsid15953908 Except as expressly authorized herein, }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid3610293\charrsid15953908 You}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid16479123\charrsid15953908 may not:
+\par }\pard \ltrpar\s28\qj \li0\ri0\widctlpar\wrapdefault\faauto\rin0\lin0\itap0\pararsid4329051 {\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid16479123\charrsid15953908
+\par {\listtext\pard\plain\ltrpar \s28 \rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \b\f37\fs20\cf1\insrsid16479123\charrsid15953908 \hich\af37\dbch\af0\loch\f37 a)\tab}}\pard \ltrpar
+\s28\qj \fi-360\li720\ri0\widctlpar\wrapdefault\faauto\ls11\rin0\lin720\itap0\pararsid16479123 {\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid16479123\charrsid15953908 modify or create derivative works of the }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
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+\f37\fs20\insrsid16479123\charrsid15953908 or (iii) modify }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid3610293\charrsid15953908 Your }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid16479123\charrsid15953908
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+\par }\pard \ltrpar\s28\qj \fi-360\li720\ri0\widctlpar\wrapdefault\faauto\rin0\lin720\itap0\pararsid16479123 {\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid2256315\charrsid15953908
+\par }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid9581323\charrsid15953908
+\par }\pard \ltrpar\s28\qj \li0\ri0\widctlpar\wrapdefault\faauto\rin0\lin0\itap0\pararsid4329051 {\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \b\f37\fs20\expnd0\expndtw-3\insrsid3243892\charrsid15953908 4}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
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+ shall have no right, title or interest therein except as expressly set forth in this Agreement.}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\expnd0\expndtw-3\insrsid12583395\charrsid15953908
+\par }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\ul\expnd0\expndtw-3\insrsid11487463\charrsid15953908
+\par }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \b\f37\fs20\insrsid3243892\charrsid15953908 5}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \b\f37\fs20\insrsid11560611\charrsid15953908 .\tab }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \b\f37\fs20\insrsid8019640\charrsid15953908
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+\f37\fs20\insrsid15164937\charrsid15953908 ha}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid1598747\charrsid15953908 ve}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid15164937\charrsid15953908
+ no obligation to give AMD any suggestions, comments or other feedback (\'93Feedback\'94) relating to the }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid8792582\charrsid15953908 Software}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid15164937\charrsid15953908 . However, AMD may use and include any Feedback that it receives from }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid3610293\charrsid15953908 You}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid15164937\charrsid15953908 to improve the }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid8792582\charrsid15953908 Software}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid15164937\charrsid15953908
+ or other AMD products, software and technologies. Accordingly, for any Feedback }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid3610293\charrsid15953908 You}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid15164937\charrsid15953908
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+AMD and its affiliates and subsidiaries a worldwide, non-exclusive, irrevocable, royalty-free, perpetual license to, directly or indirectly, use, reproduce, license, sublicense, distribute, make
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+Rights of any third party or (b) is subject to license terms which seek to require any products incorporating or derived fr}{\rtlch\fcs1 \af31506\afs20 \ltrch\fcs0 \f31506\fs20\insrsid5390130\charrsid8205376 om such Feedback, or other AMD Intellectual P}{
+\rtlch\fcs1 \af31506\afs20 \ltrch\fcs0 \f31506\fs20\insrsid15164937\charrsid8205376 roperty, to be licensed to or otherwise shared with any third party.}{\rtlch\fcs1 \af31506\afs20 \ltrch\fcs0 \f31506\fs20\insrsid10111961\charrsid8205376
+\par }{\rtlch\fcs1 \af31506\afs20 \ltrch\fcs0 \b\f31506\fs20\insrsid8205376\charrsid8205376
+\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid9053797 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af31506
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+. The Software, including all Intellectual Property Rights therein, is and remains the sole and exclusive property of AMD or its licensors, and You shall have no right, title or interest therein
+except as expressly set forth in this Agreement. You agree to prevent any unauthorized copying of the Software. All title in and to the Software, all copies thereof (in whole or in part, and in any form), and all rights and Intellectual Property Rights t
+herein shall remain vested in AMD. Except as expressly provided in Section 2 herein, AMD does not grant any express or implied right to You under AMD patents, copyrights, trademarks, or trade secret information.
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+\ltrch\fcs0 \f31506\cf1\insrsid9250421\charrsid8205376 The following policies apply to Your Use of the Software:
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+\par {\listtext\pard\plain\ltrpar \s27 \rtlch\fcs1 \af42\afs20 \ltrch\fcs0 \f31506\fs20\cf1\insrsid9250421\charrsid8205376 \hich\af31506\dbch\af0\loch\f31506 (a)\tab}}\pard\plain \ltrpar\s27\ql \fi-270\li270\ri0\sl240\slmult0
+\widctlpar\wrapdefault\aspalpha\aspnum\faauto\ls17\adjustright\rin0\lin270\itap0\pararsid12857070\contextualspace \cbpat8 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af31506
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+, sets out the terms which AMD processes any personal information collected from You, or that You provide to AMD. By agreeing to this Agreement, You consent to such processing, acknowledge that You have read and agree to such policy, and You warrant that
+all information provided by You is accurate.
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+\ltrch\fcs0 \b\f31506\insrsid1577702\charrsid8205376
+\par }{\rtlch\fcs1 \af31506 \ltrch\fcs0 \b\f31506\insrsid5315391\charrsid8205376 6}{\rtlch\fcs1 \af31506 \ltrch\fcs0 \b\f31506\insrsid1577702\charrsid8205376 .\tab }{\rtlch\fcs1 \af31506 \ltrch\fcs0 \b\f31506\insrsid5794662\charrsid8205376
+SUPPORT AND UPDATES. }{\rtlch\fcs1 \af31506 \ltrch\fcs0 \f31506\insrsid5794662\charrsid8205376 AMD is under no obligation to provide any kind of support under this Agreement. AMD may, in its sole discretion, provide to }{\rtlch\fcs1 \af31506
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+\ltrch\fcs0 \f31506\insrsid5794662\charrsid8205376 , and such updates will be covered under this Agreement.\~
+\par }\pard\plain \ltrpar\s28\qj \li0\ri0\widctlpar\wrapdefault\faauto\rin0\lin0\itap0\pararsid2494828 \rtlch\fcs1 \af40\afs24\alang1025 \ltrch\fcs0 \f40\fs24\cf1\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af31506\afs20 \ltrch\fcs0
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+\par }\pard\plain \ltrpar\s1\ql \li0\ri0\sa120\keep\keepn\nowidctlpar\tx360\wrapdefault\aspalpha\aspnum\faauto\outlinelevel0\adjustright\rin0\lin0\itap0\pararsid2494828 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0
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+\par }\pard\plain \ltrpar\s28\qj \li0\ri0\widctlpar\wrapdefault\faauto\rin0\lin0\itap0\pararsid2494828 \rtlch\fcs1 \af40\afs24\alang1025 \ltrch\fcs0 \f40\fs24\cf1\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
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+\af37\afs20 \ltrch\fcs0 \b\f37\fs20\insrsid2182777\charrsid15953908 .}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid2182777\charrsid15953908 }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid16479123\charrsid15953908 THE }{\rtlch\fcs1
+\af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid8792582\charrsid15953908 SOFTWARE}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid16479123\charrsid15953908
+ IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND. AMD DISCLAIMS ALL WARRANTIES, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE,}{\rtlch\fcs1 \af37\afs20
+\ltrch\fcs0 \f37\fs20\insrsid5390130\charrsid15953908 AND}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid16479123\charrsid15953908 NON-INFRINGEMENT}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid5390130\charrsid15953908 ,}{\rtlch\fcs1
+\af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid2769501\charrsid15953908 }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid16479123\charrsid15953908 THAT THE }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid8792582\charrsid15953908 SOFTWARE}{
+\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid16479123\charrsid15953908 WILL RUN UNINTERRUPTED OR ERROR-FREE OR }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid6762244\charrsid15953908 WARRANTIES }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid16479123\charrsid15953908 ARISING FROM CUSTOM OF TRADE OR COURSE OF USAGE. THE ENTIRE RISK ASSOCIATED WITH THE USE OF THE }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid8792582\charrsid15953908 SOFTWARE}{\rtlch\fcs1 \af37\afs20
+\ltrch\fcs0 \f37\fs20\insrsid16479123\charrsid15953908 IS ASSUMED BY }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid3610293\charrsid15953908 YOU}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid11431762\charrsid15953908
+ INCLUDING, WITHOUT LIMITATION, THE RISK OF DATA CORRUPTION OR LOSS}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid16479123\charrsid15953908
+. Some jurisdictions do not allow the exclusion of implied warranties, so the above exclusion may not apply to }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid3610293\charrsid15953908 You}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid16479123\charrsid15953908 . }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid2494828\charrsid15953908
+\par }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid8214255\charrsid15953908
+\par }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \b\f37\fs20\insrsid5315391\charrsid15953908 7}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \b\f37\fs20\insrsid2182777\charrsid15953908 .2}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid5794662\charrsid15953908 \tab }{
+\rtlch\fcs1 \ab\af37\afs20 \ltrch\fcs0 \b\f37\fs20\insrsid16479123\charrsid15953908 Limitation of Liability and Indemnification}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid16479123\charrsid15953908
+. AMD AND ITS LICENSORS WILL NOT, UNDER ANY CIRCUMSTANCES BE LIABLE TO }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid3610293\charrsid15953908 YOU}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid16479123\charrsid15953908
+ FOR ANY PUNITIVE, DIRECT, INCIDENTAL, INDIRECT, SPECIAL OR CONSEQUENTIAL DAMAGES}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid2769501\charrsid15953908 INCLUDING LOSS OF }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid11431762\charrsid15953908 USE, }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid2769501\charrsid15953908 PROFITS}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid11431762\charrsid15953908 ,}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid2769501\charrsid15953908 }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid11431762\charrsid15953908 OR}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid2769501\charrsid15953908 DATA }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid16479123\charrsid15953908 ARISING FROM USE OF THE }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid8792582\charrsid15953908 SOFTWARE}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid16479123\charrsid15953908
+ OR THIS AGREEMENT EVEN IF AMD AND ITS LICENSORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ In no event shall AMD's total liability for all damages, losses, and causes of action (whether in contract, tort (including negligence) or otherwise) exceed the amount of $100 USD. }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid3610293\charrsid15953908 You}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid16479123\charrsid15953908 agree to defend, indemnify and hold harmless AMD and its licensors,
+and any of their directors, officers, employees, affiliates or agents from and against any and all loss, damage, liability and other expenses (including reasonable attorneys' fees), resulting from }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid3610293\charrsid15953908 You}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid1598747\charrsid15953908 r}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid16479123\charrsid15953908 use}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid2785221\charrsid15953908 , di}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid12522995\charrsid15953908 stribution}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid11431762\charrsid15953908 or sublicense }{\rtlch\fcs1
+\af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid16479123\charrsid15953908 of the }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid8792582\charrsid15953908 Software}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid16479123\charrsid15953908 or vio
+lation of the terms and conditions of this Agreement}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid12522995\charrsid15953908 by }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid3610293\charrsid15953908 You}{\rtlch\fcs1 \af37\afs20
+\ltrch\fcs0 \f37\fs20\insrsid12522995\charrsid15953908 or any sublicense}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid5390130\charrsid15953908 . The parties agree that these limitations are an essential element in setting consideration herein.}
+{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid2182777\charrsid15953908
+\par }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid3243892\charrsid15953908
+\par }\pard \ltrpar\s28\qj \li0\ri0\nowidctlpar\tx720\wrapdefault\faauto\rin0\lin0\itap0\pararsid3243892 {\rtlch\fcs1 \ab\af37\afs20 \ltrch\fcs0 \b\f37\fs20\insrsid5315391\charrsid15953908 8}{\rtlch\fcs1 \ab\af37\afs20 \ltrch\fcs0
+\b\f37\fs20\insrsid3243892\charrsid15953908 .\tab CONFIDENTIALITY.}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\expnd0\expndtw-3\insrsid3243892\charrsid15953908 }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid3610293\charrsid15953908 You}{
+\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid3243892\charrsid15953908 shall protect the }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid8792582\charrsid15953908 Software}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid3243892\charrsid15953908 and any information related thereto (}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid6762244\charrsid15953908 collectively, }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid3243892\charrsid15953908
+\'93Confidential Information\'94) by using the same degree of care, but no less than a reasonable degree of care, to prevent the unauthorized use, dissemination or publication of the Confidential Information as }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid3610293\charrsid15953908 You}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid3243892\charrsid15953908 uses to protect }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid8792582\charrsid15953908 your}{\rtlch\fcs1 \af37\afs20
+\ltrch\fcs0 \f37\fs20\insrsid3243892\charrsid15953908 own confidential information of a like nature. }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid3610293\charrsid15953908 You}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid3243892\charrsid15953908 shall not disclose any Confidential Information disclosed hereunder to any third party and shall limit disclosure of Confidential Information to only those of }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid8792582\charrsid15953908 your}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid3243892\charrsid15953908 employees and contractors with a need to know and who are bound by confidentiality obligations with }{\rtlch\fcs1 \af37\afs20
+\ltrch\fcs0 \f37\fs20\insrsid3610293\charrsid15953908 You}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid3243892\charrsid15953908 at least as restrictive as those contained in this Agreement. }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid3610293\charrsid15953908 You}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid3243892\charrsid15953908 shall be responsible for }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid8792582\charrsid15953908 your}{\rtlch\fcs1
+\af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid3243892\charrsid15953908 employees and contractors adherence to the terms of this Agreement. }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\expnd0\expndtw-3\insrsid3610293\charrsid15953908 You}{\rtlch\fcs1
+\af37\afs20 \ltrch\fcs0 \f37\fs20\expnd0\expndtw-3\insrsid3243892\charrsid15953908 may disclose Confidential Information in accordance with a judicial or other governmental order, provided that }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\expnd0\expndtw-3\insrsid3610293\charrsid15953908 You}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\expnd0\expndtw-3\insrsid3243892\charrsid15953908
+ either (a) gives AMD reasonable notice prior to such disclosure to allow AMD a reasonable opportunity to seek a protective order or equi
+valent or (b) obtains written assurance from the applicable judicial or governmental entity that it will afford the Confidential Information the highest level of protection afforded under applicable law or regulation. }{\rtlch\fcs1 \af37\afs20
+\ltrch\fcs0 \b\f37\fs20\cf0\insrsid3243892\charrsid15953908
+\par }\pard \ltrpar\s28\qj \li0\ri0\widctlpar\wrapdefault\faauto\rin0\lin0\itap0\pararsid2494828 {\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid2494828\charrsid15953908
+\par }\pard \ltrpar\s28\qj \li0\ri0\widctlpar\wrapdefault\faauto\rin0\lin0\itap0\pararsid3243892 {\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \b\f37\fs20\insrsid5315391\charrsid15953908 9}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\b\f37\fs20\insrsid2182777\charrsid15953908 .\tab TERMINATION}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \b\f37\fs20\insrsid7479446\charrsid15953908 AND SURVIVAL}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid2494828\charrsid15953908 .}{\rtlch\fcs1
+\af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid8670315\charrsid15953908 }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid7479446\charrsid15953908 AMD may terminate the Agreement immediately upon the breach by }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid3610293\charrsid15953908 You}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid7479446\charrsid15953908 or any }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid9861369\charrsid15953908 sublicensee }{\rtlch\fcs1 \af37\afs20
+\ltrch\fcs0 \f37\fs20\insrsid7479446\charrsid15953908 of the terms of the Agreement.}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid6762244\charrsid15953908 }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid3610293\charrsid15953908 You}{
+\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid6762244\charrsid15953908 may terminate the Agreement upon thirty (30) days written notice to AMD.}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid7479446\charrsid15953908 }{\rtlch\fcs1
+\af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid2182777\charrsid15953908 The termination of this Agreement shall}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid5925573\charrsid15953908 :}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid2182777\charrsid15953908 }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid5925573\charrsid15953908 (i) }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid2359616\charrsid15953908 immediately result in the termination of all }{
+\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid16088132\charrsid15953908 rights}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid5925573\charrsid15953908 granted by }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid3610293\charrsid15953908 You}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid5925573\charrsid15953908 }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid2359616\charrsid15953908 to }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid16088132\charrsid15953908 distribute the }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid8792582\charrsid15953908 Software}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid16088132\charrsid15953908 through }{\rtlch\fcs1
+\af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid10188447\charrsid15953908 multiple tiers of distribution}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid10188447\delrsid10188447\charrsid15953908 }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid2494828\charrsid15953908 under Section 2}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid5925573\charrsid15953908 ; and (ii) }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid2182777\charrsid15953908
+have no effect on any sublicenses previously granted by }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid3610293\charrsid15953908 You}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid2182777\charrsid15953908 to end users}{\rtlch\fcs1
+\af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid5925573\charrsid15953908 under Subsection}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid2494828\charrsid15953908 s 2,}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid5925573\charrsid15953908 w
+hich sublicenses shall survive in accordance with their terms}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid2182777\charrsid15953908 . }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid7479446\charrsid15953908
+Upon termination or expiration of this Agreement, all provisions survive except for Section 2}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid9861369\charrsid15953908 and}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid10385238\charrsid15953908 }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid9861369\charrsid15953908 y}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid3610293\charrsid15953908 ou}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid10385238\charrsid15953908 will cease using and destroy or return to AMD all copies of the }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid8792582\charrsid15953908 Software}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid10385238\charrsid15953908 .}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \b\f37\fs20\insrsid10385238\charrsid15953908 }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \b\f37\fs20\insrsid3243892\charrsid15953908
+\par }\pard \ltrpar\s28\qj \li0\ri0\widctlpar\wrapdefault\faauto\rin0\lin0\itap0\pararsid539192 {\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid539192\charrsid15953908
+\par }\pard\plain \ltrpar\qj \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0\pararsid539192 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af37 \ltrch\fcs0
+\b\f37\cgrid0\insrsid539192\charrsid15953908 1}{\rtlch\fcs1 \ab\af37 \ltrch\fcs0 \b\f37\cgrid0\insrsid5315391\charrsid15953908 0}{\rtlch\fcs1 \ab\af37 \ltrch\fcs0 \b\f37\cgrid0\insrsid539192\charrsid15953908 .\tab EXPORT RESTRICTIONS}{\rtlch\fcs1
+\ab\af37 \ltrch\fcs0 \f37\cgrid0\insrsid539192\charrsid15953908 . }{\rtlch\fcs1 \ab\af37 \ltrch\fcs0 \b\f37\cgrid0\insrsid539192\charrsid15953908 }{\rtlch\fcs1 \ab\af37 \ltrch\fcs0 \f37\cgrid0\insrsid3610293\charrsid15953908 You}{\rtlch\fcs1 \ab\af37
+\ltrch\fcs0 \f37\cgrid0\insrsid539192\charrsid15953908 shall adhere to all applicable U.S., European, and other export laws, }{\rtlch\fcs1 \af37 \ltrch\fcs0 \f37\insrsid539192\charrsid15953908
+including but not limited to the U.S. Export Administration Regulations (\'93EAR\'94) (15 C.F.R Sections 730-774), and E.U. Council Regulation (EC) No 428/2009 of\~5\~May\~2009. Further, pursuant to Section 740.6 of the EAR, }{\rtlch\fcs1 \af37
+\ltrch\fcs0 \f37\insrsid3610293\charrsid15953908 You}{\rtlch\fcs1 \af37 \ltrch\fcs0 \f37\insrsid539192\charrsid15953908 hereby certif}{\rtlch\fcs1 \af37 \ltrch\fcs0 \f37\insrsid16743814\charrsid15953908 y }{\rtlch\fcs1 \af37 \ltrch\fcs0
+\f37\insrsid539192\charrsid15953908 that, except pursuant to a license granted by the United States Department of Commerce Bureau of Industry and Security or as otherwise permitted pursuant to a License Exception under the EAR, }{\rtlch\fcs1 \af37
+\ltrch\fcs0 \f37\insrsid3610293\charrsid15953908 You}{\rtlch\fcs1 \af37 \ltrch\fcs0 \f37\insrsid539192\charrsid15953908 will not (1) export, re-export or release to a national of a
+ country in Country Groups D:1, E:1 or E:2 any restricted technology, software, or source code it receives from AMD, or (2) export to Country Groups D:1, E:1 or E:2 the direct product of such technology or software, if such foreign produced direct product
+ is subject to national security controls as identified on the Commerce Control List (currently found in Supplement 1 to Part 774 of EAR). For the most current Country Group listings, or for additional information about the EAR or }{\rtlch\fcs1 \af37
+\ltrch\fcs0 \f37\insrsid3610293\charrsid15953908 You}{\rtlch\fcs1 \af37 \ltrch\fcs0 \f37\insrsid10166019\charrsid15953908 r}{\rtlch\fcs1 \af37 \ltrch\fcs0 \f37\insrsid539192\charrsid15953908 obligations under th
+ose regulations, please refer to the U.S. Bureau of Industry and Security\rquote s website at }{\field\fldedit{\*\fldinst {\rtlch\fcs1 \af37 \ltrch\fcs0 \cs25\f37\ul\cf2\insrsid10631540 HYPERLINK "http://www.bis.doc.gov/" }}{\fldrslt {\rtlch\fcs1 \af37
+\ltrch\fcs0 \cs25\f37\ul\cf2\insrsid539192\charrsid15953908 http://www.bis.doc.gov/}}}\sectd \ltrsect\psz1\sbknone\linex0\headery446\titlepg\sectdefaultcl\sectrsid13984695\sftnbj {\rtlch\fcs1 \af37 \ltrch\fcs0 \f37\insrsid539192\charrsid15953908 .
+
+\par
+\par }\pard\plain \ltrpar\s28\qj \li0\ri0\widctlpar\wrapdefault\faauto\rin0\lin0\itap0\pararsid539192 \rtlch\fcs1 \af40\afs24\alang1025 \ltrch\fcs0 \f40\fs24\cf1\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af37\afs20 \ltrch\fcs0
+\b\f37\fs20\insrsid539192\charrsid15953908 1}{\rtlch\fcs1 \ab\af37\afs20 \ltrch\fcs0 \b\f37\fs20\insrsid5315391\charrsid15953908 1}{\rtlch\fcs1 \ab\af37\afs20 \ltrch\fcs0 \b\f37\fs20\insrsid539192\charrsid15953908 .\tab GOVERNMENT END USERS}{\rtlch\fcs1
+\af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid539192\charrsid15953908 . The }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid8792582\charrsid15953908 Software}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid539192\charrsid15953908
+ is provided with \'93RESTRICTED RIGHTS.\'94 Use, duplication or disclosure by the Government is subject to restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or its successor. Use of the }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\f37\fs20\insrsid8792582\charrsid15953908 Software}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid539192\charrsid15953908 by the Government constitutes acknowledgment of AMD\rquote s proprietary rights in it.
+\par }\pard \ltrpar\s28\qj \li0\ri0\widctlpar\wrapdefault\faauto\rin0\lin0\itap0\pararsid3243892 {\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \b\f37\fs20\insrsid10385238\charrsid15953908 }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\b\f37\fs20\insrsid12870146\charrsid15953908
+\par }\pard \ltrpar\s28\qj \li0\ri0\widctlpar\wrapdefault\faauto\rin0\lin0\itap0\pararsid7479446 {\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \b\f37\fs20\expnd0\expndtw-3\insrsid6974857\charrsid15953908 1}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
+\b\f37\fs20\expnd0\expndtw-3\insrsid5315391\charrsid15953908 2}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \b\f37\fs20\expnd0\expndtw-3\insrsid1577702\charrsid15953908 .}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0
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+This Agreement is made under and shall be construed according to the laws of the State of California, excluding conflicts of law rules. Each party submits to the jurisdiction of the state and federal courts of Santa Clara County and the No
+rthern District of California for the purposes of this Agreement. }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid3610293\charrsid15953908 You}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid10166019\charrsid15953908 acknowledge}{
+\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid12799185\charrsid15953908 that }{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid8792582\charrsid15953908 your}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid12799185\charrsid15953908
+ breach of this Agreement may cau}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid8157620\charrsid15953908 se irreparable damage and agree}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid12799185\charrsid15953908
+ that AMD shall be entitled to seek injunctive relief under this Agreement, as well as such further relief as may be granted by a court of competent jurisdiction.}{\rtlch\fcs1 \af37\afs20 \ltrch\fcs0 \f37\fs20\insrsid6902842\charrsid15953908
+\par
+\par }\pard\plain \ltrpar\qj \li0\ri0\nowidctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid6902842 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af37
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+The parties do not intend that any agency or partnership relationship be created between them by this Agreement. Each provision of this Agreement shall be interpreted in such a manner as to be effective and valid under applicable law. However, in the ev
+ent that any provision of this Agreement becomes or is declared unenforceable by any court of competent jurisdiction, such provision shall be deemed deleted and the remainder of this Agreement shall remain in full force and effect.
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+\par }\pard\plain \ltrpar\qj \li0\ri0\nowidctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid6902842 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af37
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+ and supersedes and merges all prior oral and written agreements, discussions and understandings between them regarding the subject matter of
+ this Agreement. No waiver or modification of any provision of this Agreement shall be binding unless made in writing and signed by an authorized representative of each Party.
+\par }{\rtlch\fcs1 \af37 \ltrch\fcs0 \f37\insrsid741925
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+IF YOU DO NOT AGREE TO THE TERMS OF THIS AGREEMENT, DO NOT INSTALL, COPY OR USE THIS SOFTWARE. }{\rtlch\fcs1 \ab\af37 \ltrch\fcs0 \f37\cf1\kerning1\insrsid13984695\charrsid15953908
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\ No newline at end of file diff --git a/meta-r1000/recipes-devtools/rgp/files/RadeonDeveloperServiceCLI b/meta-r1000/recipes-devtools/rgp/files/RadeonDeveloperServiceCLI Binary files differnew file mode 100644 index 00000000..e4e6f2ab --- /dev/null +++ b/meta-r1000/recipes-devtools/rgp/files/RadeonDeveloperServiceCLI diff --git a/meta-r1000/recipes-devtools/rgp/files/rds-cli.service b/meta-r1000/recipes-devtools/rgp/files/rds-cli.service new file mode 100644 index 00000000..c44d1f07 --- /dev/null +++ b/meta-r1000/recipes-devtools/rgp/files/rds-cli.service @@ -0,0 +1,13 @@ +[Unit] +Description="Radeon Developer Service CLI" +Wants=connman-wait-online.service +After=connman-wait-online.service + +[Service] +Type=simple +Restart=always +ExecStartPre=/bin/rm -f /dev/shm/sem.D0939873-BA4B-4C4E-9729-D82DED85BC41 +ExecStart=/usr/bin/RadeonDeveloperServiceCLI + +[Install] +WantedBy=multi-user.target diff --git a/meta-r1000/recipes-devtools/rgp/rgp_1.2.0.bb b/meta-r1000/recipes-devtools/rgp/rgp_1.2.0.bb new file mode 100644 index 00000000..4b9c6469 --- /dev/null +++ b/meta-r1000/recipes-devtools/rgp/rgp_1.2.0.bb @@ -0,0 +1,39 @@ +SUMMARY = "Radeon-GPUProfiler" +DESCRIPTION = "The Radeon GPU Profiler (RGP) is a ground-breaking \ + low-level optimization tool from AMD. It provides \ + detailed timing information on Radeon Graphics \ + using custom, built-in, hardware thread-tracing, \ + allowing the developer deep inspection of GPU workloads. \ + This package merely deploys the remote profiling service \ + on the target so a host can collect and display profiling \ + data." + +LICENSE = "Proprietary" +LIC_FILES_CHKSUM = "file://License.rtf;md5=5441ae9fb95849e3aacd0f330710f9fa" + +inherit systemd + +RDEPENDS_${PN} += "connman-wait-online" + +SRC_URI = "file://License.rtf \ + file://RadeonDeveloperServiceCLI \ + file://${BOOT_SERVICE}" + +S = "${WORKDIR}" +BOOT_SERVICE = "rds-cli.service" +SYSTEMD_SERVICE_${PN} = "${BOOT_SERVICE}" +SYSTEMD_AUTO_ENABLE = "enable" + +# Skip configure and compile +do_configure[noexec] = "1" +do_compile[noexec] = "1" + +do_install () { + # Install the binary for RDS CLI + install -d ${D}${bindir} + install -m 0755 ${S}/RadeonDeveloperServiceCLI ${D}${bindir}/ + + # Install the systemd service so we can kick start on boot + install -d ${D}${systemd_unitdir}/system + install -m 644 ${WORKDIR}/${BOOT_SERVICE} ${D}${systemd_unitdir}/system/ +} diff --git a/meta-r1000/recipes-devtools/spirv/spirv-tools/0002-spirv-lesspipe.sh-allow-using-generic-shells.patch b/meta-r1000/recipes-devtools/spirv/spirv-tools/0002-spirv-lesspipe.sh-allow-using-generic-shells.patch new file mode 100644 index 00000000..40bc477a --- /dev/null +++ b/meta-r1000/recipes-devtools/spirv/spirv-tools/0002-spirv-lesspipe.sh-allow-using-generic-shells.patch @@ -0,0 +1,27 @@ +From f6c173b1c32e6dcbac510a4bcb60e6bb080c146a Mon Sep 17 00:00:00 2001 +From: Awais Belal <awais_belal@mentor.com> +Date: Wed, 31 May 2017 12:26:04 +0500 +Subject: [PATCH 2/2] spirv-lesspipe.sh: allow using generic shells + +The script is harmless for any type of shell and +shouldn't be tied with bash to allow catering +more possibilities. + +Signed-off-by: Awais Belal <awais_belal@mentor.com> +--- + tools/lesspipe/spirv-lesspipe.sh | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/tools/lesspipe/spirv-lesspipe.sh b/tools/lesspipe/spirv-lesspipe.sh +index 81e3355..f955259 100644 +--- a/tools/lesspipe/spirv-lesspipe.sh ++++ b/tools/lesspipe/spirv-lesspipe.sh +@@ -1,4 +1,4 @@ +-#!/bin/bash ++#!/bin/sh + # Copyright (c) 2016 The Khronos Group Inc. + + # Licensed under the Apache License, Version 2.0 (the "License"); +-- +2.11.1 + diff --git a/meta-r1000/recipes-devtools/spirv/spirv-tools_git.bb b/meta-r1000/recipes-devtools/spirv/spirv-tools_git.bb new file mode 100644 index 00000000..a4da04e2 --- /dev/null +++ b/meta-r1000/recipes-devtools/spirv/spirv-tools_git.bb @@ -0,0 +1,28 @@ +SUMMARY = "SPIR-V Tools" +DESCRIPTION = "SPIR-V is a binary intermediate language for representing \ + graphical-shader stages and compute kernels for multiple \ + Khronos APIs, such as OpenCL, OpenGL, and Vulkan." +SECTION = "graphics" +HOMEPAGE = "https://www.khronos.org/registry/spir-v" + +inherit cmake python3native + +LICENSE = "Apache-2.0" +LIC_FILES_CHKSUM = "file://LICENSE;md5=3b83ef96387f14655fc854ddc3c6bd57" + +S = "${WORKDIR}/git" +SPIRV_HEADERS_LOCATION = "${S}/external/spirv-headers" +HEADERS_VERSION = "1.1" + +SRCREV_spirv-tools = "9e19fc0f31ceaf1f6bc907dbf17dcfded85f2ce8" +SRCREV_spirv-headers = "ce309203d7eceaf908bea8862c27f3e0749f7d00" +SRC_URI = "git://github.com/KhronosGroup/SPIRV-Tools;protocol=http;name=spirv-tools \ + git://github.com/KhronosGroup/SPIRV-Headers;name=spirv-headers;destsuffix=${SPIRV_HEADERS_LOCATION} \ + file://0002-spirv-lesspipe.sh-allow-using-generic-shells.patch" + +do_install_append() { + if test -d ${SPIRV_HEADERS_LOCATION}/include/spirv/${HEADERS_VERSION}; then + install -d ${D}/${includedir}/SPIRV + install -m 0644 ${SPIRV_HEADERS_LOCATION}/include/spirv/${HEADERS_VERSION}/* ${D}/${includedir}/SPIRV + fi +} diff --git a/meta-r1000/recipes-graphics/mesa/mesa_git.bbappend b/meta-r1000/recipes-graphics/mesa/mesa_git.bbappend new file mode 100644 index 00000000..5211be22 --- /dev/null +++ b/meta-r1000/recipes-graphics/mesa/mesa_git.bbappend @@ -0,0 +1 @@ +PACKAGECONFIG_append_r1000 = " dri3"
\ No newline at end of file diff --git a/meta-r1000/recipes-graphics/vulkan/vulkan-loader-layers/0001-CMakeLists-add-include-path-so-Xlib.h-is-found-as-ne.patch b/meta-r1000/recipes-graphics/vulkan/vulkan-loader-layers/0001-CMakeLists-add-include-path-so-Xlib.h-is-found-as-ne.patch new file mode 100644 index 00000000..10337189 --- /dev/null +++ b/meta-r1000/recipes-graphics/vulkan/vulkan-loader-layers/0001-CMakeLists-add-include-path-so-Xlib.h-is-found-as-ne.patch @@ -0,0 +1,83 @@ +From 49d4dd326b9d4b7b013f4a1d21498568d76443b2 Mon Sep 17 00:00:00 2001 +From: Awais Belal <awais_belal@mentor.com> +Date: Tue, 4 Sep 2018 14:09:12 +0500 +Subject: [PATCH 1/5] CMakeLists: add include path so Xlib.h is found as needed + +All the targets including vk_platform.h or directly including +X11/Xlib.h require to know the directory for the installed +header. Add the directory to these so the requirements are +filled in properly. + +Signed-off-by: Awais Belal <awais_belal@mentor.com> +--- + CMakeLists.txt | 2 ++ + demos/CMakeLists.txt | 1 + + layers/CMakeLists.txt | 1 + + libs/vkjson/CMakeLists.txt | 1 + + loader/CMakeLists.txt | 1 + + 5 files changed, 6 insertions(+) + +diff --git a/CMakeLists.txt b/CMakeLists.txt +index 5cf85d487..5ce69d216 100644 +--- a/CMakeLists.txt ++++ b/CMakeLists.txt +@@ -225,6 +225,8 @@ find_path(SPIRV_TOOLS_INCLUDE_DIR spirv-tools/libspirv.h HINTS "${EXTERNAL_SOURC + "${CMAKE_SOURCE_DIR}/../glslang/External/spirv-tools/include" + DOC "Path to spirv-tools/libspirv.h") + ++find_path(X11_XLIB_INCLUDE_DIR X11/Xlib.h DOC "Path to X11/Xlib.h") ++ + find_library(GLSLANG_LIB NAMES glslang + HINTS ${GLSLANG_SEARCH_PATH} ) + +diff --git a/demos/CMakeLists.txt b/demos/CMakeLists.txt +index 487b19910..fb5022bf5 100644 +--- a/demos/CMakeLists.txt ++++ b/demos/CMakeLists.txt +@@ -41,6 +41,7 @@ elseif(CMAKE_SYSTEM_NAME STREQUAL "Linux") + set(DEMO_INCLUDE_DIRS + ${X11_INCLUDE_DIR} + ${DEMO_INCLUDE_DIRS} ++ ${X11_XLIB_INCLUDE_DIR} + ) + link_libraries(${X11_LIBRARIES}) + add_definitions(-DVK_USE_PLATFORM_XLIB_KHR) +diff --git a/layers/CMakeLists.txt b/layers/CMakeLists.txt +index 08b0e2090..6068d0031 100644 +--- a/layers/CMakeLists.txt ++++ b/layers/CMakeLists.txt +@@ -146,6 +146,7 @@ include_directories( + ${CMAKE_CURRENT_BINARY_DIR} + ${PROJECT_BINARY_DIR} + ${CMAKE_BINARY_DIR} ++ ${X11_XLIB_INCLUDE_DIR} + ) + + if (WIN32) +diff --git a/libs/vkjson/CMakeLists.txt b/libs/vkjson/CMakeLists.txt +index 2e79d9109..4b1df5988 100644 +--- a/libs/vkjson/CMakeLists.txt ++++ b/libs/vkjson/CMakeLists.txt +@@ -23,6 +23,7 @@ include_directories( + ${CMAKE_CURRENT_SOURCE_DIR} + ${CMAKE_CURRENT_SOURCE_DIR}/../../loader + ${CMAKE_CURRENT_SOURCE_DIR}/../../include/vulkan ++ ${X11_XLIB_INCLUDE_DIR} + ) + + add_library(vkjson STATIC vkjson.cc vkjson_instance.cc ../../loader/cJSON.c) +diff --git a/loader/CMakeLists.txt b/loader/CMakeLists.txt +index 4d1d08fc8..55ae2cb85 100644 +--- a/loader/CMakeLists.txt ++++ b/loader/CMakeLists.txt +@@ -3,6 +3,7 @@ include_directories( + ${CMAKE_CURRENT_BINARY_DIR} + ${PROJECT_BINARY_DIR} + ${CMAKE_BINARY_DIR} ++ ${X11_XLIB_INCLUDE_DIR} + ) + + # Check for the existance of the secure_getenv or __secure_getenv commands +-- +2.11.1 + diff --git a/meta-r1000/recipes-graphics/vulkan/vulkan-loader-layers/0002-demos-CMakeLists.txt-install-demos.patch b/meta-r1000/recipes-graphics/vulkan/vulkan-loader-layers/0002-demos-CMakeLists.txt-install-demos.patch new file mode 100644 index 00000000..1ffc283e --- /dev/null +++ b/meta-r1000/recipes-graphics/vulkan/vulkan-loader-layers/0002-demos-CMakeLists.txt-install-demos.patch @@ -0,0 +1,35 @@ +From 0ee0a0502b96b46190f6e47243b0a008ff04ebbd Mon Sep 17 00:00:00 2001 +From: Awais Belal <awais_belal@mentor.com> +Date: Tue, 4 Sep 2018 14:10:37 +0500 +Subject: [PATCH 2/5] demos/CMakeLists.txt: install demos + +Install demos to the target. + +Signed-off-by: Awais Belal <awais_belal@mentor.com> +--- + demos/CMakeLists.txt | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/demos/CMakeLists.txt b/demos/CMakeLists.txt +index fb5022bf5..5a723805d 100644 +--- a/demos/CMakeLists.txt ++++ b/demos/CMakeLists.txt +@@ -148,6 +148,7 @@ if(NOT WIN32) + if (${CMAKE_SYSTEM_PROCESSOR} STREQUAL ${CMAKE_HOST_SYSTEM_PROCESSOR}) + add_executable(cube cube.c ${PROJECT_SOURCE_DIR}/demos/cube.vert ${PROJECT_SOURCE_DIR}/demos/cube.frag cube.vert.inc cube.frag.inc) + target_link_libraries(cube ${LIBRARIES}) ++ install(TARGETS cube DESTINATION ${CMAKE_INSTALL_BINDIR}) + endif() + else() + if (CMAKE_CL_64) +@@ -164,6 +165,7 @@ if(NOT WIN32) + if (${CMAKE_SYSTEM_PROCESSOR} STREQUAL ${CMAKE_HOST_SYSTEM_PROCESSOR}) + add_executable(cubepp cube.cpp ${PROJECT_SOURCE_DIR}/demos/cube.vert ${PROJECT_SOURCE_DIR}/demos/cube.frag cube.vert.inc cube.frag.inc) + target_link_libraries(cubepp ${LIBRARIES}) ++ install(TARGETS cubepp DESTINATION ${CMAKE_INSTALL_BINDIR}) + endif() + else() + if (CMAKE_CL_64) +-- +2.11.1 + diff --git a/meta-r1000/recipes-graphics/vulkan/vulkan-loader-layers/0003-CMakeLists.txt-use-a-fixed-header-for-spirv_commit.patch b/meta-r1000/recipes-graphics/vulkan/vulkan-loader-layers/0003-CMakeLists.txt-use-a-fixed-header-for-spirv_commit.patch new file mode 100644 index 00000000..c18441f5 --- /dev/null +++ b/meta-r1000/recipes-graphics/vulkan/vulkan-loader-layers/0003-CMakeLists.txt-use-a-fixed-header-for-spirv_commit.patch @@ -0,0 +1,71 @@ +From af1706e021e900f2cfb15e7bc0f9f68cdd1bd04c Mon Sep 17 00:00:00 2001 +From: Awais Belal <awais_belal@mentor.com> +Date: Tue, 4 Sep 2018 14:58:18 +0500 +Subject: [PATCH 3/5] CMakeLists.txt: use a fixed header for spirv_commit + +Signed-off-by: Awais Belal <awais_belal@mentor.com> +--- + CMakeLists.txt | 3 --- + spirv_tools_commit_id.h | 29 +++++++++++++++++++++++++++++ + 2 files changed, 29 insertions(+), 3 deletions(-) + create mode 100644 spirv_tools_commit_id.h + +diff --git a/CMakeLists.txt b/CMakeLists.txt +index 5cf85d487..b0ec3cbaf 100644 +--- a/CMakeLists.txt ++++ b/CMakeLists.txt +@@ -343,7 +343,6 @@ add_custom_target(generate_helper_files DEPENDS + vk_dispatch_table_helper.h + vk_extension_helper.h + vk_typemap_helper.h +- spirv_tools_commit_id.h + ) + set_target_properties(generate_helper_files PROPERTIES FOLDER ${LVL_TARGET_FOLDER}) + +@@ -358,8 +357,6 @@ run_vk_xml_generate(helper_file_generator.py vk_enum_string_helper.h) + run_vk_xml_generate(helper_file_generator.py vk_object_types.h) + run_vk_xml_generate(helper_file_generator.py vk_extension_helper.h) + run_vk_xml_generate(helper_file_generator.py vk_typemap_helper.h) +-run_external_revision_generate(${EXTERNAL_SOURCE_ROOT}/glslang/External/spirv-tools SPIRV_TOOLS_COMMIT_ID spirv_tools_commit_id.h) +- + + + if(NOT WIN32) +diff --git a/include/vulkan/spirv_tools_commit_id.h b/include/vulkan/spirv_tools_commit_id.h +new file mode 100644 +index 000000000..ae588b33f +--- /dev/null ++++ b/include/vulkan/spirv_tools_commit_id.h +@@ -0,0 +1,29 @@ ++// *** THIS FILE IS GENERATED - DO NOT EDIT *** ++// See external_revision_generator.py for modifications ++ ++/*************************************************************************** ++ * ++ * Copyright (c) 2015-2017 The Khronos Group Inc. ++ * Copyright (c) 2015-2017 Valve Corporation ++ * Copyright (c) 2015-2017 LunarG, Inc. ++ * Copyright (c) 2015-2017 Google Inc. ++ * ++ * Licensed under the Apache License, Version 2.0 (the "License"); ++ * you may not use this file except in compliance with the License. ++ * You may obtain a copy of the License at ++ * ++ * http://www.apache.org/licenses/LICENSE-2.0 ++ * ++ * Unless required by applicable law or agreed to in writing, software ++ * distributed under the License is distributed on an "AS IS" BASIS, ++ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ++ * See the License for the specific language governing permissions and ++ * limitations under the License. ++ * ++ * Author: Chris Forbes <chrisforbes@google.com> ++ * Author: Cort Stratton <cort@google.com> ++ * ++ ****************************************************************************/ ++#pragma once ++ ++#define SPIRV_TOOLS_COMMIT_ID "2651ccaec8170b3257642b3c438f50dc4f181fdd" +-- +2.11.1 + diff --git a/meta-r1000/recipes-graphics/vulkan/vulkan-loader-layers/0004-layer_validation_tests-include-math.h.patch b/meta-r1000/recipes-graphics/vulkan/vulkan-loader-layers/0004-layer_validation_tests-include-math.h.patch new file mode 100644 index 00000000..bd9713ea --- /dev/null +++ b/meta-r1000/recipes-graphics/vulkan/vulkan-loader-layers/0004-layer_validation_tests-include-math.h.patch @@ -0,0 +1,28 @@ +From a5beebd78eb232596f2b6b4de1ee417b629ada47 Mon Sep 17 00:00:00 2001 +From: Awais Belal <awais_belal@mentor.com> +Date: Tue, 4 Sep 2018 15:33:12 +0500 +Subject: [PATCH 4/5] layer_validation_tests: include math.h + +Without the inclusion several math functions +fail as expected. + +Signed-off-by: Awais Belal <awais_belal@mentor.com> +--- + tests/layer_validation_tests.cpp | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/tests/layer_validation_tests.cpp b/tests/layer_validation_tests.cpp +index 132578f85..26b0671fa 100644 +--- a/tests/layer_validation_tests.cpp ++++ b/tests/layer_validation_tests.cpp +@@ -45,6 +45,7 @@ + #include "vk_typemap_helper.h" + + #include <limits.h> ++#include <math.h> + + #include <algorithm> + #include <functional> +-- +2.11.1 + diff --git a/meta-r1000/recipes-graphics/vulkan/vulkan-loader-layers/0005-demos-cube-use-absolute-location-for-data-files.patch b/meta-r1000/recipes-graphics/vulkan/vulkan-loader-layers/0005-demos-cube-use-absolute-location-for-data-files.patch new file mode 100644 index 00000000..85c15b89 --- /dev/null +++ b/meta-r1000/recipes-graphics/vulkan/vulkan-loader-layers/0005-demos-cube-use-absolute-location-for-data-files.patch @@ -0,0 +1,70 @@ +From f6c2eeaad968b1ad0ebef7fad79eb5f01305a6e3 Mon Sep 17 00:00:00 2001 +From: Awais Belal <awais_belal@mentor.com> +Date: Wed, 5 Sep 2018 11:43:07 +0500 +Subject: [PATCH 5/5] demos/cube*: use absolute location for data files + +If absolute locations are not used here the demo +looks for texture files in a haphazard way and +can only be launched from the same directory. +This allows running the demo from anywhere and +consolidate any data files that are needed. + +Signed-off-by: Awais Belal <awais_belal@mentor.com> +--- + demos/cube.c | 7 ++++++- + demos/cube.cpp | 7 ++++++- + 2 files changed, 12 insertions(+), 2 deletions(-) + +diff --git a/demos/cube.c b/demos/cube.c +index 29a484260..6b5f0b7af 100644 +--- a/demos/cube.c ++++ b/demos/cube.c +@@ -67,6 +67,8 @@ + #define APP_SHORT_NAME "cube" + #define APP_LONG_NAME "The Vulkan Cube Demo Program" + ++#define VULKAN_DATA_LOC "/usr/share/vulkan-data/" ++ + // Allow a maximum of two outstanding presentation operations. + #define FRAME_LAG 2 + +@@ -1484,7 +1486,10 @@ bool loadTexture(const char *filename, uint8_t *rgba_data, VkSubresourceLayout * + + return true; + #else +- FILE *fPtr = fopen(filename, "rb"); ++ char abs_filename[256]; ++ strcpy(abs_filename, VULKAN_DATA_LOC); ++ strcat(abs_filename, filename); ++ FILE *fPtr = fopen(abs_filename, "rb"); + char header[256], *cPtr, *tmp; + + if (!fPtr) return false; +diff --git a/demos/cube.cpp b/demos/cube.cpp +index fe8cb7c90..3eee7d9c8 100644 +--- a/demos/cube.cpp ++++ b/demos/cube.cpp +@@ -57,6 +57,8 @@ + // Allow a maximum of two outstanding presentation operations. + #define FRAME_LAG 2 + ++#define VULKAN_DATA_LOC "/usr/share/vulkan-data/" ++ + #define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0])) + + #ifdef _WIN32 +@@ -2261,7 +2263,10 @@ void Demo::update_data_buffer() { + } + + bool Demo::loadTexture(const char *filename, uint8_t *rgba_data, vk::SubresourceLayout *layout, int32_t *width, int32_t *height) { +- FILE *fPtr = fopen(filename, "rb"); ++ char abs_filename[256]; ++ strcpy(abs_filename, VULKAN_DATA_LOC); ++ strcat(abs_filename, filename); ++ FILE *fPtr = fopen(abs_filename, "rb"); + if (!fPtr) { + return false; + } +-- +2.11.1 + diff --git a/meta-r1000/recipes-graphics/vulkan/vulkan-loader-layers_1.1.70.bb b/meta-r1000/recipes-graphics/vulkan/vulkan-loader-layers_1.1.70.bb new file mode 100644 index 00000000..1acb3fe2 --- /dev/null +++ b/meta-r1000/recipes-graphics/vulkan/vulkan-loader-layers_1.1.70.bb @@ -0,0 +1,56 @@ +SUMMARY = "Vulkan Ecosystem Components - Loader and Validation Layers" +DESCRIPTION = "Vulkan is a new generation graphics and compute API that \ + provides high-efficiency, cross-platform access to modern \ + GPUs used in a wide variety of devices from PCs and \ + consoles to mobile phones and embedded platforms." +SECTION = "graphics" +HOMEPAGE = "https://www.khronos.org/vulkan" +DEPENDS = "bison-native libx11 libxcb glslang glslang-native spirv-tools \ + libice libxext libsm libxrandr" + +RDEPENDS_${PN} = "${PN}-layer-libs libxcb-sync libxcb-present libxcb-dri3" + +inherit cmake python3native + +REQUIRED_DISTRO_FEATURES = "x11" + +LICENSE = "Apache-2.0" +LIC_FILES_CHKSUM = "file://LICENSE.txt;md5=99c647ca3d4f6a4b9d8628f757aad156" + +S = "${WORKDIR}/git" + +SRCREV = "1fede1a6b8d6103cc9fcacb567747aa2af167849" +SRC_URI = "git://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers;branch=sdk-${PV} \ + file://0001-CMakeLists-add-include-path-so-Xlib.h-is-found-as-ne.patch \ + file://0002-demos-CMakeLists.txt-install-demos.patch \ + file://0003-CMakeLists.txt-use-a-fixed-header-for-spirv_commit.patch \ + file://0004-layer_validation_tests-include-math.h.patch \ + file://0005-demos-cube-use-absolute-location-for-data-files.patch" + +EXTRA_OECMAKE = " \ + -DCUSTOM_GLSLANG_BIN_ROOT=1 \ + -DGLSLANG_BINARY_ROOT=${STAGING_DIR_HOST}/usr \ + -DCUSTOM_SPIRV_TOOLS_BIN_ROOT=1 \ + -DSPIRV_TOOLS_BINARY_ROOT=${STAGING_DIR_HOST}/usr \ + -DBUILD_TESTS=1 \ + -DBUILD_WSI_MIR_SUPPORT=0 \ + -DBUILD_WSI_WAYLAND_SUPPORT=0 \ +" + +PACKAGES =+ "${PN}-layer-libs" +FILES_${PN}-layer-libs = "${libdir}/libVkLayer_*.so" + +FILES_SOLIBSDEV = "" +FILES_${PN} += "${libdir}/libvulkan.so \ + ${datadir}" +INSANE_SKIP_${PN} = "dev-so" + +do_install_append() { + mv ${D}${bindir}/cube ${D}${bindir}/cube-vulkan + mv ${D}${bindir}/cubepp ${D}${bindir}/cubepp-vulkan + + install -D ${B}/demos/lunarg.ppm ${D}${datadir}/vulkan-data/lunarg.ppm + + # drop the spirv_tools_commit_id.h from installation + rm -f ${D}${includedir}/vulkan/spirv_tools_commit_id.h +} diff --git a/meta-r1000/recipes-graphics/xorg-xserver/xserver-xf86-config_0.1.bbappend b/meta-r1000/recipes-graphics/xorg-xserver/xserver-xf86-config_0.1.bbappend new file mode 100644 index 00000000..0772dead --- /dev/null +++ b/meta-r1000/recipes-graphics/xorg-xserver/xserver-xf86-config_0.1.bbappend @@ -0,0 +1,3 @@ +do_install_append_r1000 () { + sed -i -e 's/^\tBusID "PCI:0:1:0"/\t#BusID "PCI:1:0:0"/' ${D}/${sysconfdir}/X11/xorg.conf +} diff --git a/meta-r1000/recipes-kernel/amd-spi/amd-spi_1.0.bb b/meta-r1000/recipes-kernel/amd-spi/amd-spi_1.0.bb new file mode 100644 index 00000000..b23e5ce6 --- /dev/null +++ b/meta-r1000/recipes-kernel/amd-spi/amd-spi_1.0.bb @@ -0,0 +1,16 @@ +DESCRIPTION = "This kernel module provides support for AMD SPI controller driver" +LICENSE = "BSD | GPLv2" +LIC_FILES_CHKSUM = "file://spi_amd.c;endline=29;md5=e9fdf6da58412e619d89ec9e135a1be3" + +inherit module + +SRC_URI = "file://Makefile \ + file://spi_amd.c \ + file://spi_amd.h \ + file://spirom.c \ + file://spirom.h \ + " + +S = "${WORKDIR}" + +# The inherit of module.bbclass will take care of the rest diff --git a/meta-r1000/recipes-kernel/amd-spi/files/Makefile b/meta-r1000/recipes-kernel/amd-spi/files/Makefile new file mode 100644 index 00000000..f778a69a --- /dev/null +++ b/meta-r1000/recipes-kernel/amd-spi/files/Makefile @@ -0,0 +1,14 @@ +obj-m := spi_amd.o spirom.o + +SRC := $(shell pwd) + +all: + $(MAKE) -C $(KERNEL_SRC) M=$(SRC) + +modules_install: + $(MAKE) -C $(KERNEL_SRC) M=$(SRC) modules_install + +clean: + rm -f *.o *~ core .depend .*.cmd *.ko *.mod.c + rm -f Module.markers Module.symvers modules.order + rm -rf .tmp_versions Modules.symvers diff --git a/meta-r1000/recipes-kernel/amd-spi/files/spi_amd.c b/meta-r1000/recipes-kernel/amd-spi/files/spi_amd.c new file mode 100644 index 00000000..998d9ea6 --- /dev/null +++ b/meta-r1000/recipes-kernel/amd-spi/files/spi_amd.c @@ -0,0 +1,479 @@ +/***************************************************************************** +* +* Copyright (c) 2013, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +***************************************************************************/ +#include <linux/init.h> +#include <linux/module.h> +#include <linux/pci.h> +#include <linux/spi/spi.h> +#include <linux/kthread.h> + +#include "spi_amd.h" + +struct amd_platform_data { + u8 chip_select; +}; + +struct amd_spi { + void __iomem *io_remap_addr; + unsigned long io_base_addr; + u32 rom_addr; + struct spi_master *master; + struct amd_platform_data controller_data; + struct task_struct *kthread_spi; + struct list_head msg_queue; + wait_queue_head_t wq; +}; + +static struct pci_device_id amd_spi_pci_device_id[] = { + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LPC_BRIDGE) }, + {} +}; +MODULE_DEVICE_TABLE(pci, amd_spi_pci_device_id); + +static inline u8 amd_spi_readreg8(struct spi_master *master, int idx) +{ + struct amd_spi *amd_spi = spi_master_get_devdata(master); + + return ioread8((u8 *)amd_spi->io_remap_addr + idx); +} + +static inline void amd_spi_writereg8(struct spi_master *master, int idx, + u8 val) +{ + struct amd_spi *amd_spi = spi_master_get_devdata(master); + + iowrite8(val, ((u8 *)amd_spi->io_remap_addr + idx)); +} + +static inline void amd_spi_setclear_reg8(struct spi_master *master, int idx, + u8 set, u8 clear) +{ + u8 tmp = amd_spi_readreg8(master, idx); + tmp = (tmp & ~clear) | set; + amd_spi_writereg8(master, idx, tmp); +} + +static inline u32 amd_spi_readreg32(struct spi_master *master, int idx) +{ + struct amd_spi *amd_spi = spi_master_get_devdata(master); + + return ioread32((u8 *)amd_spi->io_remap_addr + idx); +} + +static inline void amd_spi_writereg32(struct spi_master *master, int idx, + u32 val) +{ + struct amd_spi *amd_spi = spi_master_get_devdata(master); + + iowrite32(val, ((u8 *)amd_spi->io_remap_addr + idx)); +} + +static inline void amd_spi_setclear_reg32(struct spi_master *master, int idx, + u32 set, u32 clear) +{ + u32 tmp = amd_spi_readreg32(master, idx); + tmp = (tmp & ~clear) | set; + amd_spi_writereg32(master, idx, tmp); +} + +static void amd_spi_select_chip(struct spi_master *master) +{ + struct amd_spi *amd_spi = spi_master_get_devdata(master); + u8 chip_select = amd_spi->controller_data.chip_select; + + amd_spi_setclear_reg8(master, AMD_SPI_ALT_CS_REG, chip_select, + AMD_SPI_ALT_CS_MASK); +} + + +static void amd_spi_clear_fifo_ptr(struct spi_master *master) +{ + amd_spi_setclear_reg32(master, AMD_SPI_CTRL0_REG, AMD_SPI_FIFO_CLEAR, + AMD_SPI_FIFO_CLEAR); +} + +static void amd_spi_set_opcode(struct spi_master *master, u8 cmd_opcode) +{ + amd_spi_setclear_reg32(master, AMD_SPI_CTRL0_REG, cmd_opcode, + AMD_SPI_OPCODE_MASK); +} + +static inline void amd_spi_set_rx_count(struct spi_master *master, + u8 rx_count) +{ + amd_spi_setclear_reg8(master, AMD_SPI_RX_COUNT_REG, rx_count, 0xff); +} + +static inline void amd_spi_set_tx_count(struct spi_master *master, + u8 tx_count) +{ + amd_spi_setclear_reg8(master, AMD_SPI_TX_COUNT_REG, tx_count, 0xff); +} + +static void amd_spi_execute_opcode(struct spi_master *master) +{ + struct amd_spi *amd_spi = spi_master_get_devdata(master); + bool spi_busy; + + /* Set ExecuteOpCode bit in the CTRL0 register */ + amd_spi_setclear_reg32(master, AMD_SPI_CTRL0_REG, AMD_SPI_EXEC_CMD, + AMD_SPI_EXEC_CMD); + + /* poll for SPI bus to become idle */ + spi_busy = (ioread32((u8 *)amd_spi->io_remap_addr + + AMD_SPI_CTRL0_REG) & AMD_SPI_BUSY) == AMD_SPI_BUSY; + while (spi_busy) { + set_current_state(TASK_INTERRUPTIBLE); + schedule(); + set_current_state(TASK_RUNNING); + spi_busy = (ioread32((u8 *)amd_spi->io_remap_addr + + AMD_SPI_CTRL0_REG) & AMD_SPI_BUSY) == AMD_SPI_BUSY; + } +} + +/* Helper function */ +#ifdef CONFIG_SPI_DEBUG +static void amd_spi_dump_reg(struct spi_master *master) +{ + struct amd_spi *amd_spi = spi_master_get_devdata(master); + + printk(KERN_DEBUG DRIVER_NAME ": SPI CTRL 0 registers: 0x%.8x\n", + ioread32((u8 *)amd_spi->io_remap_addr + AMD_SPI_CTRL0_REG)); + /* + * We cannot read CTRL1 register, because reading it would + * inadvertently increment the FIFO pointer. + */ + printk(KERN_DEBUG DRIVER_NAME ": SPI ALT CS registers: 0x%.2x\n", + ioread8((u8 *)amd_spi->io_remap_addr + AMD_SPI_ALT_CS_REG)); + printk(KERN_DEBUG DRIVER_NAME ": SPI Tx Byte Count: 0x%.2x\n", + ioread8((u8 *)amd_spi->io_remap_addr + AMD_SPI_TX_COUNT_REG)); + printk(KERN_DEBUG DRIVER_NAME ": SPI Rx Byte Count: 0x%.2x\n", + ioread8((u8 *)amd_spi->io_remap_addr + AMD_SPI_RX_COUNT_REG)); + printk(KERN_DEBUG DRIVER_NAME ": SPI Status registers: 0x%.8x\n", + ioread32((u8 *)amd_spi->io_remap_addr + AMD_SPI_STATUS_REG)); +} +#else +static void amd_spi_dump_reg(struct spi_master *master) {} +#endif + + +static int amd_spi_master_setup(struct spi_device *spi) +{ + struct spi_master *master = spi->master; + struct amd_spi *amd_spi = spi_master_get_devdata(master); + + amd_spi->controller_data.chip_select = spi->chip_select; + + amd_spi_select_chip(master); + + return 0; +} + +static int amd_spi_master_transfer(struct spi_master *master, + struct spi_message *msg) +{ + struct amd_spi *amd_spi = spi_master_get_devdata(master); + + /* + * Add new message to the queue and let the kernel thread know + * about it. + */ + list_add_tail(&msg->queue, &amd_spi->msg_queue); + wake_up_interruptible(&amd_spi->wq); + + return 0; +} +static int amd_spi_thread(void *t) +{ + struct amd_spi *amd_spi = t; + struct spi_master *master = amd_spi->master; + struct spi_transfer *transfer = NULL; + struct spi_message *message = NULL; + int direction = 0,i = 0,saved_index = 0; + int opcode_found = 0,recv_flag = 0,tx_len = 0,rx_len = 0; + u8 cmd_opcode = 0; + long timeout = 0; + u8 *buffer = NULL; + + /* + * What we do here is actually pretty simple. We pick one message + * at a time from the message queue set up by the controller, and + * then process all the spi_transfers of that spi_message in one go. + * We then remove the message from the queue, and complete the + * transaction. This might not be the best approach, but this is how + * we chose to implement this. Note that out SPI controller has FIFO + * size of 70 bytes, but we consider it to contain a maximum of + * 64-bytes of data and 3-bytes of address. + */ + while (1) { + /* + * Let us wait on a wait queue till the message queue is empty. + */ + do { + timeout = wait_event_interruptible_timeout(amd_spi->wq, + !list_empty(&amd_spi->msg_queue),1000); + + /* check stop condition */ + if (kthread_should_stop()) { + set_current_state(TASK_RUNNING); + return 0; + } + } while(timeout == 0); + + /* + * Else, pull the very first message from the queue and process + * all transfers within that message. And process the messages + * in a pure linear fashion. We also remove the spi_message + * from the queue. + */ + message = list_entry(amd_spi->msg_queue.next, + struct spi_message, queue); + list_del_init(&message->queue); + + /* We store the CS# line to be used for this spi_message */ + amd_spi->controller_data.chip_select = + message->spi->chip_select; + + /* Setting all variables to default value. */ + direction = i = 0; + opcode_found = 0; + recv_flag = tx_len = rx_len = 0; + cmd_opcode = 0; + buffer = NULL; + saved_index = 0; + + amd_spi_select_chip(master); + + /* + * This loop extracts spi_transfers from the spi message, + * programs the command into command register. Pointer variable + * *buffer* points to either tx_buf or rx_buf of spi_transfer + * depending on direction of transfer. Also programs FIFO of + * controller if data has to be transmitted. + */ + list_for_each_entry(transfer, &message->transfers, + transfer_list) + { + if(transfer->rx_buf != NULL) + direction = RECEIVE; + else if(transfer->tx_buf != NULL) + direction = TRANSMIT; + + switch (direction) { + case TRANSMIT: + buffer = (u8 *)transfer->tx_buf; + + if(opcode_found != 1) { + /* Store no. of bytes to be sent into + * FIFO */ + tx_len = transfer->len - 1; + /* Store opcode */ + cmd_opcode = *(u8 *)transfer->tx_buf; + /* Pointing to start of TX data */ + buffer++; + /* Program the command register*/ + amd_spi_set_opcode(master, cmd_opcode); + opcode_found = 1; + } else { + /* Store no. of bytes to be sent into + * FIFO */ + tx_len = transfer->len; + } + + /* Write data into the FIFO. */ + for (i = 0; i < tx_len; i++) { + iowrite8(buffer[i], + ((u8 *)amd_spi->io_remap_addr + + AMD_SPI_FIFO_BASE + + i + saved_index)); + } + + /* Set no. of bytes to be transmitted */ + amd_spi_set_tx_count(master, + tx_len + saved_index); + + /* + * Saving the index, from where next + * spi_transfer's data will be stored in FIFO. + */ + saved_index = i; + break; + case RECEIVE: + /* Store no. of bytes to be received from + * FIFO */ + rx_len = transfer->len; + buffer = (u8 *)transfer->rx_buf; + recv_flag=1; + break; + } + } + + /* Set the RX count to the number of bytes to expect in + * response */ + amd_spi_set_rx_count(master, rx_len ); + amd_spi_clear_fifo_ptr(master); + amd_spi_dump_reg(master); + /* Executing command */ + amd_spi_execute_opcode(master); + amd_spi_dump_reg(master); + + if(recv_flag == 1) { + /* Read data from FIFO to receive buffer */ + for (i = 0; i < rx_len; i++) { + buffer[i] = ioread8((u8 *)amd_spi->io_remap_addr + + AMD_SPI_FIFO_BASE + + tx_len + i); + } + + recv_flag = 0; + } + + /* Update statistics */ + message->actual_length = tx_len + rx_len + 1 ; + /* complete the transaction */ + message->status = 0; + spi_finalize_current_message(master); + } + + return 0; +} + +static int amd_spi_pci_probe(struct pci_dev *pdev, + const struct pci_device_id *id) +{ + struct device *dev = &pdev->dev; + struct spi_master *master; + struct amd_spi *amd_spi; + u32 io_base_addr; + int err = 0; + + /* Allocate storage for spi_master and driver private data */ + master = spi_alloc_master(dev, sizeof(struct amd_spi)); + if (master == NULL) { + dev_err(dev, "Error allocating SPI master\n"); + return -ENOMEM; + } + + amd_spi = spi_master_get_devdata(master); + amd_spi->master = master; + + /* + * Lets first get the base address of SPI registers. The SPI Base + * Address is stored at offset 0xA0 into the LPC PCI configuration + * space. As per the specification, it is stored at bits 6:31 of the + * register. The address is aligned at 64-byte boundary, + * so we should just mask the lower 6 bits and get the address. + */ + pci_read_config_dword(pdev, AMD_PCI_LPC_SPI_BASE_ADDR_REG, + &io_base_addr); + amd_spi->io_base_addr = io_base_addr & AMD_SPI_BASE_ADDR_MASK; + amd_spi->io_remap_addr = ioremap_nocache(amd_spi->io_base_addr, + AMD_SPI_MEM_SIZE); + if (amd_spi->io_remap_addr == NULL) { + dev_err(dev, "ioremap of SPI registers failed\n"); + err = -ENOMEM; + goto err_free_master; + } + dev_dbg(dev, "io_base_addr: 0x%.8lx, io_remap_address: %p\n", + amd_spi->io_base_addr, amd_spi->io_remap_addr); + INIT_LIST_HEAD(&amd_spi->msg_queue); + init_waitqueue_head(&amd_spi->wq); + amd_spi->kthread_spi = kthread_run(amd_spi_thread, amd_spi, + "amd_spi_thread"); + + /* Now lets initialize the fields of spi_master */ + master->bus_num = 0; /* + * This should be the same as passed in + * spi_board_info structure + */ + master->num_chipselect = 4; /* Can be overwritten later during setup */ + master->mode_bits = 0; + master->flags = 0; + master->setup = amd_spi_master_setup; + master->transfer_one_message = amd_spi_master_transfer; + /* Register the controller with SPI framework */ + err = spi_register_master(master); + if (err) { + dev_err(dev, "error registering SPI controller\n"); + goto err_iounmap; + } + pci_set_drvdata(pdev, amd_spi); + + return 0; + +err_iounmap: + iounmap(amd_spi->io_remap_addr); +err_free_master: + spi_master_put(master); + + return 0; +} + +static void amd_spi_pci_remove(struct pci_dev *pdev) +{ + struct amd_spi *amd_spi = pci_get_drvdata(pdev); + + kthread_stop(amd_spi->kthread_spi); + iounmap(amd_spi->io_remap_addr); + spi_unregister_master(amd_spi->master); + spi_master_put(amd_spi->master); + pci_set_drvdata(pdev, NULL); +} + +static struct pci_driver amd_spi_pci_driver = { + .name = "amd_spi", + .id_table = amd_spi_pci_device_id, + .probe = amd_spi_pci_probe, + .remove = amd_spi_pci_remove, +}; + +static int __init amd_spi_init(void) +{ + int ret; + + pr_info("AMD SPI Driver v%s\n", SPI_VERSION); + + ret = pci_register_driver(&amd_spi_pci_driver); + if (ret) + return ret; + + return 0; +} +module_init(amd_spi_init); + +static void __exit amd_spi_exit(void) +{ + pci_unregister_driver(&amd_spi_pci_driver); +} +module_exit(amd_spi_exit); + +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_AUTHOR("Arindam Nath <arindam.nath@amd.com>"); +MODULE_AUTHOR("Sanjay Mehta <sanju.mehta@amd.com>"); +MODULE_DESCRIPTION("AMD SPI Master Controller Driver"); diff --git a/meta-r1000/recipes-kernel/amd-spi/files/spi_amd.h b/meta-r1000/recipes-kernel/amd-spi/files/spi_amd.h new file mode 100644 index 00000000..ec58b9a8 --- /dev/null +++ b/meta-r1000/recipes-kernel/amd-spi/files/spi_amd.h @@ -0,0 +1,28 @@ +#ifndef SPI_AMD_H +#define SPI_AMD_H + +#define DRIVER_NAME "spi_amd" +#define SPI_VERSION "1.0" + +#define AMD_SPI_CTRL0_REG 0x00 + #define AMD_SPI_EXEC_CMD (0x1 << 16) + #define AMD_SPI_OPCODE_MASK 0xFF + #define AMD_SPI_FIFO_CLEAR (0x1 << 20) + #define AMD_SPI_BUSY (0x1 << 31) +#define AMD_SPI_ALT_CS_REG 0x1D + #define AMD_SPI_ALT_CS_MASK 0x3 +#define AMD_SPI_FIFO_BASE 0x80 +#define AMD_SPI_TX_COUNT_REG 0x48 +#define AMD_SPI_RX_COUNT_REG 0x4B +#define AMD_SPI_STATUS_REG 0x4C + +#define AMD_PCI_LPC_SPI_BASE_ADDR_REG 0xA0 +#define AMD_SPI_BASE_ADDR_MASK ~0x3F +#define AMD_SPI_MEM_SIZE 200 + +#define PCI_DEVICE_ID_AMD_LPC_BRIDGE 0x790E + +#define TRANSMIT 1 +#define RECEIVE 2 + +#endif /* SPI_AMD_H */ diff --git a/meta-r1000/recipes-kernel/amd-spi/files/spirom.c b/meta-r1000/recipes-kernel/amd-spi/files/spirom.c new file mode 100644 index 00000000..cb5970ba --- /dev/null +++ b/meta-r1000/recipes-kernel/amd-spi/files/spirom.c @@ -0,0 +1,519 @@ +/***************************************************************************** +* +* spirom.c - SPI ROM client driver +* +* Copyright (c) 2014, Advanced Micro Devices, Inc. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +* +***************************************************************************/ +#include <linux/init.h> +#include <linux/module.h> +#include <linux/ioctl.h> +#include <linux/fs.h> +#include <linux/device.h> +#include <linux/err.h> +#include <linux/list.h> +#include <linux/errno.h> +#include <linux/mutex.h> +#include <linux/slab.h> +#include <linux/spi/spi.h> +#include <linux/pci.h> +#include <linux/delay.h> + +#include <linux/uaccess.h> + +#include "spirom.h" + +#define SPIROM_VERSION "0.2" + +/* + * SPI has a character major number assigned. We allocate minor numbers + * dynamically using a bitmask. You must use hotplug tools, such as udev + * (or mdev with busybox) to create and destroy the /dev/spiromB.C device + * nodes, since there is no fixed association of minor numbers with any + * particular SPI bus or device. + */ +#define SPIROM_MAJOR 153 /* assigned */ +#define N_SPI_MINORS 32 /* ... up to 256 */ + +#define SPI_BUS 0 +#define SPI_BUS_CS1 0 + +static unsigned long minors[N_SPI_MINORS / BITS_PER_LONG]; + + +struct spirom_data { + dev_t devt; + spinlock_t spi_lock; + struct spi_device *spi; + struct list_head device_entry; + struct completion done; + + struct mutex buf_lock; + unsigned users; +}; + +static LIST_HEAD(device_list); +static DEFINE_MUTEX(device_list_lock); + +/*-------------------------------------------------------------------------*/ + +/* + * We can't use the standard synchronous wrappers for file I/O; we + * need to protect against async removal of the underlying spi_device. + */ +static void spirom_complete(void *arg) +{ + complete(arg); +} + +static ssize_t +spirom_sync(struct spirom_data *spirom, struct spi_message *message) +{ + int status; + + message->complete = spirom_complete; + message->context = &spirom->done; + + spin_lock_irq(&spirom->spi_lock); + if (spirom->spi == NULL) + status = -ESHUTDOWN; + else + status = spi_async(spirom->spi, message); + spin_unlock_irq(&spirom->spi_lock); + + if (status == 0) { + /* + * There might be cases where the controller driver has been + * unloaded in the middle of a transaction. So we might end up + * in a situation where we will be waiting for an event which + * will never happen. So we provide a timeout of 1 second for + * situations like this. + */ + wait_for_completion_timeout(&spirom->done, HZ); + status = message->status; + if (status == 0) + status = message->actual_length; + } + return status; +} + +static int spirom_message(struct spirom_data *spirom, + struct spi_ioc_transfer *u_trans, unsigned long arg) +{ + struct spi_message msg; + struct spi_transfer *transfer; + u8 *buffer; + int status = u_trans->len; + + buffer = u_trans->buf; + spi_message_init(&msg); + + /* The very first spi_transfer will contain the command only */ + transfer = kzalloc(sizeof(struct spi_transfer), GFP_KERNEL); + if (!transfer) + return -ENOMEM; + + transfer->tx_buf = buffer; + transfer->len = 1; + buffer += transfer->len; + spi_message_add_tail(transfer, &msg); + + /* + * If the command expects an address as its argument, we populate + * it in the very next spi_transfer. + */ + if (u_trans->addr_present) { + transfer = kzalloc(sizeof(struct spi_transfer), GFP_KERNEL); + if (!transfer) + return -ENOMEM; + + transfer->tx_buf = buffer; + transfer->len = 3; // 3-byte address + buffer += transfer->len; + spi_message_add_tail(transfer, &msg); + } + + /* + * Next is data, which can have a maximum of 64-bytes, the size limited + * by the number of bytes that can stored in the controller FIFO. + */ + if (u_trans->len) { + transfer = kzalloc(sizeof(struct spi_transfer), GFP_KERNEL); + if (!transfer) + return -ENOMEM; + + if (u_trans->direction == TRANSMIT) + transfer->tx_buf = buffer; + else if (u_trans->direction == RECEIVE) + transfer->rx_buf = buffer; + + transfer->len = u_trans->len; + /* No need to increment buffer pointer */ + spi_message_add_tail(transfer, &msg); + } + + status = spirom_sync(spirom, &msg); + + if (u_trans->direction == RECEIVE) { + /* + * The received data should have been populated in + * u_trans->buf, so we just need to copy it into the + * user-space buffer. + */ + buffer = u_trans->buf; + if (u_trans->addr_present) { + buffer += 4; // 1-byte command and 3-byte address + if(__copy_to_user((u8 __user *) + (((struct spi_ioc_transfer *)arg)->buf) + 4, + buffer, u_trans->len)) { + status = -EFAULT; + } + } else { + buffer += 1; // 1-byte command only + if(__copy_to_user((u8 __user *) + (((struct spi_ioc_transfer *)arg)->buf) + 1, + buffer, u_trans->len)) { + status = -EFAULT; + } + } + } + + /* Done with everything, free the memory taken by spi_transfer */ + while (msg.transfers.next != &msg.transfers) { + transfer = list_entry(msg.transfers.next, struct spi_transfer, + transfer_list); + msg.transfers.next = transfer->transfer_list.next; + transfer->transfer_list.next->prev = &msg.transfers; + kfree(transfer); + } + + return status; +} + +static long +spirom_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) +{ + int err = 0; + int retval = 0; + struct spirom_data *spirom; + struct spi_device *spi; + u32 tmp; + struct spi_ioc_transfer *ioc; + + /* Check type and command number */ + if (_IOC_TYPE(cmd) != SPI_IOC_MAGIC) + return -ENOTTY; + + /* Check access direction once here; don't repeat below. + * IOC_DIR is from the user perspective, while access_ok is + * from the kernel perspective; so they look reversed. + */ + if (_IOC_DIR(cmd) & _IOC_READ) + err = !access_ok(VERIFY_WRITE, + (void __user *)arg, _IOC_SIZE(cmd)); + if (err == 0 && _IOC_DIR(cmd) & _IOC_WRITE) + err = !access_ok(VERIFY_READ, + (void __user *)arg, _IOC_SIZE(cmd)); + if (err) + return -EFAULT; + + /* guard against device removal before, or while, + * we issue this ioctl. + */ + spirom = filp->private_data; + spin_lock_irq(&spirom->spi_lock); + spi = spi_dev_get(spirom->spi); + spin_unlock_irq(&spirom->spi_lock); + + if (spi == NULL) + return -ESHUTDOWN; + + /* use the buffer lock here for triple duty: + * - prevent I/O (from us) so calling spi_setup() is safe; + * - prevent concurrent SPI_IOC_WR_* from morphing + * data fields while SPI_IOC_RD_* reads them; + * - SPI_IOC_MESSAGE needs the buffer locked "normally". + */ + mutex_lock(&spirom->buf_lock); + + /* segmented and/or full-duplex I/O request */ + if (_IOC_NR(cmd) != _IOC_NR(SPI_IOC_MESSAGE(0)) || + _IOC_DIR(cmd) !=_IOC_WRITE) { + retval = -ENOTTY; + goto out; + } + + tmp = sizeof(struct spi_ioc_transfer); + + /* copy into scratch area */ + ioc = kzalloc(tmp, GFP_KERNEL); + if (!ioc) { + retval = -ENOMEM; + goto out; + } + if (__copy_from_user(ioc, (struct spi_ioc_transfer __user *)arg, + tmp)) { + kfree(ioc); + retval = -EFAULT; + goto out; + } + + /* translate to spi_message, execute */ + retval = spirom_message(spirom, ioc, arg); + kfree(ioc); + +out: + mutex_unlock(&spirom->buf_lock); + spi_dev_put(spi); + return retval; +} + +static int spirom_open(struct inode *inode, struct file *filp) +{ + struct spirom_data *spirom; + int status = -ENXIO; + + mutex_lock(&device_list_lock); + + list_for_each_entry(spirom, &device_list, device_entry) { + if (spirom->devt == inode->i_rdev) { + status = 0; + break; + } + } + if (status == 0) { + if (status == 0) { + spirom->users++; + filp->private_data = spirom; + nonseekable_open(inode, filp); + } + } else + pr_debug("spirom: nothing for minor %d\n", iminor(inode)); + + mutex_unlock(&device_list_lock); + return status; +} + +static int spirom_release(struct inode *inode, struct file *filp) +{ + struct spirom_data *spirom; + int status = 0; + + mutex_lock(&device_list_lock); + spirom = filp->private_data; + filp->private_data = NULL; + + /* last close? */ + spirom->users--; + if (!spirom->users) { + int dofree; + + /* ... after we unbound from the underlying device? */ + spin_lock_irq(&spirom->spi_lock); + dofree = (spirom->spi == NULL); + spin_unlock_irq(&spirom->spi_lock); + + if (dofree) + kfree(spirom); + } + mutex_unlock(&device_list_lock); + + return status; +} + +static const struct file_operations spirom_fops = { + .owner = THIS_MODULE, + .unlocked_ioctl = spirom_ioctl, + .open = spirom_open, + .release = spirom_release, +}; + +static int __init add_spi_device_to_bus(void) +{ + struct spi_master *spi_master; + struct spi_device *spi_device; + struct spi_board_info spi_info; + + spi_master = spi_busnum_to_master(SPI_BUS); + if (!spi_master) { + printk(KERN_ALERT "Please make sure to \'modprobe " + "spi_amd\' driver first\n"); + return -1; + } + memset(&spi_info, 0, sizeof(struct spi_board_info)); + + strlcpy(spi_info.modalias, "spirom", SPI_NAME_SIZE); + spi_info.bus_num = SPI_BUS; //Bus number of SPI master + spi_info.chip_select = SPI_BUS_CS1; //CS on which SPI device is connected + + spi_device = spi_new_device(spi_master, &spi_info); + if (!spi_device) + return -ENODEV; + + return 0; +} + +/*-------------------------------------------------------------------------*/ + +/* The main reason to have this class is to make mdev/udev create the + * /dev/spiromB.C character device nodes exposing our userspace API. + * It also simplifies memory management. + */ + +static struct class *spirom_class; + +/*-------------------------------------------------------------------------*/ + +static int spirom_probe(struct spi_device *spi) +{ + struct spirom_data *spirom; + int status; + unsigned long minor; + + /* Allocate driver data */ + spirom = kzalloc(sizeof(*spirom), GFP_KERNEL); + if (!spirom) + return -ENOMEM; + + /* Initialize the driver data */ + spirom->spi = spi; + spin_lock_init(&spirom->spi_lock); + mutex_init(&spirom->buf_lock); + + INIT_LIST_HEAD(&spirom->device_entry); + init_completion(&spirom->done); + + /* If we can allocate a minor number, hook up this device. + * Reusing minors is fine so long as udev or mdev is working. + */ + mutex_lock(&device_list_lock); + minor = find_first_zero_bit(minors, N_SPI_MINORS); + if (minor < N_SPI_MINORS) { + struct device *dev; + + spirom->devt = MKDEV(SPIROM_MAJOR, minor); + dev = device_create(spirom_class, &spi->dev, spirom->devt, + spirom, "spirom%d.%d", + spi->master->bus_num, spi->chip_select); + status = IS_ERR(dev) ? PTR_ERR(dev) : 0; + } else { + dev_dbg(&spi->dev, "no minor number available!\n"); + status = -ENODEV; + } + if (status == 0) { + set_bit(minor, minors); + list_add(&spirom->device_entry, &device_list); + } + mutex_unlock(&device_list_lock); + + if (status == 0) + spi_set_drvdata(spi, spirom); + else + kfree(spirom); + + return status; +} + +static int spirom_remove(struct spi_device *spi) +{ + struct spirom_data *spirom = spi_get_drvdata(spi); + + /* make sure ops on existing fds can abort cleanly */ + spin_lock_irq(&spirom->spi_lock); + spirom->spi = NULL; + spi_set_drvdata(spi, NULL); + spin_unlock_irq(&spirom->spi_lock); + + /* prevent new opens */ + mutex_lock(&device_list_lock); + list_del(&spirom->device_entry); + clear_bit(MINOR(spirom->devt), minors); + device_destroy(spirom_class, spirom->devt); + if (spirom->users == 0) + kfree(spirom); + mutex_unlock(&device_list_lock); + + return 0; +} + +static struct spi_driver spirom_spi = { + .driver = { + .name = "spirom", + .owner = THIS_MODULE, + }, + .probe = spirom_probe, + .remove = spirom_remove, + + /* NOTE: suspend/resume methods are not necessary here. + * We don't do anything except pass the requests to/from + * the underlying controller. The refrigerator handles + * most issues; the controller driver handles the rest. + */ +}; + +/*-------------------------------------------------------------------------*/ + +static int __init spirom_init(void) +{ + int status; + + pr_info("AMD SPIROM Driver v%s\n", SPIROM_VERSION); + + /* Claim our 256 reserved device numbers. Then register a class + * that will key udev/mdev to add/remove /dev nodes. Last, register + * the driver which manages those device numbers. + */ + BUILD_BUG_ON(N_SPI_MINORS > 256); + status = register_chrdev(SPIROM_MAJOR, "spi", &spirom_fops); + if (status < 0) + return status; + + spirom_class = class_create(THIS_MODULE, "spirom"); + if (IS_ERR(spirom_class)) { + unregister_chrdev(SPIROM_MAJOR, spirom_spi.driver.name); + return PTR_ERR(spirom_class); + } + + status = spi_register_driver(&spirom_spi); + if (status < 0) { + class_destroy(spirom_class); + unregister_chrdev(SPIROM_MAJOR, spirom_spi.driver.name); + } + + status = add_spi_device_to_bus(); + if (status < 0) { + spi_unregister_driver(&spirom_spi); + class_destroy(spirom_class); + unregister_chrdev(SPIROM_MAJOR, spirom_spi.driver.name); + } + + return status; +} +module_init(spirom_init); + +static void __exit spirom_exit(void) +{ + spi_unregister_driver(&spirom_spi); + class_destroy(spirom_class); + unregister_chrdev(SPIROM_MAJOR, spirom_spi.driver.name); +} +module_exit(spirom_exit); + +MODULE_AUTHOR("Arindam Nath <arindam.nath@amd.com>"); +MODULE_DESCRIPTION("User mode SPI ROM interface"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("spi:spirom"); diff --git a/meta-r1000/recipes-kernel/amd-spi/files/spirom.h b/meta-r1000/recipes-kernel/amd-spi/files/spirom.h new file mode 100644 index 00000000..941b357a --- /dev/null +++ b/meta-r1000/recipes-kernel/amd-spi/files/spirom.h @@ -0,0 +1,53 @@ +#ifndef SPIROM_H +#define SPIROM_H + +#include <linux/types.h> + +/*---------------------------------------------------------------------------*/ + +/* IOCTL commands */ + +#define SPI_IOC_MAGIC 'k' + +#define TRANSMIT 1 +#define RECEIVE 2 + +/* + * struct spi_ioc_transfer - interface structure between application and ioctl + * + * @buf: Buffer to hold 1-byte command, 3-bytes address, and 64-byte data for + * transmit or receive. The internal FIFO of our controller can hold a + * maximum of 70 bytes, including the address. But here we assume the + * maximum data excluding address to be 64-bytes long. + * + * @direction: Direction of data transfer, either TRANSMIT or RECEIVE. + * + * @len: Length of data excluding command and address. + * + * @addr_present: Flag to indicate whether 'buf' above contains an address. + */ +struct spi_ioc_transfer { + __u8 buf[64 + 1 + 3]; + __u8 direction; + __u8 len; + __u8 addr_present; +}; + +/* not all platforms use <asm-generic/ioctl.h> or _IOC_TYPECHECK() ... */ +#define SPI_MSGSIZE(N) \ + ((((N)*(sizeof (struct spi_ioc_transfer))) < (1 << _IOC_SIZEBITS)) \ + ? ((N)*(sizeof (struct spi_ioc_transfer))) : 0) +#define SPI_IOC_MESSAGE(N) _IOW(SPI_IOC_MAGIC, 0, char[SPI_MSGSIZE(N)]) + +/* SPI ROM command codes */ +#define ROM_WREN 0x06 +#define ROM_WRDI 0x04 +#define ROM_RDSR 0x05 +#define ROM_RDID 0x9F +#define ROM_CHIP_ERASE 0x60 +#define ROM_SECTOR_ERASE 0x20 +#define ROM_BLOCK_ERASE 0xD8 +#define ROM_READ 0x03 +#define ROM_WRITE 0x02 + +#endif /* SPIROM_H */ diff --git a/meta-r1000/recipes-kernel/amd-wdt/amd-wdt_1.0.bb b/meta-r1000/recipes-kernel/amd-wdt/amd-wdt_1.0.bb new file mode 100644 index 00000000..edaecf5a --- /dev/null +++ b/meta-r1000/recipes-kernel/amd-wdt/amd-wdt_1.0.bb @@ -0,0 +1,14 @@ +DESCRIPTION = "This kernel module provides support for AMD Watchdog driver" +LICENSE = "BSD | GPLv2" +LIC_FILES_CHKSUM = "file://amd_wdt.c;endline=29;md5=8e7a9706367d146e5073510a6e176dc2" + +inherit module + +SRC_URI = "file://Makefile \ + file://amd_wdt.c \ + file://amd_wdt.h \ + " + +S = "${WORKDIR}" + +# The inherit of module.bbclass will take care of the rest diff --git a/meta-r1000/recipes-kernel/amd-wdt/files/Makefile b/meta-r1000/recipes-kernel/amd-wdt/files/Makefile new file mode 100644 index 00000000..36b32f87 --- /dev/null +++ b/meta-r1000/recipes-kernel/amd-wdt/files/Makefile @@ -0,0 +1,14 @@ +obj-m := amd_wdt.o + +SRC := $(shell pwd) + +all: + $(MAKE) -C $(KERNEL_SRC) M=$(SRC) + +modules_install: + $(MAKE) -C $(KERNEL_SRC) M=$(SRC) modules_install + +clean: + rm -f *.o *~ core .depend .*.cmd *.ko *.mod.c + rm -f Module.markers Module.symvers modules.order + rm -rf .tmp_versions Modules.symvers diff --git a/meta-r1000/recipes-kernel/amd-wdt/files/amd_wdt.c b/meta-r1000/recipes-kernel/amd-wdt/files/amd_wdt.c new file mode 100755 index 00000000..94c3f576 --- /dev/null +++ b/meta-r1000/recipes-kernel/amd-wdt/files/amd_wdt.c @@ -0,0 +1,423 @@ +/***************************************************************************** +* +* Copyright (c) 2014, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +***************************************************************************/ +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/types.h> +#include <linux/watchdog.h> +#include <linux/init.h> +#include <linux/pci.h> +#include <linux/ioport.h> +#include <linux/platform_device.h> +#include <linux/io.h> + +#include "amd_wdt.h" + +/* internal variables */ +static u32 wdtbase_phys; +static void __iomem *wdtbase; +static DEFINE_SPINLOCK(wdt_lock); +static struct pci_dev *amd_wdt_pci; + +/* watchdog platform device */ +static struct platform_device *amd_wdt_platform_device; + +/* module parameters */ +static int heartbeat = AMD_WDT_DEFAULT_TIMEOUT; +module_param(heartbeat, int, 0); +MODULE_PARM_DESC(heartbeat, "Watchdog timeout in frequency units. " + "(default=" __MODULE_STRING(WATCHDOG_HEARTBEAT) ")"); + +static char frequency[MAX_LENGTH] = "1s"; +module_param_string(frequency, frequency, MAX_LENGTH, 0); +MODULE_PARM_DESC(frequency, "Watchdog timer frequency units (32us, " + "10ms, 100ms, 1s). (default=1s)"); + +static bool nowayout = WATCHDOG_NOWAYOUT; +module_param(nowayout, bool, 0); +MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started" + " (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); + +static char action[MAX_LENGTH] = "reboot"; +module_param_string(action, action, MAX_LENGTH, 0); +MODULE_PARM_DESC(action, "Watchdog action (reboot/shutdown). (default=reboot) "); + +/* + * Watchdog specific functions + */ +static int amd_wdt_set_timeout(struct watchdog_device *wdt_dev, unsigned int t) +{ + unsigned long flags; + + /* + * In ideal cases the limits will be checked by Watchdog core itself, + * but there might be cases when we call this function directly from + * somewhere else. So check the limits here. + */ + if (t < AMD_WDT_MIN_TIMEOUT) + heartbeat = t = AMD_WDT_MIN_TIMEOUT; + else if (t > AMD_WDT_MAX_TIMEOUT) + heartbeat = t = AMD_WDT_MAX_TIMEOUT; + + /* Write new timeout value to watchdog */ + spin_lock_irqsave(&wdt_lock, flags); + writel(t, AMD_WDT_COUNT(wdtbase)); + spin_unlock_irqrestore(&wdt_lock, flags); + + wdt_dev->timeout = t; + + return 0; +} + +static int amd_wdt_ping(struct watchdog_device *wdt_dev) +{ + u32 val; + unsigned long flags; + + /* Trigger watchdog */ + spin_lock_irqsave(&wdt_lock, flags); + + val = readl(AMD_WDT_CONTROL(wdtbase)); + val |= AMD_WDT_TRIGGER_BIT; + writel(val, AMD_WDT_CONTROL(wdtbase)); + + spin_unlock_irqrestore(&wdt_lock, flags); + + return 0; +} + +static int amd_wdt_start(struct watchdog_device *wdt_dev) +{ + u32 val; + unsigned long flags; + + /* Enable the watchdog timer */ + spin_lock_irqsave(&wdt_lock, flags); + + val = readl(AMD_WDT_CONTROL(wdtbase)); + val |= AMD_WDT_START_STOP_BIT; + writel(val, AMD_WDT_CONTROL(wdtbase)); + + spin_unlock_irqrestore(&wdt_lock, flags); + + /* Trigger the watchdog timer */ + amd_wdt_ping(wdt_dev); + + return 0; +} + +static int amd_wdt_stop(struct watchdog_device *wdt_dev) +{ + u32 val; + unsigned long flags; + + /* Disable the watchdog timer */ + spin_lock_irqsave(&wdt_lock, flags); + + val = readl(AMD_WDT_CONTROL(wdtbase)); + val &= ~AMD_WDT_START_STOP_BIT; + writel(val, AMD_WDT_CONTROL(wdtbase)); + + spin_unlock_irqrestore(&wdt_lock, flags); + + return 0; +} + +static unsigned int amd_wdt_get_timeleft(struct watchdog_device *wdt_dev) +{ + u32 val; + unsigned long flags; + + spin_lock_irqsave(&wdt_lock, flags); + val = readl(AMD_WDT_COUNT(wdtbase)); + spin_unlock_irqrestore(&wdt_lock, flags); + + /* Mask out the upper 16-bits and return */ + return val & AMD_WDT_COUNT_MASK; +} + +static unsigned int amd_wdt_status(struct watchdog_device *wdt_dev) +{ + return wdt_dev->status; +} + +static struct watchdog_ops amd_wdt_ops = { + .owner = THIS_MODULE, + .start = amd_wdt_start, + .stop = amd_wdt_stop, + .ping = amd_wdt_ping, + .status = amd_wdt_status, + .set_timeout = amd_wdt_set_timeout, + .get_timeleft = amd_wdt_get_timeleft, +}; +static struct watchdog_info amd_wdt_info = { + .options = WDIOF_SETTIMEOUT | + WDIOF_MAGICCLOSE | + WDIOF_KEEPALIVEPING, + .firmware_version = 0, + .identity = WDT_MODULE_NAME, +}; + +static struct watchdog_device amd_wdt_dev = { + .info = &amd_wdt_info, + .ops = &amd_wdt_ops, +}; + +/* + * The PCI Device ID table below is used to identify the platform + * the driver is supposed to work for. Since this is a platform + * device, we need a way for us to be able to find the correct + * platform when the driver gets loaded, otherwise we should + * bail out. + */ +static const struct pci_device_id amd_wdt_pci_tbl[] = { + { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CARRIZO_SMBUS, PCI_ANY_ID, + PCI_ANY_ID, }, + { 0, }, +}; +MODULE_DEVICE_TABLE(pci, amd_wdt_pci_tbl); + +static unsigned char amd_wdt_setupdevice(void) +{ + struct pci_dev *dev = NULL; + u32 val; + + /* Match the PCI device */ + for_each_pci_dev(dev) { + if (pci_match_id(amd_wdt_pci_tbl, dev) != NULL) { + amd_wdt_pci = dev; + break; + } + } + + if (!amd_wdt_pci) + return 0; + + /* Watchdog Base Address starts from ACPI MMIO Base Address + 0xB00 */ + wdtbase_phys = AMD_ACPI_MMIO_BASE + AMD_WDT_MEM_MAP_OFFSET; + if (!request_mem_region_exclusive(wdtbase_phys, AMD_WDT_MEM_MAP_SIZE, + "AMD Watchdog")) { + pr_err("mmio address 0x%04x already in use\n", wdtbase_phys); + goto exit; + } + + wdtbase = ioremap(wdtbase_phys, AMD_WDT_MEM_MAP_SIZE); + if (!wdtbase) { + pr_err("failed to get wdtbase address\n"); + goto unreg_mem_region; + } + + /* Enable watchdog timer and decode bit */ + outb(AMD_PM_WATCHDOG_EN_REG, AMD_IO_PM_INDEX_REG); + val = inb(AMD_IO_PM_DATA_REG); + val |= AMD_PM_WATCHDOG_TIMER_EN; + outb(val, AMD_IO_PM_DATA_REG); + + /* Set the watchdog timer resolution */ + outb(AMD_PM_WATCHDOG_CONFIG_REG, AMD_IO_PM_INDEX_REG); + val = inb(AMD_IO_PM_DATA_REG); + /* Clear the previous frequency setting, if any */ + val &= ~AMD_PM_WATCHDOG_CONFIG_MASK; + + /* + * Now set the frequency depending on the module load parameter. + * In case the user passes an invalid argument, we consider the + * frequency to be of 1 second resolution. + */ + if (strncmp(frequency, "32us", 4) == 0) + val |= AMD_PM_WATCHDOG_32USEC_RES; + else if (strncmp(frequency, "10ms", 4) == 0) + val |= AMD_PM_WATCHDOG_10MSEC_RES; + else if (strncmp(frequency, "100ms", 5) == 0) + val |= AMD_PM_WATCHDOG_100MSEC_RES; + else { + val |= AMD_PM_WATCHDOG_1SEC_RES; + if (strncmp(frequency, "1s", 2) != 0) + strncpy(frequency, "1s", 2); + } + + outb(val, AMD_IO_PM_DATA_REG); + + /* Check to see if last reboot was due to watchdog timeout */ + val = readl(AMD_WDT_CONTROL(wdtbase)); + + + /* Clear out the old status */ + + /* + * Set the watchdog action depending on module load parameter. + * + * If action is specified anything other than reboot or shutdown, + * we default it to reboot. + */ + if (strncmp(action, "shutdown", 8) == 0) + val |= AMD_WDT_ACTION_RESET_BIT; + else { + val &= ~AMD_WDT_ACTION_RESET_BIT; + /* The statement below is required for when the action + * is set anything other than reboot. + */ + if (strncmp(action, "reboot", 6) != 0) + strncpy(action, "reboot", 6); + } + + writel(val, AMD_WDT_CONTROL(wdtbase)); + + return 1; + +unreg_mem_region: + release_mem_region(wdtbase_phys, AMD_WDT_MEM_MAP_SIZE); +exit: + return 0; +} + +static int amd_wdt_init(struct platform_device *dev) +{ + int ret; + u32 val; + + /* Identify our device and initialize watchdog hardware */ + if (!amd_wdt_setupdevice()) + return -ENODEV; + val = readl(AMD_WDT_CONTROL(wdtbase)); + if (val & AMD_WDT_FIRED_BIT) + amd_wdt_dev.bootstatus |= WDIOF_CARDRESET; + else + amd_wdt_dev.bootstatus &= ~WDIOF_CARDRESET; + + pr_info("Watchdog reboot %sdetected\n", + (val & AMD_WDT_FIRED_BIT) ? "" : "not "); + + /* Clear out the old status */ + val |= AMD_WDT_FIRED_BIT; + writel(val, AMD_WDT_CONTROL(wdtbase)); + + amd_wdt_dev.timeout = heartbeat; + amd_wdt_dev.min_timeout = AMD_WDT_MIN_TIMEOUT; + amd_wdt_dev.max_timeout = AMD_WDT_MAX_TIMEOUT; + watchdog_set_nowayout(&amd_wdt_dev, nowayout); + + /* Make sure watchdog is not running */ + amd_wdt_stop(&amd_wdt_dev); + + /* Set Watchdog timeout */ + amd_wdt_set_timeout(&amd_wdt_dev, heartbeat); + + ret = watchdog_register_device(&amd_wdt_dev); + if (ret != 0) { + pr_err("Watchdog timer: cannot register watchdog device" + " (err=%d)\n", ret); + goto exit; + } + + pr_info("initialized (0x%p). (timeout=%d units) (frequency=%s) " + "(nowayout=%d) (action=%s)\n", wdtbase, heartbeat, frequency, + nowayout, action); + + return 0; + +exit: + iounmap(wdtbase); + release_mem_region(wdtbase_phys, AMD_WDT_MEM_MAP_SIZE); + return ret; +} + +static void amd_wdt_cleanup(void) +{ + /* Stop the timer before we leave */ + if (!nowayout) + amd_wdt_stop(NULL); + + watchdog_unregister_device(&amd_wdt_dev); + iounmap(wdtbase); + release_mem_region(wdtbase_phys, AMD_WDT_MEM_MAP_SIZE); +} + +static int amd_wdt_remove(struct platform_device *dev) +{ + if (wdtbase) + amd_wdt_cleanup(); + + return 0; +} + +static void amd_wdt_shutdown(struct platform_device *dev) +{ + amd_wdt_stop(NULL); +} + +static struct platform_driver amd_wdt_driver = { + .probe = amd_wdt_init, + .remove = amd_wdt_remove, + .shutdown = amd_wdt_shutdown, + .driver = { + .owner = THIS_MODULE, + .name = WDT_MODULE_NAME, + }, +}; + +static int __init amd_wdt_init_module(void) +{ + int err; + + pr_info("AMD WatchDog Timer Driver v%s\n", WDT_VERSION); + + err = platform_driver_register(&amd_wdt_driver); + if (err) + return err; + + amd_wdt_platform_device = platform_device_register_simple( + WDT_MODULE_NAME, -1, NULL, 0); + if (IS_ERR(amd_wdt_platform_device)) { + err = PTR_ERR(amd_wdt_platform_device); + goto unreg_platform_driver; + } + + return 0; + +unreg_platform_driver: + platform_driver_unregister(&amd_wdt_driver); + return err; +} + +static void __exit amd_wdt_cleanup_module(void) +{ + platform_device_unregister(amd_wdt_platform_device); + platform_driver_unregister(&amd_wdt_driver); + pr_info("AMD Watchdog Module Unloaded\n"); +} + +module_init(amd_wdt_init_module); +module_exit(amd_wdt_cleanup_module); + +MODULE_AUTHOR("Arindam Nath <arindam.nath@amd.com>"); +MODULE_DESCRIPTION("Watchdog timer driver for AMD chipsets"); +MODULE_LICENSE("Dual BSD/GPL"); diff --git a/meta-r1000/recipes-kernel/amd-wdt/files/amd_wdt.h b/meta-r1000/recipes-kernel/amd-wdt/files/amd_wdt.h new file mode 100644 index 00000000..855e6810 --- /dev/null +++ b/meta-r1000/recipes-kernel/amd-wdt/files/amd_wdt.h @@ -0,0 +1,46 @@ +#ifndef _AMD_WDT_H_ +#define _AMD_WDT_H_ + +/* Module and version information */ +#define WDT_VERSION "1.0" +#define WDT_MODULE_NAME "AMD watchdog timer" +#define WDT_DRIVER_NAME WDT_MODULE_NAME ", v" WDT_VERSION + +#define AMD_WDT_DEFAULT_TIMEOUT 60 /* 60 units default heartbeat. */ +#define AMD_WDT_MIN_TIMEOUT 0x0001 /* minimum timeout value */ +#define AMD_WDT_MAX_TIMEOUT 0xFFFF /* maximum timeout value */ +#define MAX_LENGTH (8 + 1) /* shutdown has 8 characters + NULL character */ + +/* Watchdog register definitions */ +#define AMD_ACPI_MMIO_BASE 0xFED80000 +#define AMD_WDT_MEM_MAP_OFFSET 0xB00 +#define AMD_WDT_MEM_MAP_SIZE 0x100 + +#define AMD_WDT_CONTROL(base) ((base) + 0x00) /* Watchdog Control */ + #define AMD_WDT_START_STOP_BIT (1 << 0) + #define AMD_WDT_FIRED_BIT (1 << 1) + #define AMD_WDT_ACTION_RESET_BIT (1 << 2) + #define AMD_WDT_DISABLE_BIT (1 << 3) + /* 6:4 bits Reserved */ + #define AMD_WDT_TRIGGER_BIT (1 << 7) +#define AMD_WDT_COUNT(base) ((base) + 0x04) /* Watchdog Count */ + #define AMD_WDT_COUNT_MASK 0xFFFF + +#define AMD_PM_WATCHDOG_EN_REG 0x00 + #define AMD_PM_WATCHDOG_TIMER_EN (0x01 << 7) + +#define AMD_PM_WATCHDOG_CONFIG_REG 0x03 + #define AMD_PM_WATCHDOG_32USEC_RES 0x0 + #define AMD_PM_WATCHDOG_10MSEC_RES 0x1 + #define AMD_PM_WATCHDOG_100MSEC_RES 0x2 + #define AMD_PM_WATCHDOG_1SEC_RES 0x3 +#define AMD_PM_WATCHDOG_CONFIG_MASK 0x3 + +/* IO port address for indirect access using ACPI PM registers */ +#define AMD_IO_PM_INDEX_REG 0xCD6 +#define AMD_IO_PM_DATA_REG 0xCD7 + +#define AMD_ACPI_MMIO_ADDR_MASK ~0x1FFF +#define PCI_DEVICE_ID_AMD_CARRIZO_SMBUS 0x790B + +#endif /* _AMD_WDT_H_ */ diff --git a/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware.bb b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware.bb new file mode 100644 index 00000000..93fbfc8d --- /dev/null +++ b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware.bb @@ -0,0 +1,35 @@ +DESCRIPTION = "These binaries provide kernel support for newer AMD GPUs" +SECTION = "kernel" +LICENSE = "Firmware-amd" + +SRC_URI = "file://raven2_asd.bin \ + file://raven2_ce.bin \ + file://raven2_gpu_info.bin \ + file://raven2_me.bin \ + file://raven2_mec2.bin \ + file://raven2_mec.bin \ + file://raven2_pfp.bin \ + file://raven2_rlc.bin \ + file://raven2_sdma1.bin \ + file://raven2_sdma.bin \ + file://raven2_vcn.bin \ + file://LICENSE" + +LIC_FILES_CHKSUM = "file://LICENSE;md5=07b0c31777bd686d8e1609c6940b5e74" + +S = "${WORKDIR}" + +# Since, no binaries are generated for a specific target, +# inherit allarch to simply populate prebuilt binaries +inherit allarch + +do_compile() { + : +} + +do_install() { + install -v -m 444 -D ${S}/LICENSE ${D}/lib/firmware/amdgpu/LICENSE + install -v -m 0644 ${S}/*.bin ${D}/lib/firmware/amdgpu +} + +FILES_${PN} = "/lib/firmware/*" diff --git a/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/LICENSE b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/LICENSE new file mode 100644 index 00000000..fe3780b3 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/LICENSE @@ -0,0 +1,51 @@ +Copyright (C) 2009-2014 Advanced Micro Devices, Inc. All rights reserved. + +REDISTRIBUTION: Permission is hereby granted, free of any license fees, +to any person obtaining a copy of this microcode (the "Software"), to +install, reproduce, copy and distribute copies, in binary form only, of +the Software and to permit persons to whom the Software is provided to +do the same, provided that the following conditions are met: + +No reverse engineering, decompilation, or disassembly of this Software +is permitted. + +Redistributions must reproduce the above copyright notice, this +permission notice, and the following disclaimers and notices in the +Software documentation and/or other materials provided with the +Software. + +DISCLAIMER: THE USE OF THE SOFTWARE IS AT YOUR SOLE RISK. THE SOFTWARE +IS PROVIDED "AS IS" AND WITHOUT WARRANTY OF ANY KIND AND COPYRIGHT +HOLDER AND ITS LICENSORS EXPRESSLY DISCLAIM ALL WARRANTIES, EXPRESS AND +IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +COPYRIGHT HOLDER AND ITS LICENSORS DO NOT WARRANT THAT THE SOFTWARE WILL +MEET YOUR REQUIREMENTS, OR THAT THE OPERATION OF THE SOFTWARE WILL BE +UNINTERRUPTED OR ERROR-FREE. THE ENTIRE RISK ASSOCIATED WITH THE USE OF +THE SOFTWARE IS ASSUMED BY YOU. FURTHERMORE, COPYRIGHT HOLDER AND ITS +LICENSORS DO NOT WARRANT OR MAKE ANY REPRESENTATIONS REGARDING THE USE +OR THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, +ACCURACY, RELIABILITY, CURRENTNESS, OR OTHERWISE. + +DISCLAIMER: UNDER NO CIRCUMSTANCES INCLUDING NEGLIGENCE, SHALL COPYRIGHT +HOLDER AND ITS LICENSORS OR ITS DIRECTORS, OFFICERS, EMPLOYEES OR AGENTS +("AUTHORIZED REPRESENTATIVES") BE LIABLE FOR ANY INCIDENTAL, INDIRECT, +SPECIAL OR CONSEQUENTIAL DAMAGES (INCLUDING DAMAGES FOR LOSS OF BUSINESS +PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, AND THE +LIKE) ARISING OUT OF THE USE, MISUSE OR INABILITY TO USE THE SOFTWARE, +BREACH OR DEFAULT, INCLUDING THOSE ARISING FROM INFRINGEMENT OR ALLEGED +INFRINGEMENT OF ANY PATENT, TRADEMARK, COPYRIGHT OR OTHER INTELLECTUAL +PROPERTY RIGHT EVEN IF COPYRIGHT HOLDER AND ITS AUTHORIZED +REPRESENTATIVES HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. IN +NO EVENT SHALL COPYRIGHT HOLDER OR ITS AUTHORIZED REPRESENTATIVES TOTAL +LIABILITY FOR ALL DAMAGES, LOSSES, AND CAUSES OF ACTION (WHETHER IN +CONTRACT, TORT (INCLUDING NEGLIGENCE) OR OTHERWISE) EXCEED THE AMOUNT OF +US$10. + +Notice: The Software is subject to United States export laws and +regulations. You agree to comply with all domestic and international +export laws and regulations that apply to the Software, including but +not limited to the Export Administration Regulations administered by the +U.S. Department of Commerce and International Traffic in Arm Regulations +administered by the U.S. Department of State. These laws include +restrictions on destinations, end users and end use. diff --git a/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_asd.bin b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_asd.bin Binary files differnew file mode 100644 index 00000000..186cb5b4 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_asd.bin diff --git a/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_ce.bin b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_ce.bin Binary files differnew file mode 100644 index 00000000..015bb206 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_ce.bin diff --git a/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_gpu_info.bin b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_gpu_info.bin Binary files differnew file mode 100644 index 00000000..4c361f50 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_gpu_info.bin diff --git a/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_me.bin b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_me.bin Binary files differnew file mode 100644 index 00000000..b2e0ec2d --- /dev/null +++ b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_me.bin diff --git a/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_mec.bin b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_mec.bin Binary files differnew file mode 100644 index 00000000..5b68507f --- /dev/null +++ b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_mec.bin diff --git a/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_mec2.bin b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_mec2.bin Binary files differnew file mode 100644 index 00000000..5b68507f --- /dev/null +++ b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_mec2.bin diff --git a/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_pfp.bin b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_pfp.bin Binary files differnew file mode 100644 index 00000000..17597231 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_pfp.bin diff --git a/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_rlc.bin b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_rlc.bin Binary files differnew file mode 100644 index 00000000..af7d365a --- /dev/null +++ b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_rlc.bin diff --git a/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_sdma.bin b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_sdma.bin Binary files differnew file mode 100644 index 00000000..80e4fb65 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_sdma.bin diff --git a/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_sdma1.bin b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_sdma1.bin Binary files differnew file mode 100644 index 00000000..d86fc166 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_sdma1.bin diff --git a/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_vcn.bin b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_vcn.bin Binary files differnew file mode 100644 index 00000000..f20b5512 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux-firmware/amdgpu-firmware/raven2_vcn.bin diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-extra-config.cfg b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-extra-config.cfg new file mode 100644 index 00000000..11400909 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-extra-config.cfg @@ -0,0 +1,416 @@ +CONFIG_PERF_EVENTS_INTEL_UNCORE=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_PGTABLE_LEVELS=4 +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_USELIB=y +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y +CONFIG_SRCU=y +# CONFIG_TASKS_RCU is not set +CONFIG_RCU_KTHREAD_PRIO=0 +# CONFIG_RCU_EXPEDITE_BOOT is not set +CONFIG_BUILD_BIN2C=y +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 +CONFIG_PAGE_COUNTER=y +CONFIG_BPF=y +CONFIG_MULTIUSER=y +CONFIG_SGETMASK_SYSCALL=y +CONFIG_SYSFS_SYSCALL=y +# CONFIG_BPF_SYSCALL is not set +CONFIG_ADVISE_SYSCALLS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_ARCH_HUGE_VMAP=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +# CONFIG_MODULE_COMPRESS is not set +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_ARCH_USE_QUEUE_RWLOCK=y +CONFIG_QUEUE_RWLOCK=y +CONFIG_X86_FEATURE_NAMES=y +# CONFIG_X86_GOLDFISH is not set +CONFIG_IOSF_MBI=m +# CONFIG_IOSF_MBI_DEBUG is not set +CONFIG_X86_VSYSCALL_EMULATION=y +CONFIG_X86_DIRECT_GBPAGES=y +CONFIG_MEMORY_BALLOON=y +# CONFIG_ZSWAP is not set +# CONFIG_ZPOOL is not set +# CONFIG_ZBUD is not set +CONFIG_GENERIC_EARLY_IOREMAP=y +# CONFIG_X86_PMEM_LEGACY is not set +# CONFIG_X86_INTEL_MPX is not set +# CONFIG_EFI_MIXED is not set +CONFIG_HAVE_LIVEPATCH=y +# CONFIG_LIVEPATCH is not set +CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y +CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y +CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y +CONFIG_ACPI_HOTPLUG_IOAPIC=y +# CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set +CONFIG_HAVE_ACPI_APEI=y +CONFIG_HAVE_ACPI_APEI_NMI=y +# CONFIG_PMIC_OPREGION is not set +CONFIG_PCI_BUS_ADDR_T_64BIT=y +CONFIG_PMC_ATOM=y +CONFIG_NET_UDP_TUNNEL=m +# CONFIG_NET_FOU is not set +# CONFIG_NET_FOU_IP_TUNNELS is not set +# CONFIG_GENEVE is not set +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_BRIDGE_NETFILTER=m +CONFIG_NF_NAT_REDIRECT=m +# CONFIG_NETFILTER_XT_NAT is not set +# CONFIG_NF_LOG_ARP is not set +# CONFIG_NF_LOG_IPV4 is not set +CONFIG_NF_REJECT_IPV4=m +CONFIG_NF_NAT_IPV4=m +# CONFIG_NF_NAT_MASQUERADE_IPV4 is not set +CONFIG_NF_NAT_PROTO_GRE=m +CONFIG_NF_NAT_PPTP=m +CONFIG_NF_NAT_H323=m +# CONFIG_IP_NF_NAT is not set +# CONFIG_NF_REJECT_IPV6 is not set +# CONFIG_NF_LOG_IPV6 is not set +CONFIG_TIPC_MEDIA_UDP=y +# CONFIG_NET_ACT_VLAN is not set +# CONFIG_NET_ACT_BPF is not set +# CONFIG_NET_ACT_CONNMARK is not set +# CONFIG_MPLS is not set +# CONFIG_NET_SWITCHDEV is not set +# CONFIG_MAC80211_RC_MINSTREL_VHT is not set +CONFIG_UEVENT_HELPER=y +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_ALLOW_DEV_COREDUMP=y +# CONFIG_FENCE_TRACE is not set +# CONFIG_BLK_DEV_PMEM is not set +# CONFIG_INTEL_MEI_TXE is not set +# CONFIG_INTEL_MIC_BUS is not set +# CONFIG_ECHO is not set +# CONFIG_CXL_BASE is not set +# CONFIG_SCSI_MQ_DEFAULT is not set +# CONFIG_SCSI_AM53C974 is not set +# CONFIG_SCSI_WD719X is not set +# CONFIG_DM_MQ_DEFAULT is not set +# CONFIG_DM_ERA is not set +# CONFIG_DM_LOG_WRITES is not set +# CONFIG_IPVLAN is not set +# CONFIG_NET_VENDOR_AGERE is not set +# CONFIG_ET131X is not set +# CONFIG_ALTERA_TSE is not set +# CONFIG_BCMGENET is not set +# CONFIG_CX_ECAT is not set +# CONFIG_FM10K is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_SXGBE_ETH is not set +# CONFIG_TI_CPSW_ALE is not set +# CONFIG_BCM7XXX_PHY is not set +CONFIG_MARVELL_PHY=y +# CONFIG_MDIO_BCM_UNIMAC is not set +CONFIG_USB_NET_DRIVERS=y +# CONFIG_ATH9K_DYNACK is not set +# CONFIG_ATH9K_CHANNEL_CONTEXT is not set +CONFIG_ATH9K_PCOEM=y +CONFIG_BRCMFMAC_PROTO_BCDC=y +# CONFIG_BRCMFMAC_PCIE is not set +# CONFIG_RTL8723BE is not set +# CONFIG_RTL8192EE is not set +# CONFIG_RTL8821AE is not set +# CONFIG_RSI_91X is not set +# CONFIG_MOUSE_PS2_FOCALTECH is not set +# CONFIG_MOUSE_ELAN_I2C is not set +# CONFIG_TABLET_SERIAL_WACOM4 is not set +# CONFIG_TOUCHSCREEN_GOODIX is not set +# CONFIG_TOUCHSCREEN_ELAN is not set +# CONFIG_TOUCHSCREEN_SX8654 is not set +CONFIG_DEVMEM=y +CONFIG_SERIAL_EARLYCON=y +# CONFIG_SERIAL_8250_FINTEK is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_IPMI_SSIF is not set +# CONFIG_TCG_CRB is not set +# CONFIG_TCG_TIS_ST33ZP24 is not set +# CONFIG_XILLYBUS is not set +CONFIG_ACPI_I2C_OPREGION=y +# CONFIG_I2C_SLAVE is not set +# CONFIG_SPI_CADENCE is not set +# CONFIG_SPMI is not set +# CONFIG_PINCTRL_BAYTRAIL is not set +# CONFIG_PINCTRL_CHERRYVIEW is not set +# CONFIG_PINCTRL_SUNRISEPOINT is not set +CONFIG_GPIOLIB_IRQCHIP=y +# CONFIG_GPIO_DWAPB is not set +# CONFIG_GPIO_F7188X is not set +# CONFIG_GPIO_ICH is not set +# CONFIG_GPIO_LYNXPOINT is not set +# CONFIG_GPIO_SCH311X is not set +# CONFIG_GPIO_ADP5588 is not set +# CONFIG_GPIO_BT8XX is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_SENSORS_APPLESMC is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_G762 is not set +# CONFIG_SENSORS_I5500 is not set +# CONFIG_SENSORS_CORETEMP is not set +# CONFIG_SENSORS_POWR1220 is not set +# CONFIG_SENSORS_LTC2945 is not set +# CONFIG_SENSORS_LTC4151 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4222 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LTC4260 is not set +# CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX16065 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX1668 is not set +# CONFIG_SENSORS_MAX197 is not set +# CONFIG_SENSORS_MAX6639 is not set +# CONFIG_SENSORS_MAX6642 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_MAX6697 is not set +# CONFIG_SENSORS_HTU21 is not set +# CONFIG_SENSORS_MCP3021 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_NTC_THERMISTOR is not set +# CONFIG_SENSORS_NCT6683 is not set +# CONFIG_SENSORS_NCT6775 is not set +# CONFIG_SENSORS_NCT7802 is not set +# CONFIG_SENSORS_NCT7904 is not set +# CONFIG_SENSORS_SHTC1 is not set +# CONFIG_SENSORS_SMM665 is not set +# CONFIG_SENSORS_ADC128D818 is not set +# CONFIG_SENSORS_TMP103 is not set +# CONFIG_THERMAL_GOV_BANG_BANG is not set +# CONFIG_INTEL_SOC_DTS_THERMAL is not set +# CONFIG_INT340X_THERMAL is not set +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_CADENCE_WATCHDOG is not set +CONFIG_BCMA_DRIVER_PCI=y +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_AXP20X is not set +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_INTEL_QUARK_I2C_GPIO is not set +# CONFIG_INTEL_SOC_PMIC is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RTSX_USB is not set +# CONFIG_MFD_RN5T618 is not set +# CONFIG_MFD_SKY81452 is not set +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MEDIA_SDR_SUPPORT is not set +# CONFIG_USB_GSPCA_DTCS033 is not set +# CONFIG_USB_GSPCA_TOUPTEK is not set +# CONFIG_DRM_I2C_ADV7511 is not set +# CONFIG_DRM_AMD_POWERPLAY is not set +# CONFIG_DRM_VGEM is not set +CONFIG_FB_CMDLINE=y +CONFIG_HDMI=y +CONFIG_DUMMY_CONSOLE_COLUMNS=80 +CONFIG_DUMMY_CONSOLE_ROWS=25 +CONFIG_SND_DMAENGINE_PCM=m +# CONFIG_SND_SE6X is not set +CONFIG_SND_HDA=y +CONFIG_SND_HDA_PREALLOC_SIZE=64 +# CONFIG_SND_HDA_CODEC_CA0132_DSP is not set +CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0 +CONFIG_SND_HDA_CORE=y +# CONFIG_SND_BCD2000 is not set +# CONFIG_SND_USB_POD is not set +# CONFIG_SND_USB_PODHD is not set +# CONFIG_SND_USB_TONEPORT is not set +# CONFIG_SND_USB_VARIAX is not set +CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +# CONFIG_SND_SOC_FSL_ASRC is not set +# CONFIG_SND_SOC_FSL_SAI is not set +# CONFIG_SND_SOC_FSL_SSI is not set +# CONFIG_SND_SOC_FSL_SPDIF is not set +# CONFIG_SND_SOC_FSL_ESAI is not set +# CONFIG_SND_SOC_IMX_AUDMUX is not set +# CONFIG_SND_SOC_INTEL_BYTCR_RT5640_MACH is not set +# CONFIG_SND_SOC_QCOM is not set +# CONFIG_SND_SOC_XTFPGA_I2S is not set +# CONFIG_SND_SOC_ADAU1701 is not set +# CONFIG_SND_SOC_AK4104 is not set +# CONFIG_SND_SOC_AK4554 is not set +# CONFIG_SND_SOC_AK4642 is not set +# CONFIG_SND_SOC_AK5386 is not set +# CONFIG_SND_SOC_ALC5623 is not set +# CONFIG_SND_SOC_CS35L32 is not set +# CONFIG_SND_SOC_CS42L51_I2C is not set +# CONFIG_SND_SOC_CS42L52 is not set +# CONFIG_SND_SOC_CS42L56 is not set +# CONFIG_SND_SOC_CS42L73 is not set +# CONFIG_SND_SOC_CS4265 is not set +# CONFIG_SND_SOC_CS4270 is not set +# CONFIG_SND_SOC_CS4271_I2C is not set +# CONFIG_SND_SOC_CS4271_SPI is not set +# CONFIG_SND_SOC_CS42XX8_I2C is not set +# CONFIG_SND_SOC_HDMI_CODEC is not set +# CONFIG_SND_SOC_ES8328 is not set +# CONFIG_SND_SOC_PCM1681 is not set +# CONFIG_SND_SOC_PCM1792A is not set +# CONFIG_SND_SOC_PCM512x_I2C is not set +# CONFIG_SND_SOC_PCM512x_SPI is not set +# CONFIG_SND_SOC_RT5631 is not set +# CONFIG_SND_SOC_RT5677_SPI is not set +# CONFIG_SND_SOC_SGTL5000 is not set +# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set +# CONFIG_SND_SOC_SPDIF is not set +# CONFIG_SND_SOC_SSM2602_SPI is not set +# CONFIG_SND_SOC_SSM2602_I2C is not set +# CONFIG_SND_SOC_SSM4567 is not set +# CONFIG_SND_SOC_STA32X is not set +# CONFIG_SND_SOC_STA350 is not set +# CONFIG_SND_SOC_TAS2552 is not set +# CONFIG_SND_SOC_TAS5086 is not set +# CONFIG_SND_SOC_TFA9879 is not set +# CONFIG_SND_SOC_TLV320AIC23_I2C is not set +# CONFIG_SND_SOC_TLV320AIC23_SPI is not set +# CONFIG_SND_SOC_TLV320AIC31XX is not set +# CONFIG_SND_SOC_TLV320AIC3X is not set +# CONFIG_SND_SOC_TS3A227E is not set +# CONFIG_SND_SOC_WM8510 is not set +# CONFIG_SND_SOC_WM8523 is not set +# CONFIG_SND_SOC_WM8580 is not set +# CONFIG_SND_SOC_WM8711 is not set +# CONFIG_SND_SOC_WM8728 is not set +# CONFIG_SND_SOC_WM8731 is not set +# CONFIG_SND_SOC_WM8737 is not set +# CONFIG_SND_SOC_WM8741 is not set +# CONFIG_SND_SOC_WM8750 is not set +# CONFIG_SND_SOC_WM8753 is not set +# CONFIG_SND_SOC_WM8770 is not set +# CONFIG_SND_SOC_WM8776 is not set +# CONFIG_SND_SOC_WM8804_I2C is not set +# CONFIG_SND_SOC_WM8804_SPI is not set +# CONFIG_SND_SOC_WM8903 is not set +# CONFIG_SND_SOC_WM8962 is not set +# CONFIG_SND_SOC_WM8978 is not set +# CONFIG_SND_SOC_TPA6130A2 is not set +# CONFIG_USB_OTG_FSM is not set +CONFIG_USB_XHCI_PCI=y +# CONFIG_USB_MAX3421_HCD is not set +# CONFIG_USB_UAS is not set +# CONFIG_USBIP_CORE is not set +# CONFIG_USB_ISP1760 is not set +# CONFIG_USB_LINK_LAYER_TEST is not set +# CONFIG_USB_CHAOSKEY is not set +# CONFIG_USB_LED_TRIG is not set +# CONFIG_MMC_USDHI6ROL0 is not set +# CONFIG_MMC_TOSHIBA_PCI is not set +# CONFIG_LEDS_CLASS_FLASH is not set +# CONFIG_LEDS_LP8860 is not set +# CONFIG_LEDS_PM8941_WLED is not set +# CONFIG_EDAC_IE31200 is not set +# CONFIG_RTC_DRV_ABB5ZES3 is not set +# CONFIG_RTC_DRV_ABX80X is not set +# CONFIG_RTC_DRV_PCF85063 is not set +# CONFIG_RTC_DRV_DS1343 is not set +# CONFIG_RTC_DRV_DS1347 is not set +# CONFIG_RTC_DRV_MCP795 is not set +# CONFIG_RTC_DRV_DS1685_FAMILY is not set +# CONFIG_RTC_DRV_DS2404 is not set +# CONFIG_RTC_DRV_XGENE is not set +CONFIG_VIRTIO_PCI_LEGACY=y +# CONFIG_VIRTIO_INPUT is not set +# CONFIG_R8723AU is not set +# CONFIG_FB_SM750 is not set +# CONFIG_GS_FPGABOOT is not set +# CONFIG_CRYPTO_SKEIN is not set +# CONFIG_UNISYSSPAR is not set +# CONFIG_FB_TFT is not set +CONFIG_I2O=m +CONFIG_I2O_LCT_NOTIFY_ON_CHANGES=y +CONFIG_I2O_EXT_ADAPTEC=y +CONFIG_I2O_EXT_ADAPTEC_DMA64=y +CONFIG_I2O_CONFIG=m +CONFIG_I2O_CONFIG_OLD_IOCTL=y +# CONFIG_I2O_BUS is not set +CONFIG_I2O_BLOCK=m +CONFIG_I2O_SCSI=m +CONFIG_I2O_PROC=m +# CONFIG_DELL_SMO8800 is not set +# CONFIG_TOSHIBA_HAPS is not set +# CONFIG_COMMON_CLK_PXA is not set +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_ATMEL_PIT is not set +# CONFIG_SH_TIMER_CMT is not set +# CONFIG_SH_TIMER_MTU2 is not set +# CONFIG_SH_TIMER_TMU is not set +# CONFIG_EM_TIMER_STI is not set +# CONFIG_SOC_TI is not set +# CONFIG_PM_DEVFREQ_EVENT is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_MCB is not set +CONFIG_RAS=y +# CONFIG_THUNDERBOLT is not set +# CONFIG_ANDROID is not set +CONFIG_EFI_RUNTIME_WRAPPERS=y +# CONFIG_EXT4_ENCRYPTION is not set +# CONFIG_F2FS_FS is not set +# CONFIG_FS_DAX is not set +# CONFIG_OVERLAY_FS is not set +CONFIG_KERNFS=y +CONFIG_EFIVAR_FS=m +# CONFIG_SQUASHFS_LZ4 is not set +# CONFIG_PSTORE_PMSG is not set +# CONFIG_AUFS_XATTR is not set +# CONFIG_NFSD_PNFS is not set +CONFIG_GRACE_PERIOD=y +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_DEBUG_INFO_SPLIT is not set +# CONFIG_DEBUG_INFO_DWARF4 is not set +# CONFIG_GDB_SCRIPTS is not set +# CONFIG_PAGE_OWNER is not set +# CONFIG_PAGE_EXTENSION is not set +CONFIG_HAVE_ARCH_KASAN=y +# CONFIG_KASAN is not set +CONFIG_KASAN_SHADOW_OFFSET=0xdffffc0000000000 +# CONFIG_SCHED_STACK_END_CHECK is not set +# CONFIG_DEBUG_TIMEKEEPING is not set +# CONFIG_LOCK_TORTURE_TEST is not set +# CONFIG_DEBUG_PI_LIST is not set +# CONFIG_PROVE_RCU is not set +# CONFIG_TORTURE_TEST is not set +# CONFIG_TRACEPOINT_BENCHMARK is not set +# CONFIG_TRACE_ENUM_MAP_FILE is not set +# CONFIG_TEST_HEXDUMP is not set +# CONFIG_TEST_RHASHTABLE is not set +# CONFIG_TEST_LKM is not set +# CONFIG_TEST_BPF is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_MEMTEST is not set +CONFIG_INTEGRITY=y +# CONFIG_INTEGRITY_SIGNATURE is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_MCRYPTD is not set +CONFIG_CRYPTO_GCM=m +CONFIG_CRYPTO_GHASH=m +# CONFIG_CRYPTO_SHA1_MB is not set +# CONFIG_CRYPTO_DES3_EDE_X86_64 is not set +# CONFIG_CRYPTO_DRBG_MENU is not set +# CONFIG_CRYPTO_USER_API_RNG is not set +# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set +CONFIG_KVM_COMPAT=y +# CONFIG_HAVE_ARCH_BITREVERSE is not set +CONFIG_RATIONAL=y +CONFIG_ARCH_HAS_FAST_MULTIPLIER=y +# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set +CONFIG_HAS_IOPORT_MAP=y +CONFIG_GLOB=y +# CONFIG_GLOB_SELFTEST is not set +CONFIG_ARCH_HAS_SG_CHAIN=y +CONFIG_MICROCODE_EARLY=y +# CONFIG_MICROCODE_INTEL_EARLY is not set +# CONFIG_PINMUX is not set +# CONFIG_PAGE_TABLE_ISOLATION is not set diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-gpu-config.cfg b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-gpu-config.cfg new file mode 100644 index 00000000..6cdacf5d --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-gpu-config.cfg @@ -0,0 +1,8 @@ +CONFIG_DRM_AMDGPU=m +CONFIG_DRM_AMDGPU_CIK=y +CONFIG_DRM_AMDGPU_USERPTR=y +CONFIG_HSA_AMD=y +CONFIG_DRM_AMD_DC=y +CONFIG_DRM_AMD_DC_DCN1_0=y +CONFIG_SND_SOC_AMD_ACP=m +CONFIG_SND_SOC_AMD_CZ_RT286_MACH=m diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-standard-only.cfg b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-standard-only.cfg new file mode 100644 index 00000000..bfc1701d --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-standard-only.cfg @@ -0,0 +1,3 @@ +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y +CONFIG_X86_POWERNOW_K8=y diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-user-config.cfg b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-user-config.cfg new file mode 100644 index 00000000..63234d47 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-user-config.cfg @@ -0,0 +1,204 @@ +CONFIG_GPIO_DEVRES=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_ACPI=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_GENERIC=m +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_SPIDEV=m +CONFIG_I2C_CHARDEV=m +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_PIIX4=m +CONFIG_IGB=m +CONFIG_SENSORS_K10TEMP=m +CONFIG_X86_MCE=y +CONFIG_X86_MCE_AMD=y +CONFIG_SND_USB=y +CONFIG_SND_HWDEP=y +CONFIG_SND_JACK=y +CONFIG_SND_SEQ_HRTIMER_DEFAULT=y +CONFIG_SND_HDA_RECONFIG=y +CONFIG_SND_HDA_INPUT_BEEP_MODE=1 +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SERIAL_NONSTANDARD=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_8250_NR_UARTS=16 +CONFIG_SERIAL_8250_RUNTIME_UARTS=8 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_RSA=y +CONFIG_X86_AMD_PLATFORM_DEVICE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_RCU_FAST_NO_HZ=y +CONFIG_CGROUP_PERF=y +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BLK_DEV_THROTTLING=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_CFQ_GROUP_IOSCHED=y +CONFIG_DEFAULT_DEADLINE=y +CONFIG_DEFAULT_IOSCHED="deadline" +CONFIG_PROCESSOR_SELECT=y +CONFIG_GART_IOMMU=y +CONFIG_CALGARY_IOMMU=y +CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT=y +CONFIG_NR_CPUS=24 +CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y +CONFIG_X86_MCE_INJECT=m +CONFIG_MICROCODE=y +CONFIG_X86_MSR=m +CONFIG_X86_CPUID=m +CONFIG_NUMA=y +CONFIG_AMD_NUMA=y +CONFIG_X86_64_ACPI_NUMA=y +CONFIG_NODES_SPAN_OTHER_NODES=y +CONFIG_NODES_SHIFT=6 +CONFIG_ARCH_MEMORY_PROBE=y +CONFIG_NEED_MULTIPLE_NODES=y +CONFIG_MEMORY_ISOLATION=y +CONFIG_HAVE_BOOTMEM_INFO_NODE=y +CONFIG_MEMORY_HOTPLUG=y +CONFIG_MEMORY_HOTPLUG_SPARSE=y +CONFIG_MEMORY_HOTREMOVE=y +CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y +CONFIG_NEED_BOUNCE_POOL=y +CONFIG_MMU_NOTIFIER=y +CONFIG_KSM=y +CONFIG_MEMORY_FAILURE=y +CONFIG_CLEANCACHE=y +CONFIG_FRONTSWAP=y +CONFIG_KEXEC=y +CONFIG_CRASH_DUMP=y +CONFIG_PHYSICAL_ALIGN=0x1000000 +CONFIG_COMPAT_VDSO=y +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +CONFIG_USE_PERCPU_NUMA_NODE_ID=y +CONFIG_ARCH_HIBERNATION_HEADER=y +CONFIG_HIBERNATE_CALLBACKS=y +CONFIG_HIBERNATION=y +CONFIG_PM_STD_PARTITION="" +CONFIG_PM_TRACE=y +CONFIG_PM_TRACE_RTC=y +CONFIG_ACPI_VIDEO=m +CONFIG_ACPI_NUMA=y +CONFIG_ACPI_SBS=m +CONFIG_ACPI_HED=y +CONFIG_ACPI_BGRT=y +CONFIG_ACPI_APEI=y +CONFIG_ACPI_APEI_GHES=y +CONFIG_ACPI_APEI_PCIEAER=y +CONFIG_ACPI_APEI_MEMORY_FAILURE=y +CONFIG_ACPI_APEI_EINJ=m +CONFIG_ACPI_APEI_ERST_DEBUG=m +CONFIG_SFI=y +CONFIG_CPU_FREQ_STAT_DETAILS=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_X86_PCC_CPUFREQ=m +CONFIG_X86_SPEEDSTEP_CENTRINO=y +CONFIG_X86_P4_CLOCKMOD=m +CONFIG_X86_SPEEDSTEP_LIB=m +CONFIG_PCI_MMCONFIG=y +CONFIG_PCI_REALLOC_ENABLE_AUTO=y +CONFIG_PCI_STUB=m +CONFIG_PCI_ATS=y +CONFIG_PCI_IOV=y +CONFIG_PCI_PRI=y +CONFIG_PCI_PASID=y +CONFIG_HOTPLUG_PCI_CPCI=y +CONFIG_HOTPLUG_PCI_CPCI_GENERIC=m +CONFIG_HOTPLUG_PCI_SHPC=m +CONFIG_X86_SYSFB=y +CONFIG_NET_SCH_FQ=m +CONFIG_ENCLOSURE_SERVICES=m +CONFIG_EEPROM_LEGACY=m +CONFIG_SATA_AHCI_PLATFORM=m +CONFIG_E1000=m +CONFIG_E1000E=m +CONFIG_SERIAL_8250_DETECT_IRQ=y +CONFIG_IPMI_HANDLER=m +CONFIG_HW_RANDOM_TPM=m +CONFIG_NVRAM=m +CONFIG_HANGCHECK_TIMER=m +CONFIG_TCG_TPM=y +CONFIG_GPIO_GENERIC_PLATFORM=m +CONFIG_SENSORS_K8TEMP=m +CONFIG_SENSORS_FAM15H_POWER=m +CONFIG_SENSORS_ACPI_POWER=m +CONFIG_AGP_AMD64=y +CONFIG_VGA_SWITCHEROO=y +CONFIG_VIDEO_OUTPUT_CONTROL=m +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_OHCI_HCD_PCI=m +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_MMC_SPI=m +CONFIG_EDAC=y +CONFIG_EDAC_LEGACY_SYSFS=y +CONFIG_EDAC_DECODE_MCE=y +CONFIG_EDAC_MCE_INJ=m +CONFIG_EDAC_MM_EDAC=m +CONFIG_EDAC_AMD64=m +CONFIG_SYNC_FILE=y +CONFIG_SW_SYNC=y +CONFIG_AUXDISPLAY=y +CONFIG_IOMMU_API=y +CONFIG_AMD_IOMMU=y +CONFIG_AMD_IOMMU_STATS=y +CONFIG_AMD_IOMMU_V2=m +CONFIG_DMAR_TABLE=y +CONFIG_IRQ_REMAP=y +CONFIG_PM_DEVFREQ=y +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y +CONFIG_DEVFREQ_GOV_PERFORMANCE=y +CONFIG_DEVFREQ_GOV_POWERSAVE=y +CONFIG_DEVFREQ_GOV_USERSPACE=y +CONFIG_MEMORY=y +CONFIG_EDD=y +CONFIG_EDD_OFF=y +CONFIG_DMI_SYSFS=m +CONFIG_EFI_VARS=y +CONFIG_EFI_VARS_PSTORE=y +CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y +CONFIG_EFI_RUNTIME_MAP=y +CONFIG_UEFI_CPER=y +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y +CONFIG_PROC_VMCORE=y +CONFIG_HUGETLBFS=y +CONFIG_HUGETLB_PAGE=y +CONFIG_PSTORE=y +CONFIG_SECURITYFS=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_INTERVAL_TREE=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_BLOCK_BOUNCE=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_PINCTRL_AMD=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_SND_DESIGNWARE_I2S=m +CONFIG_SND_SIMPLE_CARD=m +CONFIG_GPIO_ML_IOH=m +CONFIG_I2C_DESIGNWARE_CORE=y +CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_I2C_DESIGNWARE_PCI=m +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_DEBUG_RODATA is not set +CONFIG_DRM_AMD_ACP=y +CONFIG_SND_SOC=m +CONFIG_SND_SOC_AMD_ACP3x=m +CONFIG_FB_SIMPLE=y +CONFIG_LOGO=y +CONFIG_AMD_XGBE=y +CONFIG_AMD_XGBE_DCB=y +CONFIG_AMD_XGBE_HAVE_ECC=y diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-user-features.scc b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-user-features.scc new file mode 100644 index 00000000..e69de29b --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-user-features.scc diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-user-patches.scc b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-user-patches.scc new file mode 100755 index 00000000..e69de29b --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-user-patches.scc diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000.cfg b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000.cfg new file mode 100644 index 00000000..bd600b86 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000.cfg @@ -0,0 +1,61 @@ +CONFIG_PRINTK=y + +# Basic hardware support for the box - network, USB, PCI, sound +CONFIG_NETDEVICES=y +CONFIG_ATA=y +CONFIG_ATA_GENERIC=y +CONFIG_ATA_SFF=y +CONFIG_PCI=y +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PCI=y +CONFIG_USB_SUPPORT=y +CONFIG_USB=y +CONFIG_R8169=y +CONFIG_R8168=y +CONFIG_PATA_SCH=y +CONFIG_USB_EHCI_HCD=y +CONFIG_PCIEPORTBUS=y +CONFIG_NET=y +CONFIG_USB_UHCI_HCD=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y + +# Make sure these are on, otherwise the bootup won't be fun +CONFIG_EXT3_FS=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_MODULES=y +CONFIG_SHMEM=y +CONFIG_TMPFS=y +CONFIG_PACKET=y + +CONFIG_I2C=y +CONFIG_AGP=y +CONFIG_PM=y +CONFIG_ACPI=y +CONFIG_INPUT=y + +# Needed for booting (and using) USB memory sticks +CONFIG_BLK_DEV_LOOP=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y + +CONFIG_RD_GZIP=y + +# Filesystems +CONFIG_EXT2_FS_SECURITY=y +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +CONFIG_NFSD_V4=y +CONFIG_QFMT_V2 +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +CONFIG_QUOTA_TREE=m +CONFIG_QUOTACTL=y +CONFIG_SQUASHFS=y +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_ZLIB=y +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-r1000_4.14.inc b/meta-r1000/recipes-kernel/linux/linux-yocto-r1000_4.14.inc new file mode 100644 index 00000000..11c54127 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-r1000_4.14.inc @@ -0,0 +1,13 @@ +FILESEXTRAPATHS_prepend := "${THISDIR}/linux-yocto-${LINUX_VERSION}:" + +SRC_URI_append_r1000 += "file://r1000-user-features.scc \ + file://r1000-user-patches.scc \ + file://r1000.cfg \ + file://r1000-user-config.cfg \ + file://r1000-gpu-config.cfg \ + file://r1000-extra-config.cfg \ +" + +KERNEL_FEATURES_append_r1000 = " cfg/sound.scc" + +COMPATIBLE_MACHINE_r1000 = "r1000" diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto_4.14.bbappend b/meta-r1000/recipes-kernel/linux/linux-yocto_4.14.bbappend new file mode 100644 index 00000000..d71129e0 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto_4.14.bbappend @@ -0,0 +1,3 @@ +require linux-yocto-r1000_4.14.inc + +SRC_URI_append_r1000 += "file://r1000-standard-only.cfg" diff --git a/meta-r1000/recipes-rocm/hsa/files/hsa.tar.gz b/meta-r1000/recipes-rocm/hsa/files/hsa.tar.gz Binary files differnew file mode 100644 index 00000000..d9a080f2 --- /dev/null +++ b/meta-r1000/recipes-rocm/hsa/files/hsa.tar.gz diff --git a/meta-r1000/recipes-rocm/hsa/files/libhsakmt.tar.gz b/meta-r1000/recipes-rocm/hsa/files/libhsakmt.tar.gz Binary files differnew file mode 100644 index 00000000..ec2c5ac8 --- /dev/null +++ b/meta-r1000/recipes-rocm/hsa/files/libhsakmt.tar.gz diff --git a/meta-r1000/recipes-rocm/hsa/hsa.bb b/meta-r1000/recipes-rocm/hsa/hsa.bb new file mode 100644 index 00000000..d80faa9c --- /dev/null +++ b/meta-r1000/recipes-rocm/hsa/hsa.bb @@ -0,0 +1,31 @@ +SUMMARY = "AMD Heterogeneous System Architecture HSA" +DESCRIPTION = "This package includes the user-mode API \ + interfaces and libraries necessary for host \ + applications to launch compute kernels to \ + available HSA kernel agent." + +LICENSE = "NCSA" +LIC_FILES_CHKSUM = "file://LICENSE.txt;md5=abc754edcbe650f4f548eb4efc3cf8d5" + +RDEPENDS_${PN} = "libhsakmt" + +SRC_URI = "file://hsa.tar.gz" +SRC_URI[md5sum] = "e27a7b3821a6be61c510542840e865d2" + +S = "${WORKDIR}/hsa" + +# Skip configure and compile +do_configure[noexec] = "1" +do_compile[noexec] = "1" + +INSANE_SKIP_${PN} += "already-stripped build-deps ldflags" + +do_install () { + # Install the binary components + install -d ${D}${bindir} + cp -r ${S}/bin/* ${D}${bindir} + install -d ${D}${libdir} + cp -r ${S}/lib/* ${D}${libdir} + install -d ${D}${includedir} + cp -r ${S}/include/* ${D}${includedir} +} diff --git a/meta-r1000/recipes-rocm/hsa/libhsakmt.bb b/meta-r1000/recipes-rocm/hsa/libhsakmt.bb new file mode 100644 index 00000000..db535faf --- /dev/null +++ b/meta-r1000/recipes-rocm/hsa/libhsakmt.bb @@ -0,0 +1,29 @@ +SUMMARY = "ROCt Library" +DESCRIPTION = "This package includes the user-mode API interfaces \ + used to interact with the ROCk driver. Currently \ + supported agents include only the AMD/ATI Fiji family \ + of discrete GPUs." + +LICENSE = "MIT" +LIC_FILES_CHKSUM = "file://LICENSE.md;md5=b1afa13daf74f4073c4813368bc1b1b0" + +RDEPENDS_${PN} = "libpci numactl" + +SRC_URI = "file://libhsakmt.tar.gz" +SRC_URI[md5sum] = "4fe4381a7ec30219f115a8915c85a97c" + +S = "${WORKDIR}/libhsakmt" + +# Skip configure and compile +do_configure[noexec] = "1" +do_compile[noexec] = "1" + +INSANE_SKIP_${PN} += "already-stripped build-deps" + +do_install () { + # Install the binary components + install -d ${D}${libdir} + cp -r ${S}/lib/* ${D}${libdir} + install -d ${D}${includedir} + cp -r ${S}/include/* ${D}${includedir} +} diff --git a/meta-r1000/recipes-rocm/opencl/files/opencl.tar.gz b/meta-r1000/recipes-rocm/opencl/files/opencl.tar.gz Binary files differnew file mode 100644 index 00000000..43d62269 --- /dev/null +++ b/meta-r1000/recipes-rocm/opencl/files/opencl.tar.gz diff --git a/meta-r1000/recipes-rocm/opencl/opencl.bb b/meta-r1000/recipes-rocm/opencl/opencl.bb new file mode 100644 index 00000000..3a83afab --- /dev/null +++ b/meta-r1000/recipes-rocm/opencl/opencl.bb @@ -0,0 +1,38 @@ +SUMMARY = "OpenCL components for development on AMD platforms" +DESCRIPTION = "This package provides binary runtime/development \ + components for utilizing OpenCL on AMD platforms." + +LICENSE = "MIT" +LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302" + +RDEPENDS_${PN} = "hsa ${PN}-bitcodes ${PN}-amd-drivers" + +SRC_URI = "file://opencl.tar.gz" +SRC_URI[md5sum] = "8ace16bb9d76824ffad1dc0d18089466" + +S = "${WORKDIR}/opencl" + +# Skip configure and compile +do_configure[noexec] = "1" +do_compile[noexec] = "1" + +PACKAGES =+ "${PN}-bitcodes ${PN}-amd-drivers" + +FILES_${PN}-bitcodes = "${libdir}/bitcode/*" +FILES_${PN}-amd-drivers = "${libdir}/libcltrace.so \ + ${libdir}/libamdocl64.so" + +INSANE_SKIP_${PN} += "already-stripped build-deps ldflags" +INSANE_SKIP_${PN}-amd-drivers += "ldflags file-rdeps" + +do_install () { + # Install the binary components + install -d ${D}${bindir} + cp -r ${S}/bin/x86_64/* ${D}${bindir} + install -d ${D}${libdir} + cp -r ${S}/lib/x86_64/* ${D}${libdir} + install -d ${D}${includedir} + cp -r ${S}/include/* ${D}${includedir} + install -d ${D}${sysconfdir}/OpenCL + cp -r ${S}/etc/* ${D}${sysconfdir}/OpenCL +} |