diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3822-drm-amdgpu-cleanup-PTE-flag-generation-v3.patch')
-rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3822-drm-amdgpu-cleanup-PTE-flag-generation-v3.patch | 272 |
1 files changed, 272 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3822-drm-amdgpu-cleanup-PTE-flag-generation-v3.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3822-drm-amdgpu-cleanup-PTE-flag-generation-v3.patch new file mode 100644 index 00000000..46d877e0 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3822-drm-amdgpu-cleanup-PTE-flag-generation-v3.patch @@ -0,0 +1,272 @@ +From 7a77c6fa413d54dd9de3cff51b1083fb4e57df24 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com> +Date: Mon, 2 Sep 2019 16:39:40 +0200 +Subject: [PATCH 3822/4256] drm/amdgpu: cleanup PTE flag generation v3 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Move the ASIC specific code into a new callback function. + +v2: mask the flags for SI and CIK instead of a BUG_ON(). +v3: remove last missed BUG_ON(). + +Signed-off-by: Christian König <christian.koenig@amd.com> +Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> +Reviewed-by: Huang Rui <ray.huang@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 5 ++++ + drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 38 ++++++++++--------------- + drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 22 +++++++++++++- + drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 9 ++++++ + drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 11 ++++++- + drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 12 +++++++- + drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 24 +++++++++++++++- + 7 files changed, 94 insertions(+), 27 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h +index a669c5826415..88894fd2784d 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h +@@ -104,6 +104,10 @@ struct amdgpu_gmc_funcs { + /* get the pde for a given mc addr */ + void (*get_vm_pde)(struct amdgpu_device *adev, int level, + u64 *dst, u64 *flags); ++ /* get the pte flags to use for a BO VA mapping */ ++ void (*get_vm_pte)(struct amdgpu_device *adev, ++ struct amdgpu_bo_va_mapping *mapping, ++ uint64_t *flags); + }; + + struct amdgpu_xgmi { +@@ -186,6 +190,7 @@ struct amdgpu_gmc { + #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid)) + #define amdgpu_gmc_map_mtype(adev, flags) (adev)->gmc.gmc_funcs->map_mtype((adev),(flags)) + #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags)) ++#define amdgpu_gmc_get_vm_pte(adev, mapping, flags) (adev)->gmc.gmc_funcs->get_vm_pte((adev), (mapping), (flags)) + + /** + * amdgpu_gmc_vram_full_visible - Check if full VRAM is visible through the BAR +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +index d85753632840..604689385713 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +@@ -1573,6 +1573,7 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, + struct drm_mm_node *nodes, + struct dma_fence **fence) + { ++ uint64_t vram_base_offset = bo_adev->vm_manager.vram_base_offset; + unsigned min_linear_pages = 1 << adev->vm_manager.fragment_size; + uint64_t pfn, start = mapping->start; + int r; +@@ -1585,29 +1586,20 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, + if (!(mapping->flags & AMDGPU_PTE_WRITEABLE)) + flags &= ~AMDGPU_PTE_WRITEABLE; + +- if (adev->asic_type >= CHIP_TONGA) { +- flags &= ~AMDGPU_PTE_EXECUTABLE; +- flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; +- } +- +- if (adev->asic_type >= CHIP_NAVI10) { +- flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK; +- flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK); +- } else { +- flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; +- flags |= (mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK); +- } +- +- if ((mapping->flags & AMDGPU_PTE_PRT) && +- (adev->asic_type >= CHIP_VEGA10)) { +- flags |= AMDGPU_PTE_PRT; +- if (adev->asic_type >= CHIP_NAVI10) { +- flags |= AMDGPU_PTE_SNOOPED; +- flags |= AMDGPU_PTE_LOG; +- flags |= AMDGPU_PTE_SYSTEM; +- } +- flags &= ~AMDGPU_PTE_VALID; +- } ++ /* Apply ASIC specific mapping flags */ ++ amdgpu_gmc_get_vm_pte(adev, mapping, &flags); ++ ++ if (adev != bo_adev && ++ !(flags & AMDGPU_PTE_SYSTEM) && ++ !mapping->bo_va->is_xgmi) { ++ if (amdgpu_device_is_peer_accessible(bo_adev, adev)) { ++ flags |= AMDGPU_PTE_SYSTEM; ++ vram_base_offset = bo_adev->gmc.aper_base; ++ } else { ++ DRM_DEBUG_DRIVER("Failed to map the VRAM for peer device access.\n"); ++ return -EINVAL; ++ } ++ } + + trace_amdgpu_vm_bo_update(mapping); + +diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +index ebc2abbbf039..ed1c3b883f6a 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +@@ -440,12 +440,32 @@ static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level, + } + } + ++static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev, ++ struct amdgpu_bo_va_mapping *mapping, ++ uint64_t *flags) ++{ ++ *flags &= ~AMDGPU_PTE_EXECUTABLE; ++ *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; ++ ++ *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK; ++ *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK); ++ ++ if (mapping->flags & AMDGPU_PTE_PRT) { ++ *flags |= AMDGPU_PTE_PRT; ++ *flags |= AMDGPU_PTE_SNOOPED; ++ *flags |= AMDGPU_PTE_LOG; ++ *flags |= AMDGPU_PTE_SYSTEM; ++ *flags &= ~AMDGPU_PTE_VALID; ++ } ++} ++ + static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = { + .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb, + .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb, + .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping, + .map_mtype = gmc_v10_0_map_mtype, +- .get_vm_pde = gmc_v10_0_get_vm_pde ++ .get_vm_pde = gmc_v10_0_get_vm_pde, ++ .get_vm_pte = gmc_v10_0_get_vm_pte + }; + + static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev) +diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +index 2b6a0d27f085..5ed0d3993cb7 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +@@ -389,6 +389,14 @@ static void gmc_v6_0_get_vm_pde(struct amdgpu_device *adev, int level, + BUG_ON(*addr & 0xFFFFFF0000000FFFULL); + } + ++static void gmc_v6_0_get_vm_pte(struct amdgpu_device *adev, ++ struct amdgpu_bo_va_mapping *mapping, ++ uint64_t *flags) ++{ ++ *flags &= ~AMDGPU_PTE_EXECUTABLE; ++ *flags &= ~AMDGPU_PTE_PRT; ++} ++ + static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev, + bool value) + { +@@ -1144,6 +1152,7 @@ static const struct amdgpu_gmc_funcs gmc_v6_0_gmc_funcs = { + .emit_flush_gpu_tlb = gmc_v6_0_emit_flush_gpu_tlb, + .set_prt = gmc_v6_0_set_prt, + .get_vm_pde = gmc_v6_0_get_vm_pde, ++ .get_vm_pte = gmc_v6_0_get_vm_pte, + }; + + static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = { +diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +index 5a47f5c4a118..3fa973e6ec19 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +@@ -466,6 +466,14 @@ static void gmc_v7_0_get_vm_pde(struct amdgpu_device *adev, int level, + BUG_ON(*addr & 0xFFFFFF0000000FFFULL); + } + ++static void gmc_v7_0_get_vm_pte(struct amdgpu_device *adev, ++ struct amdgpu_bo_va_mapping *mapping, ++ uint64_t *flags) ++{ ++ *flags &= ~AMDGPU_PTE_EXECUTABLE; ++ *flags &= ~AMDGPU_PTE_PRT; ++} ++ + /** + * gmc_v8_0_set_fault_enable_default - update VM fault handling + * +@@ -1340,7 +1348,8 @@ static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = { + .emit_flush_gpu_tlb = gmc_v7_0_emit_flush_gpu_tlb, + .emit_pasid_mapping = gmc_v7_0_emit_pasid_mapping, + .set_prt = gmc_v7_0_set_prt, +- .get_vm_pde = gmc_v7_0_get_vm_pde ++ .get_vm_pde = gmc_v7_0_get_vm_pde, ++ .get_vm_pte = gmc_v7_0_get_vm_pte + }; + + static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = { +diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +index 8519d1346a37..238e20a8e4f0 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +@@ -694,6 +694,15 @@ static void gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, int level, + BUG_ON(*addr & 0xFFFFFF0000000FFFULL); + } + ++static void gmc_v8_0_get_vm_pte(struct amdgpu_device *adev, ++ struct amdgpu_bo_va_mapping *mapping, ++ uint64_t *flags) ++{ ++ *flags &= ~AMDGPU_PTE_EXECUTABLE; ++ *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; ++ *flags &= ~AMDGPU_PTE_PRT; ++} ++ + /** + * gmc_v8_0_set_fault_enable_default - update VM fault handling + * +@@ -1711,7 +1720,8 @@ static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = { + .emit_flush_gpu_tlb = gmc_v8_0_emit_flush_gpu_tlb, + .emit_pasid_mapping = gmc_v8_0_emit_pasid_mapping, + .set_prt = gmc_v8_0_set_prt, +- .get_vm_pde = gmc_v8_0_get_vm_pde ++ .get_vm_pde = gmc_v8_0_get_vm_pde, ++ .get_vm_pte = gmc_v8_0_get_vm_pte + }; + + static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = { +diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +index c95e62023e5e..561cc6bef280 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +@@ -654,12 +654,34 @@ static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, + } + } + ++static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev, ++ struct amdgpu_bo_va_mapping *mapping, ++ uint64_t *flags) ++{ ++ *flags &= ~AMDGPU_PTE_EXECUTABLE; ++ *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; ++ ++ *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; ++ *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK; ++ ++ if (mapping->flags & AMDGPU_PTE_PRT) { ++ *flags |= AMDGPU_PTE_PRT; ++ *flags &= ~AMDGPU_PTE_VALID; ++ } ++ ++ if (adev->asic_type == CHIP_ARCTURUS && ++ !(*flags & AMDGPU_PTE_SYSTEM) && ++ mapping->bo_va->is_xgmi) ++ *flags |= AMDGPU_PTE_SNOOPED; ++} ++ + static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { + .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, + .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb, + .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping, + .map_mtype = gmc_v9_0_map_mtype, +- .get_vm_pde = gmc_v9_0_get_vm_pde ++ .get_vm_pde = gmc_v9_0_get_vm_pde, ++ .get_vm_pte = gmc_v9_0_get_vm_pte + }; + + static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) +-- +2.17.1 + |