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Diffstat (limited to 'arch/arm64/boot/dts/qcom/sm8250.dtsi')
-rw-r--r--arch/arm64/boot/dts/qcom/sm8250.dtsi143
1 files changed, 71 insertions, 72 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index be970472f6c4..760501c1301a 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -671,6 +671,7 @@
firmware {
scm: scm {
compatible = "qcom,scm-sm8250", "qcom,scm";
+ qcom,dload-mode = <&tcsr 0x13000>;
#reset-cells = <1>;
};
};
@@ -2123,7 +2124,7 @@
qcom,bcm-voters = <&apps_bcm_voter>;
};
- pcie0: pci@1c00000 {
+ pcie0: pcie@1c00000 {
compatible = "qcom,pcie-sm8250";
reg = <0 0x01c00000 0 0x3000>,
<0 0x60000000 0 0xf1d>,
@@ -2227,7 +2228,7 @@
status = "disabled";
};
- pcie1: pci@1c08000 {
+ pcie1: pcie@1c08000 {
compatible = "qcom,pcie-sm8250";
reg = <0 0x01c08000 0 0x3000>,
<0 0x40000000 0 0xf1d>,
@@ -2328,7 +2329,7 @@
status = "disabled";
};
- pcie2: pci@1c10000 {
+ pcie2: pcie@1c10000 {
compatible = "qcom,pcie-sm8250";
reg = <0 0x01c10000 0 0x3000>,
<0 0x64000000 0 0xf1d>,
@@ -2434,7 +2435,7 @@
"jedec,ufs-2.0";
reg = <0 0x01d84000 0 0x3000>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&ufs_mem_phy_lanes>;
+ phys = <&ufs_mem_phy>;
phy-names = "ufsphy";
lanes-per-direction = <2>;
#reset-cells = <1>;
@@ -2463,29 +2464,48 @@
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
- freq-table-hz =
- <37500000 300000000>,
- <0 0>,
- <0 0>,
- <37500000 300000000>,
- <0 0>,
- <0 0>,
- <0 0>,
- <0 0>;
+
+ operating-points-v2 = <&ufs_opp_table>;
interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI_CH0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
interconnect-names = "ufs-ddr", "cpu-ufs";
status = "disabled";
+
+ ufs_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-37500000 {
+ opp-hz = /bits/ 64 <37500000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <37500000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <300000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
};
ufs_mem_phy: phy@1d87000 {
compatible = "qcom,sm8250-qmp-ufs-phy";
- reg = <0 0x01d87000 0 0x1c0>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ reg = <0 0x01d87000 0 0x1000>;
+
clock-names = "ref",
"ref_aux";
clocks = <&rpmhcc RPMH_CXO_CLK>,
@@ -2493,16 +2513,10 @@
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
- status = "disabled";
- ufs_mem_phy_lanes: phy@1d87400 {
- reg = <0 0x01d87400 0 0x16c>,
- <0 0x01d87600 0 0x200>,
- <0 0x01d87c00 0 0x200>,
- <0 0x01d87800 0 0x16c>,
- <0 0x01d87a00 0 0x200>;
- #phy-cells = <0>;
- };
+ #phy-cells = <0>;
+
+ status = "disabled";
};
cryptobam: dma-controller@1dc4000 {
@@ -2543,6 +2557,11 @@
#hwlock-cells = <1>;
};
+ tcsr: syscon@1fc0000 {
+ compatible = "qcom,sm8250-tcsr", "syscon";
+ reg = <0x0 0x1fc0000 0x0 0x30000>;
+ };
+
wsamacro: codec@3240000 {
compatible = "qcom,sm8250-lpass-wsa-macro";
reg = <0 0x03240000 0 0x1000>;
@@ -2565,7 +2584,7 @@
status = "disabled";
};
- swr0: soundwire-controller@3250000 {
+ swr0: soundwire@3250000 {
reg = <0 0x03250000 0 0x2000>;
compatible = "qcom,soundwire-v1.5.1";
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
@@ -2631,7 +2650,7 @@
#sound-dai-cells = <1>;
};
- swr1: soundwire-controller@3210000 {
+ swr1: soundwire@3210000 {
reg = <0 0x03210000 0 0x2000>;
compatible = "qcom,soundwire-v1.5.1";
status = "disabled";
@@ -2678,7 +2697,7 @@
};
/* tx macro */
- swr2: soundwire-controller@3230000 {
+ swr2: soundwire@3230000 {
reg = <0 0x03230000 0 0x2000>;
compatible = "qcom,soundwire-v1.5.1";
interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
@@ -3095,11 +3114,8 @@
clock-names = "apb_pclk";
out-ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
+ port {
tpda_out_funnel_qatb: endpoint {
remote-endpoint = <&funnel_qatb_in_tpda>;
};
@@ -3142,11 +3158,7 @@
};
in-ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
+ port {
funnel_qatb_in_tpda: endpoint {
remote-endpoint = <&tpda_out_funnel_qatb>;
};
@@ -3355,11 +3367,8 @@
};
in-ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
+ port {
etf_in_funnel_swao_out: endpoint {
remote-endpoint = <&funnel_swao_out_etf>;
};
@@ -3443,8 +3452,6 @@
clock-names = "apb_pclk";
out-ports {
- #address-cells = <1>;
- #size-cells = <0>;
port {
tpdm_mm_out_tpda9: endpoint {
remote-endpoint = <&tpda_9_in_tpdm_mm>;
@@ -3710,11 +3717,7 @@
};
in-ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
+ port {
funnel_apss_merg_in_funnel_apss: endpoint {
remote-endpoint = <&funnel_apss_out_funnel_apss_merg>;
};
@@ -3889,32 +3892,26 @@
usb_2_qmpphy: phy@88eb000 {
compatible = "qcom,sm8250-qmp-usb3-uni-phy";
- reg = <0 0x088eb000 0 0x200>;
- status = "disabled";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ reg = <0 0x088eb000 0 0x1000>;
clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
- <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_USB3_SEC_CLKREF_EN>,
- <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
- clock-names = "aux", "ref_clk_src", "ref", "com_aux";
+ <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "com_aux",
+ "pipe";
+ clock-output-names = "usb3_uni_phy_pipe_clk_src";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
- resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
- <&gcc GCC_USB3_PHY_SEC_BCR>;
- reset-names = "phy", "common";
+ resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
+ <&gcc GCC_USB3PHY_PHY_SEC_BCR>;
+ reset-names = "phy",
+ "phy_phy";
- usb_2_ssphy: phy@88eb200 {
- reg = <0 0x088eb200 0 0x200>,
- <0 0x088eb400 0 0x200>,
- <0 0x088eb800 0 0x800>;
- #clock-cells = <0>;
- #phy-cells = <0>;
- clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3_uni_phy_pipe_clk_src";
- };
+ status = "disabled";
};
sdhc_2: mmc@8804000 {
@@ -4141,6 +4138,7 @@
"dp_hs_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
+ wakeup-source;
resets = <&gcc GCC_USB30_PRIM_BCR>;
@@ -4209,6 +4207,7 @@
"dp_hs_phy_irq";
power-domains = <&gcc USB30_SEC_GDSC>;
+ wakeup-source;
resets = <&gcc GCC_USB30_SEC_BCR>;
@@ -4223,7 +4222,7 @@
iommus = <&apps_smmu 0x20 0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
- phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
+ phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
phy-names = "usb2-phy", "usb3-phy";
};
};
@@ -6018,7 +6017,7 @@
compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
reg = <0 0x17c10000 0 0x1000>;
clocks = <&sleep_clk>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
};
timer@17c20000 {
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-05-03 02:15:25 +0000