diff options
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts b/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts index 0afd90224a59..b11d694b98e1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts @@ -63,6 +63,50 @@ regulator-always-on; }; + reg_csi1_1v8: regulator-csi1-vdd1v8 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "CSI1_VDD1V8"; + gpio = <&expander0 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_baseboard_vdd3v3>; + }; + + reg_csi1_3v3: regulator-csi1-vdd3v3 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "CSI1_VDD3V3"; + gpio = <&expander0 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_vdd5v0>; + }; + + reg_csi2_1v8: regulator-csi2-vdd1v8 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_csi2_1v8>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "CSI2_VDD1V8"; + gpio = <&gpio3 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_baseboard_vdd3v3>; + }; + + reg_csi2_3v3: regulator-csi2-vdd3v3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_csi2_3v3>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "CSI2_VDD3V3"; + gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_vdd5v0>; + }; + regulator-vbus-usb20 { compatible = "regulator-fixed"; regulator-min-microvolt = <5000000>; @@ -413,6 +457,18 @@ >; }; + pinctrl_reg_csi2_1v8: regcsi21v8grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x19 + >; + }; + + pinctrl_reg_csi2_3v3: regcsi23v3grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x19 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x14f |