diff options
Diffstat (limited to 'meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8')
4 files changed, 1083 insertions, 0 deletions
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0058-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0058-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch new file mode 100644 index 00000000..8bc47a43 --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0058-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch @@ -0,0 +1,87 @@ +From bcbfd9f69d858306a080aa7213e96ca6eca66106 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Fri, 29 Mar 2019 12:08:39 +0530 +Subject: [PATCH 58/61] [Patch,Microblaze] : We will check the possibility of + peephole2 optimization,if we can then we will fix the compiler issue. + +--- + gcc/config/microblaze/microblaze.md | 63 ++++++++++++++++++++++--------------- + 1 file changed, 38 insertions(+), 25 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 88aee9e..8bd175f 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -880,31 +880,44 @@ + (set_attr "mode" "SI") + (set_attr "length" "4")]) + +-(define_peephole2 +- [(set (match_operand:SI 0 "register_operand") +- (fix:SI (match_operand:SF 1 "register_operand"))) +- (set (pc) +- (if_then_else (match_operator 2 "ordered_comparison_operator" +- [(match_operand:SI 3 "register_operand") +- (match_operand:SI 4 "arith_operand")]) +- (label_ref (match_operand 5)) +- (pc)))] +- "TARGET_HARD_FLOAT && !TARGET_MB_64" +- [(set (match_dup 1) (match_dup 3))] +- +- { +- rtx condition; +- rtx cmp_op0 = operands[3]; +- rtx cmp_op1 = operands[4]; +- rtx comp_reg = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); +- +- emit_insn (gen_cstoresf4 (comp_reg, operands[2], +- gen_rtx_REG (SFmode, REGNO (cmp_op0)), +- gen_rtx_REG (SFmode, REGNO (cmp_op1)))); +- condition = gen_rtx_NE (SImode, comp_reg, const0_rtx); +- emit_jump_insn (gen_condjump (condition, operands[5])); +- } +-) ++;; peephole2 optimization will be done only if fint and if-then-else ++;; are dependent.added condition for the same. ++;; if they are dependent then gcc is giving "flow control insn inside a basic block" ++;; testcase: ++;; volatile float vec = 1.0; ++;; volatile int ci = 2; ++;; register int cj = (int)(vec); ++;;// ci=cj; ++;;// if (ci <0) { ++;; if (cj < 0) { ++;; ci = 0; ++;; } ++;; commenting for now.we will check the possibility of this optimization later ++ ++;;(define_peephole2 ++;; [(set (match_operand:SI 0 "register_operand") ++;; (fix:SI (match_operand:SF 1 "register_operand"))) ++;; (set (pc) ++;; (if_then_else (match_operator 2 "ordered_comparison_operator" ++;; [(match_operand:SI 3 "register_operand") ++;; (match_operand:SI 4 "arith_operand")]) ++;; (label_ref (match_operand 5)) ++;; (pc)))] ++;; "TARGET_HARD_FLOAT && !TARGET_MB_64 && ((REGNO (operands[0])) == (REGNO (operands[3])))" ++;; [(set (match_dup 1) (match_dup 3))] ++;; { ++;; rtx condition; ++;; rtx cmp_op0 = operands[3]; ++;; rtx cmp_op1 = operands[4]; ++;; rtx comp_reg = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); ++;; ++;; emit_insn (gen_cstoresf4 (comp_reg, operands[2], ++;; gen_rtx_REG (SFmode, REGNO (cmp_op0)), ++;; gen_rtx_REG (SFmode, REGNO (cmp_op1)))); ++;; condition = gen_rtx_NE (SImode, comp_reg, const0_rtx); ++;; emit_jump_insn (gen_condjump (condition, operands[5])); ++;; } ++;;) + + ;;---------------------------------------------------------------- + ;; Negation and one's complement +-- +2.7.4 + diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0059-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0059-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch new file mode 100644 index 00000000..be4dfad5 --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0059-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch @@ -0,0 +1,51 @@ +From 2f22090a7e8216f7a9f7e958b77ac83006a7ce89 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Tue, 16 Apr 2019 17:20:24 +0530 +Subject: [PATCH 59/61] Reverting the patch as kernel boot is not working with + this patch CR-1026413 Revert "[Patch,Microblaze]:reverting the cost check + before propagating constants." + +This reverts commit 7156e379a67fa47a5fb9ede1448c0d528dbda65b. +--- + gcc/cprop.c | 4 ---- + 1 file changed, 4 deletions(-) + +diff --git a/gcc/cprop.c b/gcc/cprop.c +index deb706b..e4df509 100644 +--- a/gcc/cprop.c ++++ b/gcc/cprop.c +@@ -733,7 +733,6 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn) + int success = 0; + rtx set = single_set (insn); + +-#if 0 + bool check_rtx_costs = true; + bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); + int old_cost = set ? set_rtx_cost (set, speed) : 0; +@@ -745,7 +744,6 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn) + && (GET_CODE (XEXP (note, 0)) == CONST + || CONSTANT_P (XEXP (note, 0))))) + check_rtx_costs = false; +-#endif + + /* Usually we substitute easy stuff, so we won't copy everything. + We however need to take care to not duplicate non-trivial CONST +@@ -754,7 +752,6 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn) + + validate_replace_src_group (from, to, insn); + +-#if 0 + /* If TO is a constant, check the cost of the set after propagation + to the cost of the set before the propagation. If the cost is + higher, then do not replace FROM with TO. */ +@@ -767,7 +764,6 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn) + return false; + } + +-#endif + + if (num_changes_pending () && apply_change_group ()) + success = 1; +-- +2.7.4 + diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0060-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0060-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch new file mode 100644 index 00000000..1548faad --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0060-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch @@ -0,0 +1,466 @@ +From 80919b0f43b275e70521e4f85cd28bcd0ece3b80 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Wed, 17 Apr 2019 12:36:16 +0530 +Subject: [PATCH 60/61] [Patch,MicroBlaze]: fixed typos in mul,div and mod + assembly files. + +--- + libgcc/config/microblaze/divsi3.S | 47 ++++++++++++++++++++++++++---- + libgcc/config/microblaze/modsi3.S | 40 +++++++++++++++++++++++--- + libgcc/config/microblaze/mulsi3.S | 33 +++++++++++++++++++++- + libgcc/config/microblaze/udivsi3.S | 54 +++++++++++++++++++++++++++++++---- + libgcc/config/microblaze/umodsi3.S | 58 +++++++++++++++++++++++++++++++++++--- + 5 files changed, 212 insertions(+), 20 deletions(-) + +diff --git a/libgcc/config/microblaze/divsi3.S b/libgcc/config/microblaze/divsi3.S +index 7e7d875..cfb4c05 100644 +--- a/libgcc/config/microblaze/divsi3.S ++++ b/libgcc/config/microblaze/divsi3.S +@@ -46,7 +46,7 @@ + __divsi3: + .frame r1,0,r15 + +- ADDIK r1,r1,-32 ++ ADDLIK r1,r1,-32 + SLI r28,r1,0 + SLI r29,r1,8 + SLI r30,r1,16 +@@ -61,13 +61,23 @@ __divsi3: + SWI r30,r1,8 + SWI r31,r1,12 + #endif +- BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error +- BEQI r5,$LaResult_Is_Zero # Result is Zero +- BGEID r5,$LaR5_Pos ++#ifdef __arch64__ ++ BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error ++ BEAEQI r5,$LaResult_Is_Zero # Result is Zero ++ BEAGEID r5,$LaR5_Pos ++#else ++ BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error ++ BEQI r5,$LaResult_Is_Zero # Result is Zero ++ BGEID r5,$LaR5_Pos ++#endif + XOR r28,r5,r6 # Get the sign of the result + RSUBI r5,r5,0 # Make r5 positive + $LaR5_Pos: +- BGEI r6,$LaR6_Pos ++#ifdef __arch64__ ++ BEAGEI r6,$LaR6_Pos ++#else ++ BGEI r6,$LaR6_Pos ++#endif + RSUBI r6,r6,0 # Make r6 positive + $LaR6_Pos: + ADDIK r30,r0,0 # Clear mod +@@ -76,26 +86,51 @@ $LaR6_Pos: + + # First part try to find the first '1' in the r5 + $LaDIV0: +- BLTI r5,$LaDIV2 # This traps r5 == 0x80000000 ++#ifdef __arch64__ ++ BEALTI r5,$LaDIV2 # This traps r5 == 0x80000000 ++#else ++ BLTI r5,$LaDIV2 # This traps r5 == 0x80000000 ++#endif + $LaDIV1: + ADD r5,r5,r5 # left shift logical r5 ++#ifdef __arch64__ ++ BEAGTID r5,$LaDIV1 ++#else + BGTID r5,$LaDIV1 ++#endif + ADDIK r29,r29,-1 + $LaDIV2: + ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry + ADDC r30,r30,r30 # Move that bit into the Mod register + RSUB r31,r6,r30 # Try to subtract (r30 a r6) ++#ifdef __arch64__ ++ BEALTI r31,$LaMOD_TOO_SMALL ++#else + BLTI r31,$LaMOD_TOO_SMALL ++#endif + OR r30,r0,r31 # Move the r31 to mod since the result was positive + ADDIK r3,r3,1 + $LaMOD_TOO_SMALL: + ADDIK r29,r29,-1 ++#ifdef __arch64__ ++ BEAEQi r29,$LaLOOP_END ++#else + BEQi r29,$LaLOOP_END ++#endif + ADD r3,r3,r3 # Shift in the '1' into div ++#ifdef __arch64__ ++ BREAI $LaDIV2 # Div2 ++#else + BRI $LaDIV2 # Div2 ++#endif + $LaLOOP_END: ++#ifdef __arch64__ ++ BEAGEI r28,$LaRETURN_HERE ++ BREAID $LaRETURN_HERE ++#else + BGEI r28,$LaRETURN_HERE + BRID $LaRETURN_HERE ++#endif + RSUBI r3,r3,0 # Negate the result + $LaDiv_By_Zero: + $LaResult_Is_Zero: +diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S +index 46ff34a..49618dd 100644 +--- a/libgcc/config/microblaze/modsi3.S ++++ b/libgcc/config/microblaze/modsi3.S +@@ -62,40 +62,72 @@ __modsi3: + swi r31,r1,12 + #endif + ++#ifdef __arch64__ ++ BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error ++ BEAEQI r5,$LaResult_Is_Zero # Result is Zero ++ BEAGEId r5,$LaR5_Pos ++#else + BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error + BEQI r5,$LaResult_Is_Zero # Result is Zero + BGEId r5,$LaR5_Pos ++#endif + ADD r28,r5,r0 # Get the sign of the result [ Depends only on the first arg] + RSUBI r5,r5,0 # Make r5 positive + $LaR5_Pos: +- BGEI r6,$LaR6_Pos ++#ifdef __arch64__ ++ BEAGEI r6,$LaR6_Pos ++#else ++ BGEI r6,$LaR6_Pos ++#endif + RSUBI r6,r6,0 # Make r6 positive + $LaR6_Pos: + ADDIK r3,r0,0 # Clear mod + ADDIK r30,r0,0 # clear div +- BLTId r5,$LaDIV2 # If r5 is still negative (0x80000000), skip ++#ifdef __arch64__ ++ BEALTId r5,$LaDIV2 # If r5 is still negative (0x80000000), skip + # the first bit search. ++#else ++ BLTId r5,$LaDIV2 # If r5 is still negative (0x80000000), skip ++ # the first bit search. ++#endif + ADDIK r29,r0,32 # Initialize the loop count + # First part try to find the first '1' in the r5 + $LaDIV1: + ADD r5,r5,r5 # left shift logical r5 +- BGEID r5,$LaDIV1 # ++#ifdef __arch64__ ++ BEAGEID r5,$LaDIV1 # ++#else ++ BGEID r5,$LaDIV1 # ++#endif + ADDIK r29,r29,-1 + $LaDIV2: + ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry + ADDC r3,r3,r3 # Move that bit into the Mod register + rSUB r31,r6,r3 # Try to subtract (r30 a r6) ++#ifdef __arch64__ ++ BEALTi r31,$LaMOD_TOO_SMALL ++#else + BLTi r31,$LaMOD_TOO_SMALL ++#endif + OR r3,r0,r31 # Move the r31 to mod since the result was positive + ADDIK r30,r30,1 + $LaMOD_TOO_SMALL: + ADDIK r29,r29,-1 ++#ifdef __arch64__ ++ BEAEQi r29,$LaLOOP_END ++ ADD r30,r30,r30 # Shift in the '1' into div ++ BREAI $LaDIV2 # Div2 ++$LaLOOP_END: ++ BEAGEI r28,$LaRETURN_HERE ++ BREAId $LaRETURN_HERE ++#else + BEQi r29,$LaLOOP_END + ADD r30,r30,r30 # Shift in the '1' into div + BRI $LaDIV2 # Div2 + $LaLOOP_END: + BGEI r28,$LaRETURN_HERE + BRId $LaRETURN_HERE ++#endif + rsubi r3,r3,0 # Negate the result + $LaDiv_By_Zero: + $LaResult_Is_Zero: +@@ -108,7 +140,7 @@ $LaRETURN_HERE: + lli r29,r1,8 + lli r30,r1,16 + lli r31,r1,24 +- addik r1,r1,32 ++ addlik r1,r1,32 + rtsd r15,8 + nop + #else +diff --git a/libgcc/config/microblaze/mulsi3.S b/libgcc/config/microblaze/mulsi3.S +index 31a73c2..39951be 100644 +--- a/libgcc/config/microblaze/mulsi3.S ++++ b/libgcc/config/microblaze/mulsi3.S +@@ -43,7 +43,37 @@ + .type __mulsi3,@function + #ifdef __arch64__ + .align 3 +-#endif ++__mulsi3: ++ .frame r1,0,r15 ++ add r3,r0,r0 ++ BEAEQI r5,$L_Result_Is_Zero # Multiply by Zero ++ BEAEQI r6,$L_Result_Is_Zero # Multiply by Zero ++ BEAGEId r5,$L_R5_Pos ++ XOR r4,r5,r6 # Get the sign of the result ++ RSUBI r5,r5,0 # Make r5 positive ++$L_R5_Pos: ++ BEAGEI r6,$L_R6_Pos ++ RSUBI r6,r6,0 # Make r6 positive ++$L_R6_Pos: ++ breai $L1 ++$L2: ++ add r5,r5,r5 ++$L1: ++ srl r6,r6 ++ addc r7,r0,r0 ++ beaeqi r7,$L2 ++ beaneid r6,$L2 ++ add r3,r3,r5 ++ bealti r4,$L_NegateResult ++ rtsd r15,8 ++ nop ++$L_NegateResult: ++ rtsd r15,8 ++ rsub r3,r3,r0 ++$L_Result_Is_Zero: ++ rtsd r15,8 ++ addi r3,r0,0 ++#else + __mulsi3: + .frame r1,0,r15 + add r3,r0,r0 +@@ -74,5 +104,6 @@ $L_NegateResult: + $L_Result_Is_Zero: + rtsd r15,8 + addi r3,r0,0 ++#endif + .end __mulsi3 + .size __mulsi3, . - __mulsi3 +diff --git a/libgcc/config/microblaze/udivsi3.S b/libgcc/config/microblaze/udivsi3.S +index 94adb6a..d4fe285 100644 +--- a/libgcc/config/microblaze/udivsi3.S ++++ b/libgcc/config/microblaze/udivsi3.S +@@ -59,52 +59,96 @@ __udivsi3: + SWI r30,r1,4 + SWI r31,r1,8 + #endif ++#ifdef __arch64__ ++ BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error ++ BEAEQID r5,$LaResult_Is_Zero # Result is Zero ++#else + BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error + BEQID r5,$LaResult_Is_Zero # Result is Zero ++#endif + ADDIK r30,r0,0 # Clear mod + ADDIK r29,r0,32 # Initialize the loop count + + # Check if r6 and r5 are equal # if yes, return 1 + RSUB r18,r5,r6 ++#ifdef __arch64__ ++ BEAEQID r18,$LaRETURN_HERE ++#else + BEQID r18,$LaRETURN_HERE ++#endif + ADDIK r3,r0,1 + + # Check if (uns)r6 is greater than (uns)r5. In that case, just return 0 + XOR r18,r5,r6 +- BGEID r18,16 ++#ifdef __arch64__ ++ BEAGEID r18,16 ++#else ++ BGEID r18,16 ++#endif + ADD r3,r0,r0 # We would anyways clear r3 ++#ifdef __arch64__ ++ BEALTI r6,$LaRETURN_HERE # r6[bit 31 = 1] hence is greater ++ BREAI $LCheckr6 ++ RSUB r18,r6,r5 # MICROBLAZEcmp ++ BEALTI r18,$LaRETURN_HERE ++#else + BLTI r6,$LaRETURN_HERE # r6[bit 31 = 1] hence is greater + BRI $LCheckr6 + RSUB r18,r6,r5 # MICROBLAZEcmp + BLTI r18,$LaRETURN_HERE +- ++#endif + # If r6 [bit 31] is set, then return result as 1 + $LCheckr6: +- BGTI r6,$LaDIV0 +- BRID $LaRETURN_HERE ++#ifdef __arch64__ ++ BEAGTI r6,$LaDIV0 ++ BREAID $LaRETURN_HERE ++#else ++ BGTI r6,$LaDIV0 ++ BRID $LaRETURN_HERE ++#endif + ADDIK r3,r0,1 + + # First part try to find the first '1' in the r5 + $LaDIV0: ++#ifdef __arch64__ ++ BEALTI r5,$LaDIV2 ++#else + BLTI r5,$LaDIV2 ++#endif + $LaDIV1: + ADD r5,r5,r5 # left shift logical r5 ++#ifdef __arch64__ ++ BEAGTID r5,$LaDIV1 ++#else + BGTID r5,$LaDIV1 ++#endif + ADDIK r29,r29,-1 + $LaDIV2: + ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry + ADDC r30,r30,r30 # Move that bit into the Mod register + RSUB r31,r6,r30 # Try to subtract (r30 a r6) ++#ifdef __arch64__ ++ BEALTI r31,$LaMOD_TOO_SMALL ++#else + BLTI r31,$LaMOD_TOO_SMALL ++#endif + OR r30,r0,r31 # Move the r31 to mod since the result was positive + ADDIK r3,r3,1 + $LaMOD_TOO_SMALL: + ADDIK r29,r29,-1 ++#ifdef __arch64__ ++ BEAEQi r29,$LaLOOP_END ++ ADD r3,r3,r3 # Shift in the '1' into div ++ BREAI $LaDIV2 # Div2 ++$LaLOOP_END: ++ BREAI $LaRETURN_HERE ++#else + BEQi r29,$LaLOOP_END + ADD r3,r3,r3 # Shift in the '1' into div + BRI $LaDIV2 # Div2 + $LaLOOP_END: + BRI $LaRETURN_HERE ++#endif + $LaDiv_By_Zero: + $LaResult_Is_Zero: + OR r3,r0,r0 # set result to 0 +@@ -115,7 +159,7 @@ $LaRETURN_HERE: + LLI r29,r1,0 + LLI r30,r1,8 + LLI r31,r1,16 +- ADDIK r1,r1,24 ++ ADDLIK r1,r1,24 + RTSD r15,8 + NOP + #else +diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S +index 9bf65c3..3bd5d48 100644 +--- a/libgcc/config/microblaze/umodsi3.S ++++ b/libgcc/config/microblaze/umodsi3.S +@@ -46,7 +46,7 @@ + __umodsi3: + .frame r1,0,r15 + +- addik r1,r1,-24 ++ addlik r1,r1,-24 + sli r29,r1,0 + sli r30,r1,8 + sli r31,r1,16 +@@ -59,27 +59,77 @@ __umodsi3: + swi r30,r1,4 + swi r31,r1,8 + #endif ++#ifdef __arch64__ ++ BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error ++ BEAEQId r5,$LaResult_Is_Zero # Result is Zero ++#else + BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error + BEQId r5,$LaResult_Is_Zero # Result is Zero ++#endif + ADDIK r3,r0,0 # Clear div + ADDIK r30,r0,0 # clear mod + ADDIK r29,r0,32 # Initialize the loop count + + # Check if r6 and r5 are equal # if yes, return 0 + rsub r18,r5,r6 +- beqi r18,$LaRETURN_HERE + ++#ifdef __arch64__ ++ beaeqi r18,$LaRETURN_HERE ++#else ++ beqi r18,$LaRETURN_HERE ++#endif + # Check if (uns)r6 is greater than (uns)r5. In that case, just return r5 + xor r18,r5,r6 ++#ifdef __arch64__ ++ beageid r18,16 ++ addik r3,r5,0 ++ bealti r6,$LaRETURN_HERE ++ breai $LCheckr6 ++ rsub r18,r5,r6 # MICROBLAZEcmp ++ beagti r18,$LaRETURN_HERE ++#else + bgeid r18,16 + addik r3,r5,0 + blti r6,$LaRETURN_HERE + bri $LCheckr6 + rsub r18,r5,r6 # MICROBLAZEcmp + bgti r18,$LaRETURN_HERE +- ++#endif + # If r6 [bit 31] is set, then return result as r5-r6 + $LCheckr6: ++#ifdef __arch64__ ++ beagtid r6,$LaDIV0 ++ addik r3,r0,0 ++ addik r18,r0,0x7fffffff ++ and r5,r5,r18 ++ and r6,r6,r18 ++ breaid $LaRETURN_HERE ++ rsub r3,r6,r5 ++# First part: try to find the first '1' in the r5 ++$LaDIV0: ++ BEALTI r5,$LaDIV2 ++$LaDIV1: ++ ADD r5,r5,r5 # left shift logical r5 ++ BEAGEID r5,$LaDIV1 # ++ ADDIK r29,r29,-1 ++$LaDIV2: ++ ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry ++ ADDC r3,r3,r3 # Move that bit into the Mod register ++ rSUB r31,r6,r3 # Try to subtract (r3 a r6) ++ BEALTi r31,$LaMOD_TOO_SMALL ++ OR r3,r0,r31 # Move the r31 to mod since the result was positive ++ ADDIK r30,r30,1 ++$LaMOD_TOO_SMALL: ++ ADDIK r29,r29,-1 ++ BEAEQi r29,$LaLOOP_END ++ ADD r30,r30,r30 # Shift in the '1' into div ++ BREAI $LaDIV2 # Div2 ++$LaLOOP_END: ++ BREAI $LaRETURN_HERE ++$LaDiv_By_Zero: ++$LaResult_Is_Zero: ++ or r3,r0,r0 # set result to 0 ++#else + bgtid r6,$LaDIV0 + addik r3,r0,0 + addik r18,r0,0x7fffffff +@@ -111,7 +161,7 @@ $LaLOOP_END: + $LaDiv_By_Zero: + $LaResult_Is_Zero: + or r3,r0,r0 # set result to 0 +- ++#endif + #ifdef __arch64__ + $LaRETURN_HERE: + # Restore values of CSRs and that of r3 and the divisor and the dividend +-- +2.7.4 + diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0061-Author-Nagaraju-nmekala-xilinx.com.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0061-Author-Nagaraju-nmekala-xilinx.com.patch new file mode 100644 index 00000000..76f3e17c --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0061-Author-Nagaraju-nmekala-xilinx.com.patch @@ -0,0 +1,479 @@ +From d8b1af5c7ed5bd47d2644e20006b84f67701b856 Mon Sep 17 00:00:00 2001 +From: Nagaraju <nmekala@xilinx.com> +Date: Thu, 18 Apr 2019 16:00:37 +0530 +Subject: [PATCH 61/61] Author: Nagaraju <nmekala@xilinx.com> Date: Wed Apr + 17 14:11:00 2019 +0530 + + [Patch, microblaze]: MB-64 removal of barrel-shift instructions from default + By default MB-64 is generatting barrel-shift instructions. It has been + removed from default. Barrel-shift instructions will be generated only if + barrel-shifter is enabled. Similarly to double instructions as well. + + Signed-off-by :Nagaraju Mekala <nmekala@xilix.com> +--- + gcc/config/microblaze/microblaze.c | 2 +- + gcc/config/microblaze/microblaze.md | 269 +++++++++++++++++++++++++++++++++--- + 2 files changed, 252 insertions(+), 19 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index 33d183e..c321b03 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -3868,7 +3868,7 @@ microblaze_expand_divide (rtx operands[]) + emit_insn (gen_rtx_CLOBBER (Pmode, reg18)); + + if (TARGET_MB_64) { +- emit_insn (gen_ashldi3_long (regt1, operands[1], GEN_INT(4))); ++ emit_insn (gen_ashldi3 (regt1, operands[1], GEN_INT(4))); + emit_insn (gen_adddi3 (regt1, regt1, operands[2])); + } + else { +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 8bd175f..0d9bf8d 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -545,7 +545,7 @@ + [(set (match_operand:DF 0 "register_operand" "=d") + (plus:DF (match_operand:DF 1 "register_operand" "d") + (match_operand:DF 2 "register_operand" "d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" + "dadd\t%0,%1,%2" + [(set_attr "type" "fadd") + (set_attr "mode" "DF") +@@ -555,7 +555,7 @@ + [(set (match_operand:DF 0 "register_operand" "=d") + (minus:DF (match_operand:DF 1 "register_operand" "d") + (match_operand:DF 2 "register_operand" "d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" + "drsub\t%0,%2,%1" + [(set_attr "type" "frsub") + (set_attr "mode" "DF") +@@ -565,7 +565,7 @@ + [(set (match_operand:DF 0 "register_operand" "=d") + (mult:DF (match_operand:DF 1 "register_operand" "d") + (match_operand:DF 2 "register_operand" "d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" + "dmul\t%0,%1,%2" + [(set_attr "type" "fmul") + (set_attr "mode" "DF") +@@ -575,7 +575,7 @@ + [(set (match_operand:DF 0 "register_operand" "=d") + (div:DF (match_operand:DF 1 "register_operand" "d") + (match_operand:DF 2 "register_operand" "d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" + "ddiv\t%0,%2,%1" + [(set_attr "type" "fdiv") + (set_attr "mode" "DF") +@@ -585,7 +585,7 @@ + (define_insn "sqrtdf2" + [(set (match_operand:DF 0 "register_operand" "=d") + (sqrt:DF (match_operand:DF 1 "register_operand" "d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" + "dsqrt\t%0,%1" + [(set_attr "type" "fsqrt") + (set_attr "mode" "DF") +@@ -594,7 +594,7 @@ + (define_insn "floatdidf2" + [(set (match_operand:DF 0 "register_operand" "=d") + (float:DF (match_operand:DI 1 "register_operand" "d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" + "dbl\t%0,%1" + [(set_attr "type" "fcvt") + (set_attr "mode" "DF") +@@ -603,7 +603,7 @@ + (define_insn "fix_truncdfdi2" + [(set (match_operand:DI 0 "register_operand" "=d") + (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "d"))))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" + "dlong\t%0,%1" + [(set_attr "type" "fcvt") + (set_attr "mode" "DI") +@@ -1299,6 +1299,34 @@ + (set_attr "mode" "DI") + (set_attr "length" "4")]) + ++(define_insn "*movdi_internal2_bshift" ++ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d, d,d,R,m") ++ (match_operand:DI 1 "move_src_operand" " d,I,Mnis,R,m,dJ,dJ"))] ++ "TARGET_MB_64 && TARGET_BARREL_SHIFT" ++ { ++ switch (which_alternative) ++ { ++ case 0: ++ return "addlk\t%0,%1,r0"; ++ case 1: ++ case 2: ++ if (GET_CODE (operands[1]) == CONST_INT && ++ (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888)) ++ return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; ++ else ++ return "addlik\t%0,r0,%1"; ++ case 3: ++ case 4: ++ return "ll%i1\t%0,%1"; ++ case 5: ++ case 6: ++ return "sl%i0\t%z1,%0"; ++ } ++ } ++ [(set_attr "type" "load,no_delay_load,no_delay_load,no_delay_load,no_delay_load,no_delay_store,no_delay_store") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4,4,12,4,8,4,8")]) ++ + (define_insn "*movdi_internal2" + [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d, d,d,R,m") + (match_operand:DI 1 "move_src_operand" " d,I,Mnis,R,m,dJ,dJ"))] +@@ -1312,7 +1340,15 @@ + case 2: + if (GET_CODE (operands[1]) == CONST_INT && + (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888)) +- return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; ++ { ++ operands[2] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); ++ output_asm_insn ("addlik\t%0,r0,%h1", operands); ++ output_asm_insn ("addlik\t%2,r0,GEN_INT(32)", operands); ++ output_asm_insn ("addlik\t%2,%2,-1", operands); ++ output_asm_insn ("beaneid\t%2,.-8", operands); ++ output_asm_insn ("addlk\t%0,%0,%0", operands); ++ return "addlik\t%0,%0,%j1 #li => la"; ++ } + else + return "addlik\t%0,r0,%1"; + case 3: +@@ -1386,7 +1422,7 @@ + (define_insn "movdi_long_int" + [(set (match_operand:DI 0 "nonimmediate_operand" "=d") + (match_operand:DI 1 "general_operand" "i"))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_BARREL_SHIFT" + "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; + [(set_attr "type" "no_delay_arith") + (set_attr "mode" "DI") +@@ -1653,6 +1689,33 @@ + ;; movdf_internal + ;; Applies to both TARGET_SOFT_FLOAT and TARGET_HARD_FLOAT + ;; ++(define_insn "*movdf_internal_64_bshift" ++ [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m") ++ (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))] ++ "TARGET_MB_64 && TARGET_BARREL_SHIFT" ++ { ++ switch (which_alternative) ++ { ++ case 0: ++ return "addlk\t%0,%1,r0"; ++ case 1: ++ return "addlk\t%0,r0,r0"; ++ case 2: ++ case 4: ++ return "ll%i1\t%0,%1"; ++ case 3: ++ { ++ return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo"; ++ } ++ case 5: ++ return "sl%i0\t%1,%0"; ++ } ++ gcc_unreachable (); ++ } ++ [(set_attr "type" "no_delay_move,no_delay_move,no_delay_load,no_delay_load,no_delay_load,no_delay_store") ++ (set_attr "mode" "DF") ++ (set_attr "length" "4,4,4,16,4,4")]) ++ + (define_insn "*movdf_internal_64" + [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m") + (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))] +@@ -1669,7 +1732,13 @@ + return "ll%i1\t%0,%1"; + case 3: + { +- return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo"; ++ operands[2] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); ++ output_asm_insn ("addlik\t%0,r0,%h1", operands); ++ output_asm_insn ("addlik\t%2,r0,GEN_INT(32)", operands); ++ output_asm_insn ("addlik\t%2,%2,-1", operands); ++ output_asm_insn ("beaneid\t%2,.-8", operands); ++ output_asm_insn ("addlk\t%0,%0,%0", operands); ++ return "addlik\t%0,%0,%j1 #li => la"; + } + case 5: + return "sl%i0\t%1,%0"; +@@ -1789,11 +1858,21 @@ + "TARGET_MB_64" + { + ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) +-if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) ++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT) + { + emit_insn(gen_ashldi3_long (operands[0], operands[1],operands[2])); + DONE; + } ++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2])) ++ { ++ emit_insn(gen_ashldi3_const (operands[0], operands[1],operands[2])); ++ DONE; ++ } ++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && GET_CODE (operands[2]) == REG) ++ { ++ emit_insn(gen_ashldi3_reg (operands[0], operands[1],operands[2])); ++ DONE; ++ } + else + FAIL; + } +@@ -1803,7 +1882,7 @@ else + [(set (match_operand:DI 0 "register_operand" "=d,d") + (ashift:DI (match_operand:DI 1 "register_operand" "d,d") + (match_operand:DI 2 "arith_operand" "I,d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_BARREL_SHIFT" + "@ + bsllli\t%0,%1,%2 + bslll\t%0,%1,%2" +@@ -1811,6 +1890,51 @@ else + (set_attr "mode" "DI,DI") + (set_attr "length" "4,4")] + ) ++ ++(define_insn "ashldi3_const" ++ [(set (match_operand:DI 0 "register_operand" "=&d") ++ (ashift:DI (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "immediate_operand" "I")))] ++ "TARGET_MB_64" ++ { ++ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); ++ ++ output_asm_insn ("orli\t%3,r0,%2", operands); ++ if (REGNO (operands[0]) != REGNO (operands[1])) ++ output_asm_insn ("addlk\t%0,%1,r0", operands); ++ ++ output_asm_insn ("addlik\t%3,%3,-1", operands); ++ output_asm_insn ("beaneid\t%3,.-8", operands); ++ return "addlk\t%0,%0,%0"; ++ } ++ [(set_attr "type" "multi") ++ (set_attr "mode" "DI") ++ (set_attr "length" "20")] ++) ++ ++(define_insn "ashldi3_reg" ++ [(set (match_operand:DI 0 "register_operand" "=&d") ++ (ashift:DI (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "register_operand" "d")))] ++ "TARGET_MB_64" ++ { ++ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); ++ output_asm_insn ("andli\t%3,%2,31", operands); ++ if (REGNO (operands[0]) != REGNO (operands[1])) ++ output_asm_insn ("addlk\t%0,r0,%1", operands); ++ /* Exit the loop if zero shift. */ ++ output_asm_insn ("beaeqid\t%3,.+24", operands); ++ /* Emit the loop. */ ++ output_asm_insn ("addlk\t%0,%0,r0", operands); ++ output_asm_insn ("addlik\t%3,%3,-1", operands); ++ output_asm_insn ("beaneid\t%3,.-8", operands); ++ return "addlk\t%0,%0,%0"; ++ } ++ [(set_attr "type" "multi") ++ (set_attr "mode" "DI") ++ (set_attr "length" "28")] ++) ++ + ;; The following patterns apply when there is no barrel shifter present + + (define_insn "*ashlsi3_with_mul_delay" +@@ -1944,11 +2068,21 @@ else + "TARGET_MB_64" + { + ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) +-if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) ++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT) + { + emit_insn(gen_ashrdi3_long (operands[0], operands[1],operands[2])); + DONE; + } ++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2])) ++ { ++ emit_insn(gen_ashrdi3_const (operands[0], operands[1],operands[2])); ++ DONE; ++ } ++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && GET_CODE (operands[2]) == REG) ++ { ++ emit_insn(gen_ashrdi3_reg (operands[0], operands[1],operands[2])); ++ DONE; ++ } + else + FAIL; + } +@@ -1958,7 +2092,7 @@ else + [(set (match_operand:DI 0 "register_operand" "=d,d") + (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d") + (match_operand:DI 2 "arith_operand" "I,d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_BARREL_SHIFT" + "@ + bslrai\t%0,%1,%2 + bslra\t%0,%1,%2" +@@ -1966,6 +2100,51 @@ else + (set_attr "mode" "DI,DI") + (set_attr "length" "4,4")] + ) ++ ++(define_insn "ashrdi3_const" ++ [(set (match_operand:DI 0 "register_operand" "=&d") ++ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "immediate_operand" "I")))] ++ "TARGET_MB_64" ++ { ++ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); ++ ++ output_asm_insn ("orli\t%3,r0,%2", operands); ++ if (REGNO (operands[0]) != REGNO (operands[1])) ++ output_asm_insn ("addlk\t%0,%1,r0", operands); ++ ++ output_asm_insn ("addlik\t%3,%3,-1", operands); ++ output_asm_insn ("beaneid\t%3,.-8", operands); ++ return "srla\t%0,%0"; ++ } ++ [(set_attr "type" "arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "20")] ++) ++ ++(define_insn "ashrdi3_reg" ++ [(set (match_operand:DI 0 "register_operand" "=&d") ++ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "register_operand" "d")))] ++ "TARGET_MB_64" ++ { ++ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); ++ output_asm_insn ("andli\t%3,%2,31", operands); ++ if (REGNO (operands[0]) != REGNO (operands[1])) ++ output_asm_insn ("addlk\t%0,r0,%1", operands); ++ /* Exit the loop if zero shift. */ ++ output_asm_insn ("beaeqid\t%3,.+24", operands); ++ /* Emit the loop. */ ++ output_asm_insn ("addlk\t%0,%0,r0", operands); ++ output_asm_insn ("addlik\t%3,%3,-1", operands); ++ output_asm_insn ("beaneid\t%3,.-8", operands); ++ return "srla\t%0,%0"; ++ } ++ [(set_attr "type" "multi") ++ (set_attr "mode" "DI") ++ (set_attr "length" "28")] ++) ++ + (define_expand "ashrsi3" + [(set (match_operand:SI 0 "register_operand" "=&d") + (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") +@@ -2083,11 +2262,21 @@ else + "TARGET_MB_64" + { + ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) +-if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) ++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT) + { + emit_insn(gen_lshrdi3_long (operands[0], operands[1],operands[2])); + DONE; + } ++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2])) ++ { ++ emit_insn(gen_lshrdi3_const (operands[0], operands[1],operands[2])); ++ DONE; ++ } ++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && GET_CODE (operands[2]) == REG) ++ { ++ emit_insn(gen_lshrdi3_reg (operands[0], operands[1],operands[2])); ++ DONE; ++ } + else + FAIL; + } +@@ -2097,7 +2286,7 @@ else + [(set (match_operand:DI 0 "register_operand" "=d,d") + (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d") + (match_operand:DI 2 "arith_operand" "I,d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_BARREL_SHIFT" + "@ + bslrli\t%0,%1,%2 + bslrl\t%0,%1,%2" +@@ -2106,6 +2295,50 @@ else + (set_attr "length" "4,4")] + ) + ++(define_insn "lshrdi3_const" ++ [(set (match_operand:DI 0 "register_operand" "=&d") ++ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "immediate_operand" "I")))] ++ "TARGET_MB_64" ++ { ++ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); ++ ++ output_asm_insn ("orli\t%3,r0,%2", operands); ++ if (REGNO (operands[0]) != REGNO (operands[1])) ++ output_asm_insn ("addlk\t%0,%1,r0", operands); ++ ++ output_asm_insn ("addlik\t%3,%3,-1", operands); ++ output_asm_insn ("beaneid\t%3,.-8", operands); ++ return "srll\t%0,%0"; ++ } ++ [(set_attr "type" "multi") ++ (set_attr "mode" "DI") ++ (set_attr "length" "20")] ++) ++ ++(define_insn "lshrdi3_reg" ++ [(set (match_operand:DI 0 "register_operand" "=&d") ++ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "register_operand" "d")))] ++ "TARGET_MB_64" ++ { ++ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); ++ output_asm_insn ("andli\t%3,%2,31", operands); ++ if (REGNO (operands[0]) != REGNO (operands[1])) ++ output_asm_insn ("addlk\t%0,r0,%1", operands); ++ /* Exit the loop if zero shift. */ ++ output_asm_insn ("beaeqid\t%3,.+24", operands); ++ /* Emit the loop. */ ++ output_asm_insn ("addlk\t%0,%0,r0", operands); ++ output_asm_insn ("addlik\t%3,%3,-1", operands); ++ output_asm_insn ("beaneid\t%3,.-8", operands); ++ return "srll\t%0,%0"; ++ } ++ [(set_attr "type" "multi") ++ (set_attr "mode" "SI") ++ (set_attr "length" "28")] ++) ++ + (define_expand "lshrsi3" + [(set (match_operand:SI 0 "register_operand" "=&d") + (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") +@@ -2233,7 +2466,7 @@ else + (eq:DI + (match_operand:DI 1 "register_operand" "d") + (match_operand:DI 2 "register_operand" "d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_PATTERN_COMPARE" + "pcmpleq\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "DI") +@@ -2245,7 +2478,7 @@ else + (ne:DI + (match_operand:DI 1 "register_operand" "d") + (match_operand:DI 2 "register_operand" "d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_PATTERN_COMPARE" + "pcmplne\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "DI") +-- +2.7.4 + |