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From eaa700cb57a23278d319c888d78d597db3a35a24 Mon Sep 17 00:00:00 2001
From: John Clements <john.clements@amd.com>
Date: Tue, 3 Dec 2019 11:12:34 +0800
Subject: [PATCH 4725/4736] drm/amdgpu: Add RAS dbg print support
Leverage host to TA shared memory to capture dbg log information from RAS TA
Change-Id: I5e287560a6d493edf9bc6ac9ebbcbaeca0017dc8
Signed-off-by: John Clements <john.clements@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 34 +++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 2 +-
drivers/gpu/drm/amd/amdgpu/ta_ras_if.h | 16 ++++++++++++
3 files changed, 51 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 9b869fa9b594..f91da0b43e8c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -616,6 +616,36 @@ static int psp_xgmi_initialize(struct psp_context *psp)
}
// ras begin
+void psp_ras_print_dbg_msg(struct psp_context *psp)
+{
+ struct ta_ras_shared_memory *ras_cmd;
+ struct ta_dbg_msg_list *dbg_msgs;
+ struct ta_dbg_msg* msg;
+ uint32_t mem_offset;
+ int i, sec, m_sec;
+
+ ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
+ dbg_msgs = &ras_cmd->debug_messages;
+ msg = &dbg_msgs->msg;
+
+ for (i = 0; i < dbg_msgs->msg_cnt; i++)
+ {
+ mem_offset = (uint8_t*)msg - (uint8_t*)ras_cmd;
+
+ /* Validate memory access does not overflow shared region */
+ if (mem_offset >= PSP_RAS_SHARED_MEM_SIZE)
+ break;
+
+ /* Time stamp = seconds*1000000 + milli-seconds*1000 */
+ sec = (int)msg->time_stamp/1000000;
+ m_sec = ((int)msg->time_stamp - sec*1000000) / 1000;
+
+ DRM_INFO("[RAS] %d.%d : %s\n", sec, m_sec, msg->msg);
+
+ msg = (struct ta_dbg_msg*)((uint8_t*)msg + SIZE_OF_MSG_STRUCT(msg));
+ }
+}
+
static void psp_prep_ras_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
uint64_t ras_ta_mc, uint64_t ras_mc_shared,
uint32_t ras_ta_size, uint32_t shared_size)
@@ -679,6 +709,8 @@ static int psp_ras_load(struct psp_context *psp)
kfree(cmd);
+ psp_ras_print_dbg_msg(psp);
+
return ret;
}
@@ -747,6 +779,8 @@ int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
kfree(cmd);
+ psp_ras_print_dbg_msg(psp);
+
return ret;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 5f8fd3e3535b..a4d7690ea577 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -33,7 +33,7 @@
#define PSP_FENCE_BUFFER_SIZE 0x1000
#define PSP_CMD_BUFFER_SIZE 0x1000
#define PSP_XGMI_SHARED_MEM_SIZE 0x4000
-#define PSP_RAS_SHARED_MEM_SIZE 0x4000
+#define PSP_RAS_SHARED_MEM_SIZE 0x8000
#define PSP_1_MEG 0x100000
#define PSP_TMR_SIZE 0x400000
#define PSP_HDCP_SHARED_MEM_SIZE 0x4000
diff --git a/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h b/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h
index ca7d05993ca2..bf1c4c55ce58 100644
--- a/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h
+++ b/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h
@@ -97,6 +97,21 @@ struct ta_ras_trigger_error_input {
uint64_t value; // method if error injection. i.e persistent, coherent etc.
};
+#define SIZE_OF_MSG_STRUCT(msg_ptr) ((msg_ptr)->msg_size + sizeof(struct ta_dbg_msg) - sizeof(char))
+struct __attribute__((__packed__)) ta_dbg_msg
+{
+ uint16_t msg_size; // Not including string terminator
+ uint64_t time_stamp;
+ char msg[1]; // string of size determined by msg_size
+};
+
+struct ta_dbg_msg_list
+{
+ uint32_t total_buf_size;
+ uint32_t msg_cnt;
+ struct ta_dbg_msg msg;
+};
+
/* Common input structure for RAS callbacks */
/**********************************************************/
union ta_ras_cmd_input {
@@ -113,6 +128,7 @@ struct ta_ras_shared_memory {
enum ta_ras_status ras_status;
uint32_t reserved;
union ta_ras_cmd_input ras_in_message;
+ struct ta_dbg_msg_list debug_messages;
};
#endif // TL_RAS_IF_H_
--
2.17.1
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