diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0085-EDAC-amd64-Set-memory-type-per-DIMM.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0085-EDAC-amd64-Set-memory-type-per-DIMM.patch | 134 |
1 files changed, 134 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0085-EDAC-amd64-Set-memory-type-per-DIMM.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0085-EDAC-amd64-Set-memory-type-per-DIMM.patch new file mode 100644 index 00000000..b9a06a07 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0085-EDAC-amd64-Set-memory-type-per-DIMM.patch @@ -0,0 +1,134 @@ +From c7e861ca5dcd4a562c863009c032673014836e78 Mon Sep 17 00:00:00 2001 +From: Yazen Ghannam <yazen.ghannam@amd.com> +Date: Wed, 2 Feb 2022 14:43:06 +0000 +Subject: [PATCH 85/86] EDAC/amd64: Set memory type per DIMM + +commit 75aeaaf23def967853c8d1cfb513a6842dbc232e upstream + +Current AMD systems allow mixing of DIMM types within a system. However, +DIMMs within a channel, i.e. managed by a single Unified Memory +Controller (UMC), must be of the same type. + +Handle this possible configuration by checking and setting the memory +type for each individual "UMC" structure. + +Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> +Signed-off-by: Borislav Petkov <bp@suse.de> +Reviewed-by: William Roche <william.roche@oracle.com> +Link: https://lore.kernel.org/r/20220202144307.2678405-2-yazen.ghannam@amd.com +Signed-off-by: Zhaolong Zhang <zhaolong.zhang@windriver.com> +--- + drivers/edac/amd64_edac.c | 43 ++++++++++++++++++++++++++++----------- + drivers/edac/amd64_edac.h | 10 ++++++++- + 2 files changed, 40 insertions(+), 13 deletions(-) + +diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c +index ff29267e46a6..771b30d8c77f 100644 +--- a/drivers/edac/amd64_edac.c ++++ b/drivers/edac/amd64_edac.c +@@ -1429,7 +1429,7 @@ static void __dump_misc_regs_df(struct amd64_pvt *pvt) + edac_dbg(1, "UMC%d x16 DIMMs present: %s\n", + i, (umc->dimm_cfg & BIT(7)) ? "yes" : "no"); + +- if (pvt->dram_type == MEM_LRDDR4) { ++ if (umc->dram_type == MEM_LRDDR4) { + amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_ADDR_CFG, &tmp); + edac_dbg(1, "UMC%d LRDIMM %dx rank multiply\n", + i, 1 << ((tmp >> 4) & 0x3)); +@@ -1616,19 +1616,36 @@ static void read_dct_base_mask(struct amd64_pvt *pvt) + } + } + +-static void determine_memory_type(struct amd64_pvt *pvt) ++static void determine_memory_type_df(struct amd64_pvt *pvt) + { +- u32 dram_ctrl, dcsm; ++ struct amd64_umc *umc; ++ u32 i; + +- if (pvt->umc) { +- if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(5)) +- pvt->dram_type = MEM_LRDDR4; +- else if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(4)) +- pvt->dram_type = MEM_RDDR4; ++ for_each_umc(i) { ++ umc = &pvt->umc[i]; ++ ++ if (!(umc->sdp_ctrl & UMC_SDP_INIT)) { ++ umc->dram_type = MEM_EMPTY; ++ continue; ++ } ++ ++ if (umc->dimm_cfg & BIT(5)) ++ umc->dram_type = MEM_LRDDR4; ++ else if (umc->dimm_cfg & BIT(4)) ++ umc->dram_type = MEM_RDDR4; + else +- pvt->dram_type = MEM_DDR4; +- return; ++ umc->dram_type = MEM_DDR4; ++ ++ edac_dbg(1, " UMC%d DIMM type: %s\n", i, edac_mem_types[umc->dram_type]); + } ++} ++ ++static void determine_memory_type(struct amd64_pvt *pvt) ++{ ++ u32 dram_ctrl, dcsm; ++ ++ if (pvt->umc) ++ return determine_memory_type_df(pvt); + + switch (pvt->fam) { + case 0xf: +@@ -3442,7 +3459,9 @@ static void read_mc_regs(struct amd64_pvt *pvt) + read_dct_base_mask(pvt); + + determine_memory_type(pvt); +- edac_dbg(1, " DIMM type: %s\n", edac_mem_types[pvt->dram_type]); ++ ++ if (!pvt->umc) ++ edac_dbg(1, " DIMM type: %s\n", edac_mem_types[pvt->dram_type]); + + determine_ecc_sym_sz(pvt); + } +@@ -3538,7 +3557,7 @@ static int init_csrows_df(struct mem_ctl_info *mci) + pvt->mc_node_id, cs); + + dimm->nr_pages = get_csrow_nr_pages(pvt, umc, cs); +- dimm->mtype = pvt->dram_type; ++ dimm->mtype = pvt->umc[umc].dram_type; + dimm->edac_mode = edac_mode; + dimm->dtype = dev_type; + dimm->grain = 64; +diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h +index 650cab401e21..7691a0baacdd 100644 +--- a/drivers/edac/amd64_edac.h ++++ b/drivers/edac/amd64_edac.h +@@ -341,6 +341,9 @@ struct amd64_umc { + u32 sdp_ctrl; /* SDP Control reg */ + u32 ecc_ctrl; /* DRAM ECC Control reg */ + u32 umc_cap_hi; /* Capabilities High reg */ ++ ++ /* cache the dram_type */ ++ enum mem_type dram_type; + }; + + struct amd64_pvt { +@@ -388,7 +391,12 @@ struct amd64_pvt { + /* place to store error injection parameters prior to issue */ + struct error_injection injection; + +- /* cache the dram_type */ ++ /* ++ * cache the dram_type ++ * ++ * NOTE: Don't use this for Family 17h and later. ++ * Use dram_type in struct amd64_umc instead. ++ */ + enum mem_type dram_type; + + struct amd64_umc *umc; /* UMC registers */ +-- +2.37.3 + |