diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0064-perf-x86-amd-Make-Zen3-branch-sampling-opt-in.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0064-perf-x86-amd-Make-Zen3-branch-sampling-opt-in.patch | 129 |
1 files changed, 129 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0064-perf-x86-amd-Make-Zen3-branch-sampling-opt-in.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0064-perf-x86-amd-Make-Zen3-branch-sampling-opt-in.patch new file mode 100644 index 00000000..49b0d70d --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0064-perf-x86-amd-Make-Zen3-branch-sampling-opt-in.patch @@ -0,0 +1,129 @@ +From cde85a9d795f51d0fcdc6f0e7e5f15aa15101d5f Mon Sep 17 00:00:00 2001 +From: Stephane Eranian <eranian@google.com> +Date: Tue, 22 Mar 2022 15:15:11 -0700 +Subject: [PATCH 64/86] perf/x86/amd: Make Zen3 branch sampling opt-in + +commit cc37e520a236069c0de0e7ea455082fa11c73b12 upstream + +Add a kernel config option CONFIG_PERF_EVENTS_AMD_BRS +to make the support for AMD Zen3 Branch Sampling (BRS) an opt-in +compile time option. + +Signed-off-by: Stephane Eranian <eranian@google.com> +Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> +Link: https://lore.kernel.org/r/20220322221517.2510440-8-eranian@google.com +Signed-off-by: Zhaolong Zhang <zhaolong.zhang@windriver.com> +--- + arch/x86/events/Kconfig | 8 ++++++ + arch/x86/events/amd/Makefile | 3 ++- + arch/x86/events/perf_event.h | 49 ++++++++++++++++++++++++++++-------- + 3 files changed, 49 insertions(+), 11 deletions(-) + +diff --git a/arch/x86/events/Kconfig b/arch/x86/events/Kconfig +index d6cdfe631674..09c56965750a 100644 +--- a/arch/x86/events/Kconfig ++++ b/arch/x86/events/Kconfig +@@ -44,4 +44,12 @@ config PERF_EVENTS_AMD_UNCORE + + To compile this driver as a module, choose M here: the + module will be called 'amd-uncore'. ++ ++config PERF_EVENTS_AMD_BRS ++ depends on PERF_EVENTS && CPU_SUP_AMD ++ bool "AMD Zen3 Branch Sampling support" ++ help ++ Enable AMD Zen3 branch sampling support (BRS) which samples up to ++ 16 consecutive taken branches in registers. ++ + endmenu +diff --git a/arch/x86/events/amd/Makefile b/arch/x86/events/amd/Makefile +index cf323ffab5cd..b9f5d4610256 100644 +--- a/arch/x86/events/amd/Makefile ++++ b/arch/x86/events/amd/Makefile +@@ -1,5 +1,6 @@ + # SPDX-License-Identifier: GPL-2.0 +-obj-$(CONFIG_CPU_SUP_AMD) += core.o brs.o ++obj-$(CONFIG_CPU_SUP_AMD) += core.o ++obj-$(CONFIG_PERF_EVENTS_AMD_BRS) += brs.o + obj-$(CONFIG_PERF_EVENTS_AMD_POWER) += power.o + obj-$(CONFIG_X86_LOCAL_APIC) += ibs.o + obj-$(CONFIG_PERF_EVENTS_AMD_UNCORE) += amd-uncore.o +diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h +index 19a254cf8c7d..e2c4dc114bda 100644 +--- a/arch/x86/events/perf_event.h ++++ b/arch/x86/events/perf_event.h +@@ -1216,6 +1216,8 @@ static inline bool fixed_counter_disabled(int i, struct pmu *pmu) + #ifdef CONFIG_CPU_SUP_AMD + + int amd_pmu_init(void); ++ ++#ifdef CONFIG_PERF_EVENTS_AMD_BRS + int amd_brs_init(void); + void amd_brs_disable(void); + void amd_brs_enable(void); +@@ -1250,25 +1252,52 @@ static inline void amd_pmu_brs_del(struct perf_event *event) + + void amd_pmu_brs_sched_task(struct perf_event_context *ctx, bool sched_in); + +-/* +- * check if BRS is activated on the CPU +- * active defined as it has non-zero users and DBG_EXT_CFG.BRSEN=1 +- */ +-static inline bool amd_brs_active(void) ++static inline s64 amd_brs_adjust_period(s64 period) + { +- struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); ++ if (period > x86_pmu.lbr_nr) ++ return period - x86_pmu.lbr_nr; + +- return cpuc->brs_active; ++ return period; ++} ++#else ++static inline int amd_brs_init(void) ++{ ++ return 0; + } ++static inline void amd_brs_disable(void) {} ++static inline void amd_brs_enable(void) {} ++static inline void amd_brs_drain(void) {} ++static inline void amd_brs_lopwr_init(void) {} ++static inline void amd_brs_disable_all(void) {} ++static inline int amd_brs_setup_filter(struct perf_event *event) ++{ ++ return 0; ++} ++static inline void amd_brs_reset(void) {} + +-static inline s64 amd_brs_adjust_period(s64 period) ++static inline void amd_pmu_brs_add(struct perf_event *event) + { +- if (period > x86_pmu.lbr_nr) +- return period - x86_pmu.lbr_nr; ++} ++ ++static inline void amd_pmu_brs_del(struct perf_event *event) ++{ ++} ++ ++static inline void amd_pmu_brs_sched_task(struct perf_event_context *ctx, bool sched_in) ++{ ++} + ++static inline s64 amd_brs_adjust_period(s64 period) ++{ + return period; + } + ++static inline void amd_brs_enable_all(void) ++{ ++} ++ ++#endif ++ + #else /* CONFIG_CPU_SUP_AMD */ + + static inline int amd_pmu_init(void) +-- +2.37.3 + |