diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0056-x86-msr-Add-AMD-CPPC-MSR-definitions.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0056-x86-msr-Add-AMD-CPPC-MSR-definitions.patch | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0056-x86-msr-Add-AMD-CPPC-MSR-definitions.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0056-x86-msr-Add-AMD-CPPC-MSR-definitions.patch new file mode 100644 index 00000000..c4d54051 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0056-x86-msr-Add-AMD-CPPC-MSR-definitions.patch @@ -0,0 +1,50 @@ +From 309f58419652f454bcb7b728beb375bb49117a63 Mon Sep 17 00:00:00 2001 +From: Huang Rui <ray.huang@amd.com> +Date: Fri, 24 Dec 2021 09:04:56 +0800 +Subject: [PATCH 56/86] x86/msr: Add AMD CPPC MSR definitions + +commit 89aa94b4a218339b08f052a28c55322d5a13fc9e upstream + +AMD CPPC (Collaborative Processor Performance Control) function uses MSR +registers to manage the performance hints. So add the MSR register macro +here. + +Signed-off-by: Huang Rui <ray.huang@amd.com> +Acked-by: Borislav Petkov <bp@suse.de> +Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> +Signed-off-by: Zhaolong Zhang <zhaolong.zhang@windriver.com> +--- + arch/x86/include/asm/msr-index.h | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h +index 8f38265bc81d..23efce987acf 100644 +--- a/arch/x86/include/asm/msr-index.h ++++ b/arch/x86/include/asm/msr-index.h +@@ -525,6 +525,23 @@ + + #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f + ++/* AMD Collaborative Processor Performance Control MSRs */ ++#define MSR_AMD_CPPC_CAP1 0xc00102b0 ++#define MSR_AMD_CPPC_ENABLE 0xc00102b1 ++#define MSR_AMD_CPPC_CAP2 0xc00102b2 ++#define MSR_AMD_CPPC_REQ 0xc00102b3 ++#define MSR_AMD_CPPC_STATUS 0xc00102b4 ++ ++#define AMD_CPPC_LOWEST_PERF(x) (((x) >> 0) & 0xff) ++#define AMD_CPPC_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff) ++#define AMD_CPPC_NOMINAL_PERF(x) (((x) >> 16) & 0xff) ++#define AMD_CPPC_HIGHEST_PERF(x) (((x) >> 24) & 0xff) ++ ++#define AMD_CPPC_MAX_PERF(x) (((x) & 0xff) << 0) ++#define AMD_CPPC_MIN_PERF(x) (((x) & 0xff) << 8) ++#define AMD_CPPC_DES_PERF(x) (((x) & 0xff) << 16) ++#define AMD_CPPC_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24) ++ + /* Fam 17h MSRs */ + #define MSR_F17H_IRPERF 0xc00000e9 + +-- +2.37.3 + |