diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4695-drm-amd-display-Split-DMUB-cmd-type-into-type-subtyp.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4695-drm-amd-display-Split-DMUB-cmd-type-into-type-subtyp.patch | 286 |
1 files changed, 286 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4695-drm-amd-display-Split-DMUB-cmd-type-into-type-subtyp.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4695-drm-amd-display-Split-DMUB-cmd-type-into-type-subtyp.patch new file mode 100644 index 00000000..6919ae0e --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4695-drm-amd-display-Split-DMUB-cmd-type-into-type-subtyp.patch @@ -0,0 +1,286 @@ +From 71f9dce3ab7c375280dbc36c00eb1787083b71ec Mon Sep 17 00:00:00 2001 +From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> +Date: Tue, 12 Nov 2019 15:33:37 -0500 +Subject: [PATCH 4695/4736] drm/amd/display: Split DMUB cmd type into + type/subtype + +[Why] +Commands will be considered a stable ABI between driver and firmware. + +Commands are also split between DC commands, DAL feature commands, +and VBIOS commands. + +Commands are currently not designated to a specific ID and the enum +does not provide a stable ABI. + +We currently group all of these into a single command type of 8-bits. +With the stable ABI consideration in mind it's not unreasonable to +run out of command IDs. + +For cleaner separation and versioning split the commands into a main +type and a subtype. + +[How] +For commands where performance matters (like reg sequences) these +are still considered main commands. + +Sub commands will be split by ownership/feature. + +Update existing command sequences to reflect new changes. + +Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Leo Li <sunpeng.li@amd.com> +--- + .../drm/amd/display/dc/bios/command_table2.c | 13 +++-- + drivers/gpu/drm/amd/display/dc/dc_helper.c | 3 ++ + .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 48 +++++++------------ + .../drm/amd/display/dmub/inc/dmub_cmd_dal.h | 41 ++++++++++++++++ + .../drm/amd/display/dmub/inc/dmub_cmd_vbios.h | 41 ++++++++++++++++ + 5 files changed, 112 insertions(+), 34 deletions(-) + create mode 100644 drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd_dal.h + create mode 100644 drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd_vbios.h + +diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c +index 1836f16bb7fe..2cb7a4288cb7 100644 +--- a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c ++++ b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c +@@ -111,7 +111,8 @@ static void encoder_control_dmcub( + { + struct dmub_rb_cmd_digx_encoder_control encoder_control = { 0 }; + +- encoder_control.header.type = DMUB_CMD__DIGX_ENCODER_CONTROL; ++ encoder_control.header.type = DMUB_CMD__VBIOS; ++ encoder_control.header.sub_type = DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL; + encoder_control.encoder_control.dig.stream_param = *dig; + + dc_dmub_srv_cmd_queue(dmcub, &encoder_control.header); +@@ -219,7 +220,9 @@ static void transmitter_control_dmcub( + { + struct dmub_rb_cmd_dig1_transmitter_control transmitter_control; + +- transmitter_control.header.type = DMUB_CMD__DIG1_TRANSMITTER_CONTROL; ++ transmitter_control.header.type = DMUB_CMD__VBIOS; ++ transmitter_control.header.sub_type = ++ DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL; + transmitter_control.transmitter_control.dig = *dig; + + dc_dmub_srv_cmd_queue(dmcub, &transmitter_control.header); +@@ -302,7 +305,8 @@ static void set_pixel_clock_dmcub( + { + struct dmub_rb_cmd_set_pixel_clock pixel_clock = { 0 }; + +- pixel_clock.header.type = DMUB_CMD__SET_PIXEL_CLOCK; ++ pixel_clock.header.type = DMUB_CMD__VBIOS; ++ pixel_clock.header.sub_type = DMUB_CMD__VBIOS_SET_PIXEL_CLOCK; + pixel_clock.pixel_clock.clk = *clk; + + dc_dmub_srv_cmd_queue(dmcub, &pixel_clock.header); +@@ -650,7 +654,8 @@ static void enable_disp_power_gating_dmcub( + { + struct dmub_rb_cmd_enable_disp_power_gating power_gating; + +- power_gating.header.type = DMUB_CMD__ENABLE_DISP_POWER_GATING; ++ power_gating.header.type = DMUB_CMD__VBIOS; ++ power_gating.header.sub_type = DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING; + power_gating.power_gating.pwr = *pwr; + + dc_dmub_srv_cmd_queue(dmcub, &power_gating.header); +diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c +index acdedd889716..5f59aeeac231 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc_helper.c ++++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c +@@ -175,6 +175,7 @@ static bool dmub_reg_value_burst_set_pack(const struct dc_context *ctx, uint32_t + } + + cmd_buf->header.type = DMUB_CMD__REG_SEQ_BURST_WRITE; ++ cmd_buf->header.sub_type = 0; + cmd_buf->addr = addr; + cmd_buf->write_values[offload->reg_seq_count] = reg_val; + offload->reg_seq_count++; +@@ -203,6 +204,7 @@ static uint32_t dmub_reg_value_pack(const struct dc_context *ctx, uint32_t addr, + + /* pack commands */ + cmd_buf->header.type = DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE; ++ cmd_buf->header.sub_type = 0; + seq = &cmd_buf->seq[offload->reg_seq_count]; + + if (offload->reg_seq_count) { +@@ -227,6 +229,7 @@ static void dmub_reg_wait_done_pack(const struct dc_context *ctx, uint32_t addr, + struct dmub_rb_cmd_reg_wait *cmd_buf = &offload->cmd_data.reg_wait; + + cmd_buf->header.type = DMUB_CMD__REG_REG_WAIT; ++ cmd_buf->header.sub_type = 0; + cmd_buf->reg_wait.addr = addr; + cmd_buf->reg_wait.condition_field_value = mask & (condition_value << shift); + cmd_buf->reg_wait.mask = mask; +diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +index 43f1cd647aab..b10728f33f62 100644 +--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h ++++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +@@ -27,6 +27,8 @@ + #define _DMUB_CMD_H_ + + #include "dmub_types.h" ++#include "dmub_cmd_dal.h" ++#include "dmub_cmd_vbios.h" + #include "atomfirmware.h" + + #define DMUB_RB_CMD_SIZE 64 +@@ -34,43 +36,29 @@ + #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) + #define REG_SET_MASK 0xFFFF + ++/* ++ * Command IDs should be treated as stable ABI. ++ * Do not reuse or modify IDs. ++ */ ++ + enum dmub_cmd_type { +- DMUB_CMD__NULL, +- DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE, +- DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ, +- DMUB_CMD__REG_SEQ_BURST_WRITE, +- DMUB_CMD__REG_REG_WAIT, +- DMUB_CMD__DIGX_ENCODER_CONTROL, +- DMUB_CMD__SET_PIXEL_CLOCK, +- DMUB_CMD__ENABLE_DISP_POWER_GATING, +- DMUB_CMD__DPPHY_INIT, +- DMUB_CMD__DIG1_TRANSMITTER_CONTROL, +- DMUB_CMD__SETUP_DISPLAY_MODE, +- DMUB_CMD__BLANK_CRTC, +- DMUB_CMD__ENABLE_DISPPATH, +- DMUB_CMD__DISABLE_DISPPATH, +- DMUB_CMD__DISABLE_DISPPATH_OUTPUT, +- DMUB_CMD__READ_DISPPATH_EDID, +- DMUB_CMD__DP_PRE_LINKTRAINING, +- DMUB_CMD__INIT_CONTROLLER, +- DMUB_CMD__RESET_CONTROLLER, +- DMUB_CMD__SET_BRI_LEVEL, +- DMUB_CMD__LVTMA_CONTROL, +- +- // PSR +- DMUB_CMD__PSR_ENABLE, +- DMUB_CMD__PSR_DISABLE, +- DMUB_CMD__PSR_COPY_SETTINGS, +- DMUB_CMD__PSR_SET_LEVEL, ++ DMUB_CMD__NULL = 0, ++ DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, ++ DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, ++ DMUB_CMD__REG_SEQ_BURST_WRITE = 3, ++ DMUB_CMD__REG_REG_WAIT = 4, ++ DMUB_CMD__PSR = 64, ++ DMUB_CMD__VBIOS = 128, + }; + + #pragma pack(push, 1) + + struct dmub_cmd_header { +- enum dmub_cmd_type type : 8; +- unsigned int reserved0 : 16; ++ unsigned int type : 8; ++ unsigned int sub_type : 8; ++ unsigned int reserved0 : 8; + unsigned int payload_bytes : 6; /* up to 60 bytes */ +- unsigned int reserved : 2; ++ unsigned int reserved1 : 2; + }; + + /* +diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd_dal.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd_dal.h +new file mode 100644 +index 000000000000..14f13e8a6f3b +--- /dev/null ++++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd_dal.h +@@ -0,0 +1,41 @@ ++/* ++ * Copyright 2019 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: AMD ++ * ++ */ ++ ++#ifndef _DMUB_CMD_DAL_H_ ++#define _DMUB_CMD_DAL_H_ ++ ++/* ++ * Command IDs should be treated as stable ABI. ++ * Do not reuse or modify IDs. ++ */ ++ ++enum dmub_cmd_psr_type { ++ DMUB_CMD__PSR_ENABLE = 0, ++ DMUB_CMD__PSR_DISABLE = 1, ++ DMUB_CMD__PSR_COPY_SETTINGS = 2, ++ DMUB_CMD__PSR_SET_LEVEL = 3, ++}; ++ ++#endif /* _DMUB_CMD_DAL_H_ */ +diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd_vbios.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd_vbios.h +new file mode 100644 +index 000000000000..b6deb8e2590f +--- /dev/null ++++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd_vbios.h +@@ -0,0 +1,41 @@ ++/* ++ * Copyright 2019 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: AMD ++ * ++ */ ++ ++#ifndef _DMUB_CMD_VBIOS_H_ ++#define _DMUB_CMD_VBIOS_H_ ++ ++/* ++ * Command IDs should be treated as stable ABI. ++ * Do not reuse or modify IDs. ++ */ ++ ++enum dmub_cmd_vbios_type { ++ DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, ++ DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, ++ DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, ++ DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, ++}; ++ ++#endif /* _DMUB_CMD_VBIOS_H_ */ +-- +2.17.1 + |