diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4676-drm-amd-display-Only-wait-for-DMUB-phy-init-on-dcn21.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4676-drm-amd-display-Only-wait-for-DMUB-phy-init-on-dcn21.patch | 96 |
1 files changed, 96 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4676-drm-amd-display-Only-wait-for-DMUB-phy-init-on-dcn21.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4676-drm-amd-display-Only-wait-for-DMUB-phy-init-on-dcn21.patch new file mode 100644 index 00000000..e3c108ef --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4676-drm-amd-display-Only-wait-for-DMUB-phy-init-on-dcn21.patch @@ -0,0 +1,96 @@ +From 782580b82c79ff0c4f03499165587f81f9166545 Mon Sep 17 00:00:00 2001 +From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> +Date: Thu, 7 Nov 2019 15:26:14 -0500 +Subject: [PATCH 4676/4736] drm/amd/display: Only wait for DMUB phy init on + dcn21 + +[Why] +The wait for PHY init won't finish if the firmware doesn't support it. + +[How] +Only hook this functionality up on DCN21 and move it out of DCN20. + +For ASIC without support then this should return OK so we don't hang +while waiting in DC. + +Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Leo Li <sunpeng.li@amd.com> +--- + drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c | 5 ----- + drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h | 2 -- + drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c | 5 +++++ + drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h | 2 ++ + drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 2 +- + 5 files changed, 8 insertions(+), 8 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c +index e2b2cf2e01fd..6b7d54572aa3 100644 +--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c ++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c +@@ -135,8 +135,3 @@ bool dmub_dcn20_is_supported(struct dmub_srv *dmub) + + return supported; + } +- +-bool dmub_dcn20_is_phy_init(struct dmub_srv *dmub) +-{ +- return REG_READ(DMCUB_SCRATCH10) == 0; +-} +diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h +index e1ba748ca594..ca7db03b94f7 100644 +--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h ++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h +@@ -59,6 +59,4 @@ bool dmub_dcn20_is_hw_init(struct dmub_srv *dmub); + + bool dmub_dcn20_is_supported(struct dmub_srv *dmub); + +-bool dmub_dcn20_is_phy_init(struct dmub_srv *dmub); +- + #endif /* _DMUB_DCN20_H_ */ +diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c +index d40a808112e7..b9dc2dd645eb 100644 +--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c ++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c +@@ -124,3 +124,8 @@ bool dmub_dcn21_is_auto_load_done(struct dmub_srv *dmub) + { + return (REG_READ(DMCUB_SCRATCH0) == 3); + } ++ ++bool dmub_dcn21_is_phy_init(struct dmub_srv *dmub) ++{ ++ return REG_READ(DMCUB_SCRATCH10) == 0; ++} +diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h +index f57969d8d56f..9e5f195e288f 100644 +--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h ++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h +@@ -42,4 +42,6 @@ void dmub_dcn21_setup_windows(struct dmub_srv *dmub, + + bool dmub_dcn21_is_auto_load_done(struct dmub_srv *dmub); + ++bool dmub_dcn21_is_phy_init(struct dmub_srv *dmub); ++ + #endif /* _DMUB_DCN21_H_ */ +diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +index 60c574a39c6a..3ec26f6af2e1 100644 +--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c ++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +@@ -76,13 +76,13 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) + funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr; + funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr; + funcs->is_supported = dmub_dcn20_is_supported; +- funcs->is_phy_init = dmub_dcn20_is_phy_init; + funcs->is_hw_init = dmub_dcn20_is_hw_init; + + if (asic == DMUB_ASIC_DCN21) { + funcs->backdoor_load = dmub_dcn21_backdoor_load; + funcs->setup_windows = dmub_dcn21_setup_windows; + funcs->is_auto_load_done = dmub_dcn21_is_auto_load_done; ++ funcs->is_phy_init = dmub_dcn21_is_phy_init; + } + break; + +-- +2.17.1 + |