diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/5337-drm-amd-display-Fix-bug-use-wrong-pp-interface.patch')
-rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/5337-drm-amd-display-Fix-bug-use-wrong-pp-interface.patch | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/5337-drm-amd-display-Fix-bug-use-wrong-pp-interface.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/5337-drm-amd-display-Fix-bug-use-wrong-pp-interface.patch new file mode 100644 index 00000000..6c25cb64 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/5337-drm-amd-display-Fix-bug-use-wrong-pp-interface.patch @@ -0,0 +1,51 @@ +From ec1fddd5f88206908dabcd3579e338431346b0c3 Mon Sep 17 00:00:00 2001 +From: Rex Zhu <Rex.Zhu@amd.com> +Date: Thu, 16 Aug 2018 11:36:38 +0800 +Subject: [PATCH 5337/5725] drm/amd/display: Fix bug use wrong pp interface + +Used wrong pp interface, the original interface is +exposed by dpm on SI and paritial CI. + +Pointed out by Francis David <david.francis@amd.com> + +v2: dal only need to set min_dcefclk and min_fclk to smu. + so use display_clock_voltage_request interface, + instand of update all display configuration. + +Acked-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 12 ++++++++++-- + 1 file changed, 10 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c +index e5c5b0a..cfa907b 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c +@@ -480,12 +480,20 @@ void pp_rv_set_display_requirement(struct pp_smu *pp, + { + const struct dc_context *ctx = pp->dm; + struct amdgpu_device *adev = ctx->driver_context; ++ void *pp_handle = adev->powerplay.pp_handle; + const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; ++ struct pp_display_clock_request clock = {0}; + +- if (!pp_funcs || !pp_funcs->display_configuration_changed) ++ if (!pp_funcs || !pp_funcs->display_clock_voltage_request) + return; + +- amdgpu_dpm_display_configuration_changed(adev); ++ clock.clock_type = amd_pp_dcf_clock; ++ clock.clock_freq_in_khz = req->hard_min_dcefclk_khz; ++ pp_funcs->display_clock_voltage_request(pp_handle, &clock); ++ ++ clock.clock_type = amd_pp_f_clock; ++ clock.clock_freq_in_khz = req->hard_min_fclk_khz; ++ pp_funcs->display_clock_voltage_request(pp_handle, &clock); + } + + void pp_rv_set_wm_ranges(struct pp_smu *pp, +-- +2.7.4 + |