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Xilinx Synchronizer
-------------------
The Xilinx Synchronizer is used for buffer synchronization between
producer and consumer blocks. It manages to do so by tapping onto the bus
where the producer block is writing frame data to memory and consumer block is
reading the frame data from memory.
It can work on the encode path with max 4 channels or on decode path with
max 2 channels.
Required properties:
- compatible : Must contain "xlnx,sync-ip-1.0"
- reg: Physical base address and length of the registers set for the device.
- interrupts: Contains the interrupt line number.
- interrupt-parent: phandle to interrupt controller.
- clock-names: The input clock names for axilite, producer and consumer clock.
- clocks: Reference to the clock that drives the axi interface, producer and consumer.
- xlnx,num-chan: Range from 1 to 2 for decode.
Range from 1 to 4 for encode.
Optional properties:
- xlnx,encode: Present if IP configured for encoding path, else absent.
v_sync_vcu: subframe_sync_vcu@a00e0000 {
compatible = "xlnx,sync-ip-1.0";
reg = <0x0 0xa00e0000 0x0 0x10000>;
interrupt-parent = <&gic>;
interrupts = <0 96 4>;
clock-names = "s_axi_ctrl_aclk", "s_axi_mm_p_aclk", "s_axi_mm_aclk";
clocks = <&vid_s_axi_clk>, <&vid_stream_clk>, <&vid_stream_clk>;
xlnx,num-chan = <4>;
xlnx,encode;
};
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