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Device-Tree bindings for Xilinx I2S PL block
The IP supports I2S based playback/capture audio
Required property:
- compatible: "xlnx,i2s-transmitter-1.0" for playback and
"xlnx,i2s-receiver-1.0" for capture
Required property common to both I2S playback and capture:
- reg: Base address and size of the IP core instance.
- xlnx,dwidth: sample data width. Can be any of 16, 24.
- xlnx,num-channels: Number of I2S streams. Can be any of 1, 2, 3, 4.
supported channels = 2 * xlnx,num-channels
- xlnx,snd-pcm: reference to audio formatter block
- clock-names: List of input clocks.
Required elements for I2S Tx: "s_axi_ctrl_aclk", "aud_mclk", "s_axis_aud_aclk".
Required elements for I2S Rx: "s_axi_ctrl_aclk", "aud_mclk", "m_axis_aud_aclk".
- clocks: Input clock specifier. Refer to common clock bindings.
Example:
i2s_receiver@a0080000 {
compatible = "xlnx,i2s-receiver-1.0";
clock-names = "s_axi_ctrl_aclk", "aud_mclk", "m_axis_aud_aclk";
clocks = <&clk 71>, <&audio_ss_0_clk_wiz_0 0>, <&clk 71>;
reg = <0x0 0xa0080000 0x0 0x10000>;
xlnx,dwidth = <0x18>;
xlnx,num-channels = <1>;
xlnx,snd-pcm = <&audio_ss_0_audio_formatter_0>;
};
i2s_transmitter@a0090000 {
compatible = "xlnx,i2s-transmitter-1.0";
clock-names = "s_axi_ctrl_aclk", "aud_mclk", "s_axis_aud_aclk";
clocks = <&clk 71>, <&audio_ss_0_clk_wiz_0 0>, <&audio_ss_0_clk_wiz_0 0>;
reg = <0x0 0xa0090000 0x0 0x10000>;
xlnx,dwidth = <0x18>;
xlnx,num-channels = <1>;
xlnx,snd-pcm = <&audio_ss_0_audio_formatter_0>;
};
Documentation of "audio_ss_0_audio_formatter_0" node is located
at Documentation/devicetree/bindings/sound/xlnx,audio-formatter.txt
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