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XILINX AXI ETHERNET driver (xilinx_axienet)
--------------------------------------------------------
This driver supports following MAC configurations-
a) AXI 1G/2.5G Ethernet Subsystem.
b) 10G/25G High Speed Ethernet Subsystem.
c) 10 Gigabit Ethernet Subsystem.
d) USXGMII Ethernet Subsystem.
Management configuration is done through the AXI4-Lite interface.
The transmit and receive data interface is via the AXI4-Stream
interface connected to DMA controller. This driver supports Xilinx
AXI DMA and MCDMA DMA IP's. Programming sequence for these DMA IP's
is included in the xilinx_axienet driver.
For details about MDIO please refer phy.txt [1].
Required properties:
- compatible : Must be one of "xlnx,axi-ethernet-1.00.a" or
"xlnx,axi-ethernet-1.01.a" or "xlnx,axi-ethernet-2.01.a"
for 1G MAC,
"xlnx,ten-gig-eth-mac" for 10 Gigabit Ethernet Subsystem,
"xlnx,xxv-ethernet-1.0" for 10G/25G MAC,
"xlnx,axi-2_5-gig-ethernet-1.0" for 2.5G MAC and
"xlnx,xxv-usxgmii-ethernet-1.0" for USXGMII.
- reg : Address and length of the IO space, as well as the address
and length of the AXI DMA controller IO space, unless
axistream-connected is specified, in which case the reg
attribute of the node referenced by it is used.
- interrupts : Should be a list of 2 or 3 interrupts: TX DMA, RX DMA,
and optionally Ethernet core. If axistream-connected is
specified, the TX/RX DMA interrupts should be on that node
instead, and only the Ethernet core interrupt is optionally
specified here.
- phy-handle : See ethernet.txt [2].
- local-mac-address : See ethernet.txt [2].
- phy-mode : See ethernet.txt [2].
- axistream-connected : Should contain phandle of DMA node.
- interrupt-parent : Must be core interrupt controller.
Required properties (When AxiEthernet is configured with MCDMA):
- xlnx,channel-ids : Queue Identifier associated with the MCDMA Channel.
- interrupt-names : Should contain the interrupt names.
Optional properties:
- xlnx,rxmem : Max Rx Memory size.
- xlnx,txcsum : Tx checksum mode (Full, Partial and None).
- xlnx,rxcsum : Rx checksum mode (Full, Partial and None).
- xlnx,phy-type : Xilinx phy device type. See xilinx-phy.txt [3].
- dma-coherent : Present if dma operations are coherent.
- xlnx,eth-hasnobuf : Used when 1G MAC is configured in non-processor mode.
- clocks : AXI bus clock for the device. Refer to common clock bindings.
Used to calculate MDIO clock divisor. If not specified, it is
auto-detected from the CPU clock (but only on platforms where
this is possible). New device trees should specify this - the
auto detection is only for backward compatibility.
- axistream-connected: Reference to another node which contains the resources
for the AXI DMA controller used by this device.
If this is specified, the DMA-related resources from that
device (DMA registers and DMA TX/RX interrupts) rather
than this one will be used.
- mdio : Child node for MDIO bus. Must be defined if PHY access is
required through the core's MDIO interface (i.e. always,
unless the PHY is accessed through a different bus).
- xlnx,rxtsfifo : Configures the axi fifo for receive timestamping.
- clocks : Input clock specifier. Refer to common clock bindings.
- clock-names : Input clock names. Refer to IP PG for signal description.
1G/2.5G: s_axi_lite_clk, axis_clk and ref_clk.
10G/25G and USXGMII: s_axi_aclk, rx_core_clk and dclk.
10 Gigabit: s_axi_aclk and dclk.
AXI DMA and MCDMA: m_axi_sg_aclk, m_axi_mm2s_aclk and
m_axi_s2mm_aclk.
Optional properties (When AxiEthernet is configured with MCDMA):
- xlnx,num-queues : Number of queues/channels configured in h/w.
Optional properties (When USXGMII is in use):
- xlnx,usxgmii-rate : USXGMII PHY speed - can be 10, 100, 1000, 2500,
5000 or 10000.
Optional properties for connected DMA node:
- xlnx,addrwidth : Specify the width of the DMA address space in bits.
Value type is u8. Valid range is 32-64. Default is 32.
- xlnx,include-dre : Tells whether DMA h/w is configured with data
realignment engine(DRE) or not.
NOTE: Time Sensitive Networking (TSN) related DT bindings are explained in [4].
[1] Documentation/devicetree/bindings/net/phy.txt
[2] Documentation/devicetree/bindings/net/ethernet.txt
[3] Documentation/devicetree/bindings/net/xilinx-phy.txt
[4] Documentation/devicetree/bindings/net/xilinx_tsn.txt
Example: AXI 1G/2.5G Ethernet Subsystem + AXIDMA
axi_eth_0_dma: dma@80040000 {
#dma-cells = <1>;
compatible = "xlnx,eth-dma";
xlnx,addrwidth = /bits/ 8 <32>;
<snip>
};
axi_eth_0: ethernet@80000000 {
axistream-connected = <&axi_eth_0_dma>;
compatible = "xlnx,axi-ethernet-1.00.a";
device_type = "network";
interrupt-names = "interrupt";
interrupt-parent = <&gic>;
interrupts = <0 91 4>;
phy-handle = <&phy2>;
phy-mode = "sgmii";
reg = <0x0 0x80000000 0x0 0x40000>;
xlnx,include-dre ;
xlnx,phy-type = <0x5>;
xlnx,rxcsum = <0x0>;
xlnx,rxmem = <0x1000>;
xlnx,txcsum = <0x0>;
axi_eth_0_mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy2: phy@2 {
device_type = "ethernet-phy";
reg = <2>;
};
};
};
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