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Xilinx High-Level Synthesis Core (HLS)
--------------------------------------
High-Level Synthesis cores are synthesized from a high-level function
description developed by the user. As such their functions vary widely, but
they all share a set of common characteristics that allow them to be described
by common bindings.
Required properties:
- compatible: This property must contain "xlnx,v-hls" to indicate that the
core is compatible with the generic Xilinx HLS DT bindings. It can also
contain a more specific string to identify the HLS core implementation. The
value of those implementation-specific strings is out of scope for these DT
bindings.
- reg: Physical base address and length of the registers sets for the device.
The HLS core has two registers sets, the first one contains the core
standard registers and the second one contains the custom user registers.
- clocks: Reference to the video core clock.
- ports: Video ports, using the DT bindings defined in ../video-interfaces.txt.
The HLS core has one input port (0) and one output port (1).
Required port properties:
- xlnx,video-format: Video format as defined in video.txt.
- xlnx,video-width: Video width as defined in video.txt.
Example:
hls_0: hls@43c00000 {
compatible = "xlnx,v-hls-sobel", "xlnx,v-hls";
reg = <0x43c00000 0x24>, <0x43c00024 0xa0>;
clocks = <&clkc 15>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
xlnx,video-format = <XVIP_VF_YUV_422>;
xlnx,video-width = <8>;
hls0_in: endpoint {
remote-endpoint = <&vdma_out>;
};
};
port@1 {
reg = <1>;
xlnx,video-format = <XVIP_VF_YUV_422>;
xlnx,video-width = <8>;
hls0_out: endpoint {
remote-endpoint = <&vdma_in>;
};
};
};
};
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