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Xilinx AXI4-Stream Switch
-------------------------------
The AXI4-Stream Switch provides configurable routing between masters and slaves.
It supports up to 16 masters/sources and 16 slaves/sinks and two routing options.
There is atleast one slave/sink port and two master/source ports.
The two routing options available are TDEST routing and control register routing.
The TDEST based routing uses design parameters and hence there no software control.
Each port is mapped as a pad and has its own format specified.
Control register routing introduces an AXI4-Lite interface to configure the
routing table. There is one register for each of the master interfaces to
control each of the selectors. This routing mode requires that there is
precisely only one path between master and slave. When attempting to map the
same slave interface to multiple master interfaces, only the lowest master
interface is able to access the slave interface.
Here only the slave/sink ports have formats as master/source ports will inherit
the corresponding slave ports formats. A routing table is maintained in this case.
Please refer to PG085 AXI4-Stream Infrastructure IP Suite v2.2 for more details.
Required properties:
- compatible: Must be "xlnx,axis-switch-1.1".
- xlnx,routing-mode: Can be 0 (TDEST routing) or 1 (Control reg routing)
- xlnx,num-si-slots: Number of slave / input ports. Min 1 Max 16 .
- xlnx,num-mi-slots: Number of master / output ports. Min 1 Max 16.
- ports: Video ports, using the DT bindings defined in ../video-interfaces.txt.
- clocks: Reference to the AXI Streaming clock feeding the ACLK and
AXI4 Lite control interface clock when control routing is enabled.
- clock-names: Must have "aclk".
Optional properties:
- reg: Physical base address and length of the registers set for the device.
This is required only if xlnx,routing-mode is 1.
- clocks: Reference to AXI4 Lite control interface clock when routing-mode is 1.
- clock-names: "s_axi_ctl_clk" clock for AXI4 Lite interface when routing-mode is 1.
Example:
For TDEST routing, from 1 slave port to 4 master ports
axis_switch_0: axis_switch@0 {
compatible = "xlnx,axis-switch-1.1";
xlnx,routing-mode = <0x0>;
xlnx,num-si-slots = <0x1>;
xlnx,num-mi-slots = <0x4>;
clocks = <&vid_stream_clk>;
clock-names = "aclk";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
switch_in0: endpoint {
remote-endpoint = <&csirxss_out>;
};
};
port@1 {
reg = <1>;
switch_out0: endpoint {
remote-endpoint = <&vcap_csirxss0_in>;
};
};
port@2 {
reg = <2>;
switch_out1: endpoint {
remote-endpoint = <&vcap_csirxss1_in>;
};
};
port@3 {
reg = <3>;
switch_out2: endpoint {
remote-endpoint = <&vcap_csirxss2_in>;
};
};
port@4 {
reg = <4>;
switch_out3: endpoint {
remote-endpoint = <&vcap_csirxss3_in>;
};
};
};
};
For Control reg based routing, from 2 slave ports to 4 master ports
axis_switch_0: axis_switch@a0050000 {
compatible = "xlnx,axis-switch-1.1";
reg = <0x0 0xa0050000 0x0 0x1000>;
xlnx,routing-mode = <0x1>;
xlnx,num-si-slots = <0x2>;
xlnx,num-mi-slots = <0x4>;
clocks = <&vid_stream_clk>, <&misc_clk_0>;
clock-names = "aclk", "s_axi_ctl_clk;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
switch_in0: endpoint {
remote-endpoint = <&csirxss_out>;
};
};
port@1 {
reg = <1>;
switch_in1: endpoint {
remote-endpoint = <&tpg_out>;
};
};
port@2 {
reg = <2>;
switch_out0: endpoint {
remote-endpoint = <&vcap_csirxss0_in>;
};
};
port@3 {
reg = <3>;
switch_out1: endpoint {
remote-endpoint = <&vcap_csirxss1_in>;
};
};
port@4 {
reg = <4>;
switch_out2: endpoint {
remote-endpoint = <&vcap_csirxss2_in>;
};
};
port@5 {
reg = <5>;
switch_out3: endpoint {
remote-endpoint = <&vcap_csirxss3_in>;
};
};
};
};
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