blob: acdcc445f01b35b06c8eb190237a49855ab6c73c (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
|
* Xilinx PS PCIe Root DMA
Required properties:
- compatible: Should be "xlnx,ps_pcie_dma-1.00.a"
- reg: Register offset for Root DMA channels
- reg-names: Name for the register. Should be "ps_pcie_regbase"
- interrupts: Interrupt pin for Root DMA
- interrupt-names: Name for the interrupt. Should be "ps_pcie_rootdma_intr"
- interrupt-parent: Should be gic in case of zynqmp
- rootdma: Indicates this platform device is root dma.
This is required as the same platform driver will be invoked by pcie end points too
- dma_vendorid: 16 bit PCIe device vendor id.
This can be later used by dma client for matching while using dma_request_channel
- dma_deviceid: 16 bit PCIe device id
This can be later used by dma client for matching while using dma_request_channel
- numchannels: Indicates number of channels to be enabled for the device.
Valid values are from 1 to 4 for zynqmp
- ps_pcie_channel : One for each channel to be enabled.
This array contains channel specific properties.
Index 0: Direction of channel
Direction of channel can be either PCIe Memory to AXI memory i.e., Host to Card or
AXI Memory to PCIe memory i.e., Card to Host
PCIe to AXI Channel Direction is represented as 0x1
AXI to PCIe Channel Direction is represented as 0x0
Index 1: Number of Buffer Descriptors
This number describes number of buffer descriptors to be allocated for a channel
Index 2: Number of Queues
Each Channel has four DMA Buffer Descriptor Queues.
By default All four Queues will be managed by Root DMA driver.
User may choose to have only two queues either Source and it's Status Queue or
Destination and it's Status Queue to be handled by Driver.
The other two queues need to be handled by user logic which will not be part of this driver.
All Queues on Host is represented by 0x4
Two Queues on Host is represented by 0x2
Index 3: Coalesce Count
This number indicates the number of transfers after which interrupt needs to
be raised for the particular channel. The allowed range is from 0 to 255
Index 4: Coalesce Count Timer frequency
This property is used to control the frequency of poll timer. Poll timer is
created for a channel whenever coalesce count value (>= 1) is programmed for the particular
channel. This timer is helpful in draining out completed transactions even though interrupt is
not generated.
Client Usage:
DMA clients can request for these channels using dma_request_channel API
Xilinx PS PCIe Root DMA node Example
++++++++++++++++++++++++++++++++++++
pci_rootdma: rootdma@fd0f0000 {
compatible = "xlnx,ps_pcie_dma-1.00.a";
reg = <0x0 0xfd0f0000 0x0 0x1000>;
reg-names = "ps_pcie_regbase";
interrupts = <0 117 4>;
interrupt-names = "ps_pcie_rootdma_intr";
interrupt-parent = <&gic>;
rootdma;
dma_vendorid = /bits/ 16 <0x10EE>;
dma_deviceid = /bits/ 16 <0xD021>;
numchannels = <0x4>;
#size-cells = <0x5>;
ps_pcie_channel0 = <0x1 0x7CF 0x4 0x0 0x3E8>;
ps_pcie_channel1 = <0x0 0x7CF 0x4 0x0 0x3E8>;
ps_pcie_channel2 = <0x1 0x7CF 0x4 0x0 0x3E8>;
ps_pcie_channel3 = <0x0 0x7CF 0x4 0x0 0x3E8>;
};
|
