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2019-11-26octeontx2-af: kpu profile add support for HIGIG2 protocolHao Zheng
commit dd6d25e1cb573750dedd0d1b04e9cd0b6418cd36 from git@git.assembla.com:cavium/WindRiver.linux.git Add support for HIGIG2 protocol header to the kpu parser profile Add a NPC_LT_LA_HIGIG2_ETHER for a combined header of HIGIG2 and Ethernet. Add a NPC_LT_LA_IH_NIX_HIGIG2_ETHER for a combined header of nix_ih, HIGIG2 and Ethernet. Also add 2 upper flags in LA to indicate the presence of nix_ih and HIGIG2. Change-Id: I652ed86ab1f06f5b7f90ac4e985e1c0c854108b8 Signed-off-by: Hao Zheng <haoz@marvell.com> Reviewed-on: https://sj1git1.cavium.com/17841 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-pf: Add LIO3 link modes to ethtool's list of supported modesFelix Manlunas
commit a108847efc4ad4a07bb7f5a2612391047e979620 from git@git.assembla.com:cavium/WindRiver.linux.git For the PHY host-side, LIO3 uses the Marvell proprietary PCS types 25GBASE-R2 and 50GBASE-R4; each is combined (at the PHY line-side) with its counterpart (25G/50G Ethernet Consortium) standard PCS type (25GBASE-R or 50GBASE-R2). ethtool is not aware of and does not support Marvell proprietary PCS types; it only knows about standard PCS types. So the PF driver must pass (to ethtool) information about LIO3's PHY line-side (not PHY host-side). To that end, replace the entries of the cgx_link_mode[] lookup table that correspond to the proprietary PCS types with their standard counterparts. Also, set the bits of the macro OTX2_ETHTOOL_SUPPORTED_MODES that correspond to the proprietary modes/types. Change-Id: I993906364747abb4f75ae5ce235bf6af96ee70d0 Signed-off-by: Felix Manlunas <fmanlunas@marvell.com> Reviewed-on: https://sj1git1.cavium.com/17825 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> (cherry picked from commit c0b60c39f136e42619e9a8602b52e299af1359d1) Reviewed-on: https://sj1git1.cavium.com/17834 [Kevin: Just some minor context mods in order to port to linux-yocto] Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-pf: notify VF about ptp eventHarman Kalra
commit 1f56892993fb7d9b4aa13ed8481e3422e3d87ab1 from git@git.assembla.com:cavium/WindRiver.linux.git In case of PTP enable/disable event, PF should inform its VFs about the event. So that VFs can adjust the shifted data offset (viz 8 bytes on PTP enable). Change-Id: I83d45441ee18c53bad3b68249c32cdc273cf4fc9 Signed-off-by: Harman Kalra <hkalra@marvell.com> Reviewed-on: https://sj1git1.cavium.com/17618 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-af: Increase mbox response timeout to 2 secondsFelix Manlunas
commit 3d41081109f29fdf84517b3cd1220852f783b382 from git@git.assembla.com:cavium/WindRiver.linux.git It used to be that the intended 1 second mbox response timeout was not very precise such that the effective timeout was longer than 1 second. Recently code was checked in to make the timeout very precise. It turns out that the old, imprecise, longer-than-1-second timeout was beneficial. Now that it's been replaced with a precise 1-second timeout, we sometimes see these alarming error messages from ethtool: Cannot set new settings: Input/output error Cannot set private flags: Input/output error These turn out to be false alarms because the operations (of changing Ethernet speed or setting private flags) actually take effect. One second is not enough time for ATF to detect the arrival of a CGX_CMD, to execute the command, and to send back a response. Increase the timeout to 2 seconds for ample safety margin. Change-Id: Ia663fdf55a7a1417fc2d8b9ee751cab0903a7710 Signed-off-by: Felix Manlunas <fmanlunas@marvell.com> Reviewed-on: https://sj1git1.cavium.com/17678 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> (cherry picked from commit b842f3df534a85e70811b4490900a10d17f46f99) Reviewed-on: https://sj1git1.cavium.com/17824 Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-pf: Use BLKTYPE in register macrosSubbaraya Sundeep
commit 671aef6d85d317e805ac179c3d6d2983835e9ea1 from git@git.assembla.com:cavium/WindRiver.linux.git Use BLKTYPE instead of BLKADDR in register offset macros so that NIX1 block registers can also be accessed when required. Change-Id: I4f32885fe2fa28beb3483f84c3b13d4eb5818c04 Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/17664 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-af: Support for parsing pkts with switch headershariprasad
commit 72df259bd2f894a62c3c78e97883afe90940243c from git@git.assembla.com:cavium/WindRiver.linux.git Switch headers are designed to support better flow control and loadbalancing etc. When switch headers like EDSA, Higig2 etc are present in ingress or egress pkts default iKPU index (or PKIND) used by NPC to parse pkts will not work as there are additional headers appended to the pkt. Hence a separate Pkind is chosen on Rx and/or Tx sides to tell to KPU to parse the pkts accordingly. Changes to NPC KPU parse profile to parse headers using these iKPU indices will be pushed as a separate patch Change-Id: I1796bafadb507a528d41f96376bf44eb33cc4bb3 Signed-off-by: hariprasad <hkelam@marvell.com> Reviewed-on: https://sj1git1.cavium.com/17520 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-pf: Fix wrong info in ethtool's list of supported link modesFelix Manlunas
commit 5fe1527404347eba09db0d56b92c5cbf0a2f3092 from git@git.assembla.com:cavium/WindRiver.linux.git In otx2_get_link_mode_info(), the signed integer literal "1" is left- shifted by a value obtained by the table lookup "cgx_link_mode[bit_position]". The result is then implicitly promoted from signed int to u64 before it gets bitwise-ORed and assigned to "ethtool_link_mode" (whose type is u64). This is problematic if the result of the table lookup (which is used as the number of bit positions to left shift) is greater than or equal to 31 (one less than the bitwidth of an int). Such a situation will lead to a wrong value for "ethtool_link_mode", causing ethtool to show wrong or incomplete information in the list of supported link modes. Fix it by adding the "ULL" suffix to "1". Change-Id: I411befd4ad23df2566bf5e9cd6141faeeb53a26c Signed-off-by: Felix Manlunas <fmanlunas@marvell.com> Reviewed-on: https://sj1git1.cavium.com/17524 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> (cherry picked from commit 8b1d4774140e9b1ff99a49e2b6ab8b610631c2e9) Reviewed-on: https://sj1git1.cavium.com/17537 Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-pf: Fix clearing SQ/CQ queue interruptGeetha sowjanya
commit 751d5a0b04b7af458779149ae33cf44071e9f905 from git@git.assembla.com:cavium/WindRiver.linux.git This patch fixes cleaning SQ/CQ queue interrupt bits and LBK VF interface state after changing Queue length or number of TX/RX queues using ethtool. Change-Id: Ic0b98cc4eee22ce32c2247a8c1ffc89c3dbea6aa Signed-off-by: Geetha sowjanya <gakula@marvell.com> Reviewed-on: https://sj1git1.cavium.com/16691 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-af: Reduce mbox wait response time.Geetha sowjanya
commit 9a12d900323a132d38f0f238a971c31458ac93cb from git@git.assembla.com:cavium/WindRiver.linux.git msleep(1) in "mbox_wait_rsp()" often sleep longer i.e, ~10m. Replacing with usleep_range() as it builts on hrtimer, the wakeup will be very precise. Change-Id: I8c674f507a7d36422b1f7f73b344e25ce53a6eef Signed-off-by: Geetha sowjanya <gakula@marvell.com> Reviewed-on: https://sj1git1.cavium.com/16690 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-af: dont force enable default unicast entryhariprasad
commit debcb5884a13363a4d387ffa7cac2dd56f5ac568 from git@git.assembla.com:cavium/WindRiver.linux.git Functions which install default mcam rules like unicast, enable entries as well. This patch modifies that behavior to enable only when they were enabled before. This simplifies logic such that traffic is received only after rvu_mbox_handler_nix_lf_start_rx is called. Change-Id: I936097892c63f5210dd62e4328a2b89db45fc16f Signed-off-by: hariprasad <hkelam@marvell.com> Reviewed-on: https://sj1git1.cavium.com/17493 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-pf: Simplify ndo vf mac and vlanhariprasad
commit 68c4f101435f82b4071116ff7457c51ffcdd90a8 from git@git.assembla.com:cavium/WindRiver.linux.git Irrespective of vf interface state always send request to AF. Change-Id: I0cae60a18cef19cd95990c4a17ec61429fc2ce2e Signed-off-by: hariprasad <hkelam@marvell.com> Reviewed-on: https://sj1git1.cavium.com/17412 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-af : handle rvu pfvf mac addresshariprasad
commit a58cab5aa7d440e7e9608c55a4814e862e93a55d from git@git.assembla.com:cavium/WindRiver.linux.git Update rvu pfvf mac address in below cases * when fwdata has invalid mac * pf/vf request change in mac address Change-Id: I7d9da0e5aa810175c1aa6438c787e9f525c66942 Signed-off-by: hariprasad <hkelam@marvell.com> Reviewed-on: https://sj1git1.cavium.com/17411 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-25octeontx2-af: Get MSIXTR_BASE from fw_dataRakesh Babu
commit b58685bf513cb05f282dcfb7817664ac711ee4c0 from git@git.assembla.com:cavium/WindRiver.linux.git Get MSIX base address from firmware via fwdata structure instead of from CSR as the later will cause issue when kernel crashes and Kexec/Kdump loads secondary kernel and AF driver in the secondary kernel reads IOVA written by primary. Change-Id: I5a54638e2909e208537c68d4725f8f159201fc9d Signed-off-by: Rakesh Babu <rsaladi2@marvell.com> Reviewed-on: https://sj1git1.cavium.com/17057 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-10-31octeontx2-af: reserve top LD/LTYPEs for custom KPUStanislaw Kardach
commit 367da0d198068dd4b1310beb78ec4eb62729f7af from git@git.assembla.com:cavium/WindRiver.linux.git OCTEONTX2 NPC KPU parser configuration can be adapted to parse custom packet frames. Such configuration is called a "KPU profile". It defines both the KPU state machine as well as the LD/LTYPE values used in MCAM classification and visible in packet metadata. For performance and interoperability reasons it is best to leave a common set of LD/LTYPE flags static for all users of the HW. This commit reserves top 2 LTYPE values in each LD to allow custom creating profiles with custom protocols that would be interoperable with standard profile users. Change-Id: I31f907850da114c44c25db6b1190f6deddf7471a Signed-off-by: Stanislaw Kardach <skardach@marvell.com> Reviewed-on: https://sj1git1.cavium.com/16546 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-10-31octeontx2-af: update address of global CGX RX_STATShariprasad
commit 73be0de715d6027c9e32fb91c659e7caae032ec5 from git@git.assembla.com:cavium/WindRiver.linux.git Update address for global CGX RX_STATS by passing proper lmac value. Change-Id: I9a00411b993a11a6c7328af9b519aa809f659444 Signed-off-by: hariprasad <hkelam@marvell.com> Reviewed-on: https://sj1git1.cavium.com/16569 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-10-31octeontx2-af: Fix default profile loading checksSubbaraya Sundeep
commit b86183aa6f19548eab924c7155f4a35005965798 from git@git.assembla.com:cavium/WindRiver.linux.git Keysize of default profile is vaildated using a variable which gets initialized later. Hence get key size from register for the validation. Change-Id: Ib44ebfc1c9c9c322ebc0e0228fe0b613333214d6 Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/16520 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-10-31octeontx2-af: Init mcam resources after loading profileSubbaraya Sundeep
commit e3f9d403368f5339a345cfa0098449f465300564 from git@git.assembla.com:cavium/WindRiver.linux.git Initialize mcam resources like key width after a profile is loaded because loaded profile may change key width. Change-Id: Ia372ab9357efe6e1cb879ba3e6b8b5764b2eeb88 Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/16397 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-10-31octeontx2-af: Do not exit when firmware unavailableSubbaraya Sundeep
commit 087085463bd075d4b14b8220bf202f8877ea203b from git@git.assembla.com:cavium/WindRiver.linux.git AF driver need not bail out when no CGX devices are found. LBK devices can be used in that case. Change-Id: Ib480e9be99da3fed6d9affcc0ba137731f8c4116 Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/16285 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-10-31octeontx2-pf: Reset the PF/VF on MTU changeGeetha sowjanya
commit f511c212d5166756041444359251afff023f208b from git@git.assembla.com:cavium/WindRiver.linux.git Changing the MTU for high to low during packet transmission may lead to SMQ meta-descriptor enqueue error due to miss match in packet length and configured SMQ MAXLEN. Hence, reset the PF/VF inorder to flush SMQ before configuring new MTU. Change-Id: Icaa98653781907d9297431fc6a0b1d466d09b3e2 Signed-off-by: Geetha sowjanya <gakula@marvell.com> Reviewed-on: https://sj1git1.cavium.com/16447 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-10-31octeontx2-af: fix backpressure cfg on lf alloc and freeNithin Dabilpuram
commit e4804915b954374aeaa1ab524d3c9b40bd66d5e6 from git@git.assembla.com:cavium/WindRiver.linux.git Explicitly disable backpressure in CQ and Aura contexts during lf teardown to deassert backpressure on link as clearing CQ.ena or AURA.ena is not sufficient. Also enable pause frame config everytime lf is allocated to override previous configurations. Change-Id: Ibe50c11e6e7992e56979bbb9757e2f3cc3c3f519 Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com> Reviewed-on: https://sj1git1.cavium.com/16217 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-10-31octeontx2-pf: Add shutdown sequence for PF/VFGeetha sowjanya
commit 90c64b10f51d921844ada550493594877724686a from git@git.assembla.com:cavium/WindRiver.linux.git This patch adds pci driver shutdown support device teardown on system reboot. Change-Id: I820ee817c1b8ed399d3e309b5060334c03c5f5e5 Signed-off-by: Geetha sowjanya <gakula@marvell.com> Reviewed-on: https://sj1git1.cavium.com/16060 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-10-31octeontx2-pf: Add rx vlan offload supporthariprasad
commit f18e37bd1cf6ffe13eff7c78154e222eeb50c676 from git@git.assembla.com:cavium/WindRiver.linux.git Support vlan offload in receive path by configuring NIX to strip outer vlan. Change-Id: I3b6c6be28fe9f1804843b6cc30d18afd06d76ed5 Signed-off-by: hariprasad <hkelam@marvell.com> Reviewed-on: https://sj1git1.cavium.com/15967 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-10-31octeontx2-pf: Clear mbox interrupt status earlySubbaraya Sundeep
commit 8f3dbde036b2e6b24d68aa66cf8f980be417d987 from git@git.assembla.com:cavium/WindRiver.linux.git As long as ISR is not cleared upcoming interrupts will be lost hence clear the ISR first and queue work for processing. Change-Id: Ifd68bbbe16b91bf5640d8c7b19478f24c205da6e Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/15919 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-10-31octeontx2-af: match nvgre as ltypeKiran Kumar K
commit 7f3d06ad12b9f5cd4cd1bcb81d6f946817401949 from git@git.assembla.com:cavium/WindRiver.linux.git Add change to match NVGRE as ltype for RSS in sync with KPU profile. Change-Id: I7ee72266dab30d60bb9d9a281ee49f73ee5d2657 Signed-off-by: Kiran Kumar K <kirankumark@marvell.com> Reviewed-on: https://sj1git1.cavium.com/15626 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-10-31octeontx2-pf: Interface Mode change using ethtool.Christina Jacob
commit ea8daebe069245b205b7bbf875113b6144edc97f from git@git.assembla.com:cavium/WindRiver.linux.git Support changing cgx link mode via ethtool. Example usage: ethtool -s ethX advertise <hex_value> Change-Id: I2e77f87c8ca0a6e684c446723f823fd51780f71e Signed-off-by: Christina Jacob <cjacob@marvell.com> Reviewed-on: https://sj1git1.cavium.com/15607 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> [Kevin: Change the definition of OTX2_ETHTOOL_ALL_MODES due to the __ETHTOOL_LINK_MODE_LAST chagne.] Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-10-31octeontx2-pf: Do not set mac address againSubbaraya Sundeep
commit aaca7982f8d0883ff2b8c17737cb18607f4cd99e from git@git.assembla.com:cavium/WindRiver.linux.git AF driver sets mac address for all PFs/VFs. Setting MAC address again in otx2_open enables RX traffic before setting up NAPI hence removed it. Change-Id: Icd6182d4428b81100c5d3d55dcddd2f2da870caa Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/15665 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-10-31octeontx-af: Interface mode change feature via ethtoolChristina Jacob
commit eb65f5377da6cccad942ccb4c18819d8e3dc8a8a from git@git.assembla.com:cavium/WindRiver.linux.git Changes for supporting cgx link mode change using ethtool. Change-Id: I91cda92064ded056b074725016795f17aa114167 Signed-off-by: Christina Jacob <cjacob@marvell.com> Reviewed-on: https://sj1git1.cavium.com/15606 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-10-31octeontx2-pf: remove redundant changes from speed change suppcrt.Christina Jacob
commit 889b9c4ab3ab62a5f56abe05d4e9b7eb64722a0f from git@git.assembla.com:cavium/WindRiver.linux.git clean up speed change support via ethtool. Change-Id: I3c9f606f04c67c01421660bb3759331aa5fd80b0 Signed-off-by: Christina Jacob <cjacob@marvell.com> Reviewed-on: https://sj1git1.cavium.com/15605 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-10-31octeontx2-af: kpu profile fix for a missing action entryHao Zheng
commit f03662a20e69b916ae13ac28841381962814b358 from git@git.assembla.com:cavium/WindRiver.linux.git This patch fixes a problem where the catchall entry in KPU2 misses the corresponding action entry. Change-Id: I5525b5029623007af087170ca30e24592fcf8e6e Signed-off-by: Hao Zheng <haoz@marvell.com> Reviewed-on: https://sj1git1.cavium.com/15602 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-10-31octeontx2-af: kpu profile update for protocol nvgreHao Zheng
commit e849a34c43680a5dbe0bf18bc1317e0d290de3e2 from git@git.assembla.com:cavium/WindRiver.linux.git update kpu profile so that nvgre has a separate ltype LD_NVGRE instead of combined with LD_GRE Change-Id: I3ef48896470cfed83c203e430915252c359db210 Signed-off-by: Hao Zheng <haoz@marvell.com> Reviewed-on: https://sj1git1.cavium.com/15508 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-10-10Merge branch 'v5.2/standard/base' into v5.2/standard/cn96xxBruce Ashfield
2019-10-05skge: fix checksum byte orderStephen Hemminger
[ Upstream commit 5aafeb74b5bb65b34cc87c7623f9fa163a34fa3b ] Running old skge driver on PowerPC causes checksum errors because hardware reported 1's complement checksum is in little-endian byte order. Reported-by: Benoit <benoit.sansoni@gmail.com> Signed-off-by: Stephen Hemminger <stephen@networkplumber.org> Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-09-24Merge branch 'v5.2/standard/base' into v5.2/standard/cn96xxBruce Ashfield
2019-09-23octeontx2-af: Add T98 devid to PTP id tableTomasz Michalec
commit 6c958e5015dd3b1307f8e4382141648c14eb3b70 from git@git.assembla.com:cavium/WindRiver.linux.git This patch allows to attach Marvell PTP Driver to the PTP device on t98. Change-Id: I7dad35443c8ad96c6529f4dd2eb6c0bdf9753013 Signed-off-by: Tomasz Michalec <tomasz@marvell.com> Reviewed-on: https://sj1git1.cavium.com/15215 Reviewed-by: Chandrakala Chavva <cchavva@marvell.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-09-23octeontx2-pf: Add barrier to sync interface statusSubbaraya Sundeep
commit 446d57d2e083ee57defc821d23c52687cc880d75 from git@git.assembla.com:cavium/WindRiver.linux.git Ensure that intf_down flag is updated by using a barrier before enabling traffic. Change-Id: I61e003346030b69278d56b4d2a7bba5891470284 Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/15093 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-09-23octeontx2-pf: Fix memory leak while freeing SQBsSunil Goutham
commit b785026db2f2feec5d76d7a63421c41bc50294da from git@git.assembla.com:cavium/WindRiver.linux.git Upon enabling SQ, HW immediately fetches 2 SQB pointers from the mapped Aura, these will not be freed back to Pool once SQ is disabled. So while cleanup if we do alloc pointer from Aura and free them to kernel then 2 SQB pointers will be leaked ie never freed. Hence Aura alloc pointer cannot be used, this patch fixes this issue by saving the SQB pointers freed to Pool in the driver itself and uses that list while cleanup. Change-Id: I0ecd2a71f55d0cbf16b9d5c57ec3bc983bcb1240 Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reviewed-on: https://sj1git1.cavium.com/15089 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-09-23octeontx2-af: Add programmed macaddr to RVU pfvfVidhya Vidhyaraman
commit 203b8920a96e69616f69b4966f1b97bfb3245ea9 from git@git.assembla.com:cavium/WindRiver.linux.git This commit adds the mac address that is programmed from application into the RVU pfvf structure. The mac address retrieval will return the address from RVU pfvf structure. Change-Id: Ia9f4685b49a794dd678ed14f0e0e91d3b89de1d4 Signed-off-by: Vidhya Vidhyaraman <Vidhya.Raman@cavium.com> Reviewed-on: https://sj1git1.cavium.com/14399 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> (cherry picked from commit 232b8af019a9b0cedcf1c82ac6592282af2c74fb) Reviewed-on: https://sj1git1.cavium.com/15064 Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-09-23octeontx2-af: combine LB_STAG and LB_QINQ to one LB ltypeHao Zheng
commit 369c58581073495eae851f4813a5133cc37ef92f from git@git.assembla.com:cavium/WindRiver.linux.git NPC parser changes to combine NPC_LT_LB_STAG and NPC_LT_LB_QINQ to NPC_LT_LB_STAG_QINQ, to facilitate formulating a single MCAM entry to match on packets with one or stacked vlan tags. Change-Id: I5fa7dab5c99f2ee964123b6c81f7af695d72ba40 Signed-off-by: Hao Zheng <haoz@marvell.com> Reviewed-on: https://sj1git1.cavium.com/14808 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-09-23octeontx2-af: Fix compilation issueSunil Goutham
commit 13d8c3dd95622989a2f9499b64dbf2dfa3189f44 from git@git.assembla.com:cavium/WindRiver.linux.git Fix compilation issue introduced by patch 'commit e833c99ef4dd ("octeontx2-af: Transmit packets during SMQ flush")' Change-Id: Ice1473e779d04263577e73d5e83e2d925642cdc9 Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reviewed-on: https://sj1git1.cavium.com/14606 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Reviewed-on: https://sj1git1.cavium.com/14930 Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-09-23octeontx2-pf: Ignore NPC parser layer errorsGeetha sowjanya
commit d2a41a1a926cee01f0a2ac31a626afab33df0475 from git@git.assembla.com:cavium/WindRiver.linux.git NPC reports a layer error if none of the control flags are set in TCP packet and software drops the packets. Which is not RFC compliant. This patch fixes the issue by forwarding the packets without dropping. Change-Id: I1a2d371603124abdb2d57543478307bc13c83114 Signed-off-by: Geetha sowjanya <gakula@marvell.com> Reviewed-on: https://sj1git1.cavium.com/14568 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-09-23octeontx2-af: add parser support for DSA, extended DSA and eDSAHao Zheng
commit 27cfc1441d82840fe65d3ccb00b3ae8eeda8e489 from git@git.assembla.com:cavium/WindRiver.linux.git Marvell SOHO switches support distributed switch architecture by inserting a DSA tag right after ethernet header with a tpid of 0xDADA. Marvell Falcon switches support distributed switch architecture by inserting either a extended DSA tag of 8 bytes or a eDSA tag of 16 bytes right after the ethernet SMAC. These tags don't have a tpid field. This patch provides parser support for the tags mentioned above optionally followed by a VLAN tag. For extended DSA and eDSA tags, a special PKIND of 62 is used, as these tags don't contain a tpid field. Change-Id: I1167f2a1b47793432ac4649e1f85f9621fac3bc4 Signed-off-by: Hao Zheng <haoz@marvell.com> Reviewed-on: https://sj1git1.cavium.com/13970 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-09-23octeontx2-af: Transmit packets during SMQ flushSubbaraya Sundeep
commit accd6b7e1f2e7078aeaa9442862ca2165504ab2a from git@git.assembla.com:cavium/WindRiver.linux.git NIX SMQ flush may not complete if no send queue is transmitting packets. Hence packets need to be transmitted from a send queue when SMQ flush is initiated. This patch adds a SMQVF driver which is a stripped down version of VF netdev driver. The driver exports a function which can be called by AF driver during SMQ flush to transmit packets. A new VF of AF with pcifunc 17 is used for this purpose. So 17th AF VF should not attached to userspace. Change-Id: I6592f7615f33f423de2d464f7441864443f0dec4 Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/14560 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-09-23octeontx2-af: Always enable mcam rules for TXSubbaraya Sundeep
commit 010491289485c563d340d4782e33124bb00a346b from git@git.assembla.com:cavium/WindRiver.linux.git Enabling MCAM rule depends on whether the NIXLF is initialized or not. MCAM rules for TX can always be enabled because packet hitting a MCAM rule in TX path implies that it was transmitted by a initialized NIXLF. Change-Id: I59f33ec042b852253240a3c29fec0136066ad6ec Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/14559 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-09-23octeontx2-af: Use nix_smq_flush functionSubbaraya Sundeep
commit f31c3d4bd2b2c467b38940f56a361ea2f4002270 from git@git.assembla.com:cavium/WindRiver.linux.git nix_smq_flush function is available to flush all metadescriptors/packets from SMQ through PSE and the send data path. Hence use it wherever required. Change-Id: I9b2c85971b95780475182e8a5bd8d82a7ee9dd42 Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/14558 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-09-23octeontx2-pf: Use helper function for LBK VFSubbaraya Sundeep
commit 062ac62b16496d2d2d215d9712df8c9f7f225a44 from git@git.assembla.com:cavium/WindRiver.linux.git Helper function is available to check given device is LBK VF or not hence use it wherever required. Change-Id: Id0d548f51cd747fddbab7fde577d7968432b480e Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/14476 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-09-23octeontx2-af: Enable odd number of AF VFs alsoSubbaraya Sundeep
commit 16eaaa4a89729695d764d9a49203e9c257b11148 from git@git.assembla.com:cavium/WindRiver.linux.git Only even number of AF VFs are enabled currently and last VF is disabled if number of VFs is odd. Instead of disabling last VF altogether this patch enables it. There is no harm in doing so since last VF will remain with no pair for sending or receiving traffic. Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Change-Id: Ifdc0b4d90805a2c27c654f9147408b7f804d17de Reviewed-on: https://sj1git1.cavium.com/14475 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-09-23octeontx2-af: Change message level to debugSubbaraya Sundeep
commit 1a16c0f852a40bba93a6f3170992fba342ca811f from git@git.assembla.com:cavium/WindRiver.linux.git Message responses may time out at sender if there is no receipent hence make the time out message as dev_dbg. Change-Id: Id68d7294f2ebe52d5530692703da2bb7c44c825a Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/14491 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-09-23octeontx2-pf: Add debug messages for MSIX alloc failureSunil Goutham
commit 59a200836fd89dd2322910d0d700c4459770ee6f from git@git.assembla.com:cavium/WindRiver.linux.git Added a debug message for MSIX vector alloc and initialization failure. Change-Id: Id8adef75b0f37150555ef39609303bdea524eb52 Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reviewed-on: https://sj1git1.cavium.com/14427 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-09-23octeontx2-pf: Use post increment STP to free pointers to AuraSunil Goutham
commit b17c623daff142f98b51c0234355bd33cc5f310e from git@git.assembla.com:cavium/WindRiver.linux.git Freeing buffer pointers to Aura needs a 128bit atomic store to two 64bit registers. A regular STP can get fissioned into two separate 64bit stores which will be ignored by Aura and buffer pointer will be lost. Hence use a post increment STP. Change-Id: I0e91250f16cfe875acdb1d2c1d051ddf90cf75de Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reviewed-on: https://sj1git1.cavium.com/14426 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-09-23octeontx2-pf: Fix interface init and shutdown sequenceSunil Goutham
commit 41bf34f01baaa784960a3e5801a414eeea92ad0d from git@git.assembla.com:cavium/WindRiver.linux.git This patch fixes multiple issues - netif_carrier_off() should be done before disabling transmit at CGX/NPC level. - Fixed SQE free count checking in otx2_xmit() - In NAPI, added a check to wakeup a TXQ if incase it was stopped earlier due to queue full. - In otx2_open() 'pfvf->intf_down' should be cleared before enabling Rx at CGX/NPC level. Otherwise if in between CQ IRQ is raised then in NAPI CQ interrupt will be disabled forever. - In otx2_stop(), RQ and SQ sizes should not be cleared, otherwise upon interface DOWN and UP, RQ size will fallback to 256 which is not supported on 96xx A0. Also if user has changed RQ/SQ size via ethtool intf DOWN and UP will reset the sizes back to default. - Fixed time and packet coalescing settings, user given value was getting shifted due to wrong type used while clamping it to within supported ranges. Change-Id: I152ce646909e64ac6ff858ba0d253f3d59ea3d8d Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reviewed-on: https://sj1git1.cavium.com/14394 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-06-17 10:42:36 +0000