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path: root/drivers/net/ethernet/marvell/octeontx2
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2020-09-15octeontx2-pf: Remove wrapper APIs for mutex lock and unlockRakesh Babu
commit 248395c2a7b3b99d3ad9b13d69d5182198bdc7c4 from git@git.assembla.com:cavium/WindRiver.linux.git This patch removes wrapper fn()s around mutex_init/lock/unlock. Signed-off-by: Rakesh Babu <rsaladi2@marvell.com> Change-Id: If52051eb0c65bbe34b03d56e1c9af045ca3ca701 Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/35274 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-09-15octeontx2-af: Free RVU REE irq properlySmadar Fuks
commit 71b7c917743bd1f0c97344109dbae6e3f65c6e67 from git@git.assembla.com:cavium/WindRiver.linux.git Fix REE crash at free_irq in rvu_ree_unregister_interrupts_block during rmmod of AF driver. In order to support 2 REEs in the same interrupt handler function, request_irq is called with struct rvu_block as a cookie, instead of struct rvu. following that, free_irq should also be called with the same cookie which is struct rvu_block. In addition REE0 and REE1 have different irq names. Change-Id: I6a49d38deec74a866a045d4df3d355425546d2d9 Signed-off-by: Smadar Fuks <smadarf@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/35228 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-09-15octeontx2-af: Free RVU NIX IRQs properly.Rakesh Babu
commit 7835f527b1bb499c09940ae5cc38d5f27ad76283 from git@git.assembla.com:cavium/WindRiver.linux.git As 98xx has 2 NIX blocks, "nix_hw" data instance is passed as cookie to RVU NIX IRQ handlers instead of "rvu" data instance to distinguish among the 2 NIX IRQ handlers. To free these Interrupt handlers "nix_hw" instance should be useds as cookie, but it is left unchanged with "rvu" data instance. This leads to kernel panic when removing the AF driver. This patch fixes this panic. Change-Id: Iaa08e65877e6394f6e7eb923110707fef0448c2e Signed-off-by: Rakesh Babu <rsaladi2@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/34979 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-09-15octeontx2-af: Fix REE warnings for no previous prototypeSmadar Fuks
commit ea71358e67412557766479059d99608a4815b792 from git@git.assembla.com:cavium/WindRiver.linux.git These warnings were due to missing static declarations Change-Id: Ic41cc057ea97e18b7be23e24aaa0e2131a0cec89 Signed-off-by: Smadar Fuks <smadarf@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/34938 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-09-15octeontx2-pf: cleanup transmit link deriving logicSubbaraya Sundeep
commit a149527f26ab2a2ac156522f916b214ec5b39b60 from git@git.assembla.com:cavium/WindRiver.linux.git Unlike OcteonTx2, the channel numbers used by CGX/RPM and LBK on CN10K silicons aren't fixed in HW. They are SW programmable, hence we cannot derive transmit link from static channel numbers anymore. Get the same from admin function via mailbox. Change-Id: I093b68170f3f24f41368dccd586a57759094e19a Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/34812 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-09-15octeontx2-af: Send transmit link in mboxSubbaraya Sundeep
commit 860d655fab3086ebcbee4f215c8fd909e14a49df from git@git.assembla.com:cavium/WindRiver.linux.git Send transmit link number in the nix_lf_alloc_rsp mailbox response to AF consumers. Change-Id: I3a2a87998121b826ac83231724d6152f63d53212 Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/34811 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-09-15octeontx2-af: add npc profile support to parse NAT-T-ESPKiran Kumar K
commit e8e13a268966beb6c23678e6883fb9b3f14eb758 from git@git.assembla.com:cavium/WindRiver.linux.git Add npc profile support to parse NAT-T-ESP. NAT ESP is UDP based protocol.So, moved ESP to LE so that both UDP and ESP can be extracted. Signed-off-by: Kiran Kumar K <kirankumark@marvell.com> Change-Id: I51958e5067382e11eed315a34f481297b363b007 Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/34597 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-09-15octeontx2-af: add npc profile support to parse CPT_PARSE_HDRKiran Kumar K
commit e8e13a268966beb6c23678e6883fb9b3f14eb758 from git@git.assembla.com:cavium/WindRiver.linux.git Adding npc profile support to parse CPT_PARSE_HDR_S. cpt_parse_hdr_s will be part of LA and both ethernet header and cpt_parse_hdr_s will be extracted as part of LA. PKIND 58 has been reserved for this. Signed-off-by: Kiran Kumar K <kirankumark@marvell.com> Change-Id: I242e35bf6dee615cb2ff624127042f7857708862 Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/34606 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-09-15octeontx2-af: Backport upstream changes.Rakesh Babu
commit abc3a5994008c7167275c2cbcc0f6d77874d8daa from git@git.assembla.com:cavium/WindRiver.linux.git Backported changes from upstream kernel sources. Signed-off-by: Rakesh Babu <rsaladi2@marvell.com> Change-Id: I1c6c5b9802bd0c701249e12011ea67589ea9890a Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/34589 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-09-15octeontx2-af: Fix REE large rule file programmingSmadar Fuks
commit e6761bca8b4c58a42893015169deeebdb29043a4 from git@git.assembla.com:cavium/WindRiver.linux.git For programming purposes compiled rules (ROF), received via Mbox, are kept in memory blocks of 4MB size. Large compiled rule files require multiple memory blocks. Fixed a case in which instructions of the same ROF (prefix or graph), that were spread over multiple blocks weren't programmed correctly. Change-Id: I2251309317841e8b87cc7c1f2ecfe3a957b82513 Signed-off-by: Smadar Fuks <smadarf@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/34449 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-09-15octeontx2-af: Fix the BPID maskSubbaraya Sundeep
commit 72d2a3acac11ded56cf2ac212fae246a811f1871 from git@git.assembla.com:cavium/WindRiver.linux.git The backpressure ID to be programmed in NIX_AF_RX_CHAN(0..4095)_CFG has bit definition as [8:0] but the mask used to configure is 0xFF by mistake. This patch fixes that. Fixes: df6e0876b1e8 ("octeontx2-af: Add mbox messages to configure backpressure for an interface") Change-Id: I3949ca78dcae83e0a63d57292c6b370f25dabf2d Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/34447 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-09-15octeontx2-pf: Fix receive buffer size calculationSunil Goutham
commit 1634ec59fefebed6314484b7223a05956edd26e6 from git@git.assembla.com:cavium/WindRiver.linux.git Not considering L2 header while calculating receive buffer size resulting in pkt spilling over to next buffer. Since we no longer support multi-segmented receive pkts while processing CQE_RX these pkts are treated as errors and dropped. This patch fixes the issue to makesure pkt fits in single segment. Change-Id: I6dd49e9bc66aa4a4380b5736afd083d9aab982af Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/34367 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-09-15octeontx2-af: Fix updating wrong multicast list index in NIX_RX_ACTIONNaveen Mamindlapalli
commit 0dcc41e27a336144457985e8803d7abe6dd76b05 from git@git.assembla.com:cavium/WindRiver.linux.git This patch fixes the issue of updating wrong multicast list index in NIX_RX_ACTION when VF comes up. Otherwise, the NIX hw block receiving the broadcast traffic on the PF will attempt to refer to the incorrect multicast list index entry NIX_RX_MCE_S which was initialized to direct the traffic to another PF FUNC that may not have been initialized resulting in SMMU translation faults. Fixes: 1f2c72a130a ("octeontx2-af: Add NIX1 interfaces to NPC") Change-Id: Iad13241c7a78c40ae6bffa1be3a4c127222096de Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/34369 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-09-15octeontx2-af: Ratelimit prints from AF error interrupt handlersNaveen Mamindlapalli
commit 52f6042c889c8bb8a3743614ab1aab6f002ba8ba from git@git.assembla.com:cavium/WindRiver.linux.git Ratelimit prints from AF error interrupt handlers such as NIX AF error interrupt, NIX AF RVU error interrupt and NPA AF RVU error interrupt handler. This prevents unnecessary flooding of error messages on the console when any AF error interrupt condition triggers continuously. Change-Id: I216ef5c95ba7f320f9e7ed0800adc78044551a8e Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/34166 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-09-15octeontx2-bphy-netdev: Set minimum length of Tx packets to 64 bytesNaveen Mamindlapalli
commit a0e9c192c3c95b7c6e0442c9741902ffcf25bc19 from git@git.assembla.com:cavium/WindRiver.linux.git This patch sets the minimum length of CPRI Tx packets to 64 bytes and zero pad the buffer in case of short packets to avoid sending junk data since there is no support for zero padding in the CPRI HW. This patch fixes issue of transmitting out short packets such as ARP packets. Change-Id: I122775a0f08a36cffd3391ba3ea29720c2e01351 Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/34091 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-09-15octeontx2-pf: Support to change VLAN based RSS hash options via ethtoolGeorge Cherian
commit c066890c0646aed46b2a6d11cb6e0cf98770875e from git@git.assembla.com:cavium/WindRiver.linux.git Add support to control rx-flow-hash based on VLAN. By default VLAN plus 4-tuple based hashing is enabled. Changes can be done runtime using ethtool To enable 2-tuple plus VLAN based flow distribution # ethtool -N <intf> rx-flow-hash <prot> sdv To enable 4-tuple plus VLAN based flow distribution # ethtool -N <intf> rx-flow-hash <prot> sdfnv Change-Id: I36b1736b3882a0286e728e9c272e275f78b66bfa Signed-off-by: George Cherian <george.cherian@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/33816 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-09-15octeontx2-af: Add support for VLAN based RSS hashingGeorge Cherian
commit 887e6f37bb4c15728c2b74e6277c1c6fe778032d from git@git.assembla.com:cavium/WindRiver.linux.git Added support for PF/VF drivers to choose RSS flow key algorithm with VLAN tag included in hashing input data. Only CTAG is considered. Change-Id: Ib94984717703556f41f49cfbebb824274cdb3ea2 Signed-off-by: George Cherian <george.cherian@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/33815 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-09-15octeontx2-af: Update forwarding rule action targeting VF with its default oneNaveen Mamindlapalli
commit 568c5c354fafe7dda9a7849113482cd291af282c from git@git.assembla.com:cavium/WindRiver.linux.git Dataplane applications have limitation when installing pkt forwarding rules, where they do not support explicit Rx action to the flow rules which forward the pkts to VFs. So when RVU PF is attached to a dataplane application, all the rules that it installs targeting its VFs will have an action as UCAST resulting in all the pkts being forwarded to the RQ0 of those VFs (i.e. no flow distribution) which will have an effect on performance. This patch solves this by keeping track of all such NPC MCAM entries and ensuring that the action part is in sync with whatever VF has configured in its reserved default entry. If VF configures the default entry action as RSS, the same will be updated to all the MCAM entries that its parent PF has installed targeting this VF. Change-Id: I0751b181d24431e8a1a1699d9279be4dda9dca5d Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/33807 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-08-25Merge branch 'v5.4/standard/base' into v5.4/standard/cn96xxBruce Ashfield
2020-08-21octeontx2-af: change (struct qmem)->entry_sz from u8 to u16Eric Dumazet
[ Upstream commit 393415203f5c916b5907e0a7c89f4c2c5a9c5505 ] We need to increase TSO_HEADER_SIZE from 128 to 256. Since otx2_sq_init() calls qmem_alloc() with TSO_HEADER_SIZE, we need to change (struct qmem)->entry_sz to avoid truncation to 0. Fixes: 7a37245ef23f ("octeontx2-af: NPA block admin queue init") Signed-off-by: Eric Dumazet <edumazet@google.com> Cc: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-08-18octeontx2-pf: Avoid null pointer dereferenceSubbaraya Sundeep
commit 92fd56ae53e27c336da9e15c7c5b6e4852d95a0d from git@git.assembla.com:cavium/WindRiver.linux.git otx2_mbox_up_handler_cgx_ptp_rx_info can be called for a VF too and VF do not have ptp context. Hence check for valid ptp pointer before dereferencing. Change-Id: I30424bc1231ea4384868f22f896933fdab702c1d Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/33392 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-08-18octeontx2-bphy-netdev: Enable accessing RFOE_RX_IND regs before odp netdev initNaveen Mamindlapalli
commit 2051576d0e890374b73609d00538915bb5a17fcc from git@git.assembla.com:cavium/WindRiver.linux.git This change addresses the issue of accessing RFOE()_RX_IND_* registers using ioctl before ODP<->NETDEV initialization. Change-Id: Ie8dceabf63e79bdea44df00dc319642ea9eee059 Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/33373 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-08-18octeontx2-af: Check the msix offset return valueSubbaraya Sundeep
commit a5fd8dfa0c8eaf9d12a0097f4a1f8ba5b889ce67 from git@git.assembla.com:cavium/WindRiver.linux.git rvu_get_msix_offset can return invalid MSIX vector which is 0xFFFF. Hence the caller should check the return value otherwise possible array out of bounds can occur in rvu_clear_msix_offset function. Change-Id: I0757a0308d2e4418b46860e8078a73a72cea79ae Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/33195 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-08-18octeontx2-pf: update ethtool supported modes maskHariprasad Kelam
commit 22c602bdcd1de3b215d09228f7ee45881b8a411b from git@git.assembla.com:cavium/WindRiver.linux.git To support Sfp&Qsfp for LIO and LIO3 new link modes are supported. Update ethtool supported modes accordingly. Change-Id: Ic2a7843edded4e4db29ef1556af9fefeb4eae3be Signed-off-by: Hariprasad Kelam <hkelam@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/32649 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-08-18octeontx2-af: Stop kpu parsing at layer3 for ipv6 fragmented packets.Abhijit Ayarekar
commit 04f786035c4b55e04d2ddb22bfc85f981ba90788 from git@git.assembla.com:cavium/WindRiver.linux.git ipv6 fragmented packet may not contain completed layer 4 information. So stop kpu parsing after setting ipv6 fragmentation flag. Change-Id: I0f49bcb47dfc5b646c1d296ee452537ea48ba756 Signed-off-by: Abhijit Ayarekar <aayarekar@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/32626 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-08-18octeontx2-af: make tx nibble fixup is always applyStanislaw Kardach
commit 9edebecf71d71add7acd9b3d2603eb342c455768 from git@git.assembla.com:cavium/WindRiver.linux.git NPC_PARSE_NIBBLE for TX interface has to be equal to the RX one for some silicon revisions. Mistakenly this fixup was only applied to the default MKEX profile while it should also be applied to any loaded profile. Change-Id: Idd4b843a5423aeca79027d49deb39b8b26dea487 Signed-off-by: Stanislaw Kardach <skardach@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/32569 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-08-18octeontx2-vf: initialize interface mode as defaultHariprasad Kelam
commit 93dd7c497513541d5be35203789bc0f19e5fcfb6 from git@git.assembla.com:cavium/WindRiver.linux.git To support parsing switch protocols like HIGIG and DSA ,PF sets its interface mode accordingly on user request. But this not applicable for VF.So always initialize interface mode as default for VFs. Change-Id: I321b91d1154fda3d607e7a9ca32b96526b7d39c8 Signed-off-by: Hariprasad Kelam <hkelam@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/32607 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-08-18octeontx2-af: Fix max 16 CGX LMACs limitRakesh Babu
commit e6d90f879fa2edf72e3835f183f69785974889b7 from git@git.assembla.com:cavium/WindRiver.linux.git CN98xx supports upto 20 CGX LMAC ports. 'cgxlmac2pf_map' being 16 bit limits the number of CGX LMACs to 16. This patch fixes this limit. Signed-off-by: Rakesh Babu <rsaladi2@marvell.com> Change-Id: I1fd818cf4674a51c64920dd2103d4807f5493958 Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/32611 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-08-18octeontx2-pf: Call mbox_reset before incrementing ackHariprasad Kelam
commit fb9f0913a1456407f13c0594000589cf8b19b842 from git@git.assembla.com:cavium/WindRiver.linux.git Mbox has three states alloc, send, reset in mbox response. In few scenarios mbox reset of previous message is triggered while current request is in send state which is resulting mbox errors. To avoid the same call mbox_reset before incrementing msgs_acked flag and check msg has valid size. Change-Id: If78d2635818b766396b6ed549852b24c3baf863b Signed-off-by: Hariprasad Kelam <hkelam@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/32456 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-08-18octeontx2-af: Simplify otx2_mbox_reset callHariprasad Kelam
commit d67f287c2818736ba534f6182dfaaae987bbd80c from git@git.assembla.com:cavium/WindRiver.linux.git Refactor otx2_mbox_reset so that __otx2_mbox_reset can be called without lock protection. Change-Id: I82bc0367530780e20e1a5b455aef1d241e348ebc Signed-off-by: Hariprasad Kelam <hkelam@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/32457 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-08-18octeontx2-af: Increase number of CGX interfacesHariprasad Kelam
commit 46922d68230d3cc65bfaf1ffda8ea09c38932bc9 from git@git.assembla.com:cavium/WindRiver.linux.git 98xx board has 5 CGX interfaces adjust CGX_MAX value accordingly. Change-Id: Ide7a3952c4bb5ed35b148b0db82bfd58598f21f2 Signed-off-by: Hariprasad Kelam <hkelam@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/31918 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-08-10octeontx2-bphy-netdev: Enable MSIXEN bit in IOCTL handlerNaveen Mamindlapalli
commit 92e095632f9c5bbe2f448ecad868586d42a35423 from git@git.assembla.com:cavium/WindRiver.linux.git This patch enables the MSIX_CAP_HDR MSIXEN bit in the IOCTL handler that is used by the ODP BPHY code to configure the BPHY netdev interfaces, otherwise the MSIXEN bit would be cleared when the ODP BPHY code tries to initialize the BPHY module before calling the IOCTL. Change-Id: I48fe5931e9c2e8e25c9e18d68b72170bcd08bf5d Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/32475 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-08-10otx2-bphy-netdev: Add support for configurable PTP clock rateNaveen Mamindlapalli
commit a35d79185361b3078860eabb99446a2b165269c7 from git@git.assembla.com:cavium/WindRiver.linux.git This patch adds support for configuring the PTP clock rate via ioctl that is used by PTP timestamp algorithm. The default PTP clock rate used is 0.95GHz. Change-Id: I5a5fa7e52b208070a116a730e5d192a5c5afdbf1 Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/31818 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-08-10otx2-bphy-netdev: Add support for registering both rfoe and cpri netdev intfNaveen Mamindlapalli
commit 8d4594aff8269fecbc31f5fab8d6c73080399266 from git@git.assembla.com:cavium/WindRiver.linux.git This patch provides support for registering netdev interface for both rfoe and cpri links so that the interfaces are available in Linux all the time. The Nokia interface management application is responsible for the administrative status of each netdev interface. The resources required for both interface types are configured during start-up using the ODP BPHY application. The netdev driver will drop the Tx pkts when the interface is not enabled by ODP BPHY application. Change-Id: I83e19fedf4801c6593caecfc5fcb354cc7b1f9cc Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/31817 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-08-10octeontx2-af: fix Extended DSA and eDSA parsingSatha Rao
commit 03f7a63a9b71af1657b7b7d5294b41fcf928f624 from git@git.assembla.com:cavium/WindRiver.linux.git KPU profile interpret Extended DSA and eDSA by looking source dev. This was incorrect and it restricts to use few source device ids and also created confusion while parsing regular DSA tag. With below patch lookup was based on bit 12 of Word0. This is always zero for DSA tag and it should be one for Extended DSA and eDSA. Change-Id: I0e38d5343cb630be38a243fac3848313ab6f1d4f Signed-off-by: Satha Rao <skoteshwar@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/31683 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-07-13octeonx2-bphy-netdev: Add support for switching mode from RFOE to CPRINaveen Mamindlapalli
commit 8a189bb049a40e6eacd6fece70f43533e3f23a24 from git@git.assembla.com:cavium/WindRiver.linux.git This patch adds support for switching the mode from RFOE to CPRI. The rfoe netdev interfaces are unregistered and cpri netdev interfaces are registered. The reverse switching is not possible because of HW limitations. Change-Id: I29a040812ebfb4f428a40590c029719ad070e5b2 Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/31331 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-07-13octeontx2-bphy-netdev: Add support for CPRI Ethernet packet processingNaveen Mamindlapalli
commit 40529cdad4607a7bf36c8af7bddd9f3aba4e6e39 from git@git.assembla.com:cavium/WindRiver.linux.git This patch adds support for processing Ethernet packets which are received and transmitted by CPRI MHAB. The ODP BPHY application shares the CPRI ETH UL/DL configuration information using ioctl. The Rx packet reception notification is sent to netdev using PSM GPINT. Change-Id: I158dcd48771f0e9a793079954e1c3271ddd69cfc Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/31330 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-07-13octeontx2-bphy-netdev: segregate chardev specific codeNaveen Mamindlapalli
commit 27ca582b6f6ab1625082bf23817f192df988bcf7 from git@git.assembla.com:cavium/WindRiver.linux.git This patch segregates the chardev specific code in otx2_rfoe.c to make the code more readable and to prepare for integrating CPRI packet handling code in upcoming patches. Did some code cleanup and refactoring. Change-Id: I70bf6d0bc3026a93fb2ac11f43967c3353dcf603 Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/31329 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-07-13octeontx2-af: reset HWS group mask during FLRMichal Mazur
commit f485b25de66b15c4c04bd708e10f5f06d5ee22a6 from git@git.assembla.com:cavium/WindRiver.linux.git This patch fixes errors caused by deprecated SSOW group mask stored in registers after application is killed and then restarted. Change-Id: I08144ae24b5a43fcecf0bea84f7cf9778dc8239a Signed-off-by: Michal Mazur <mmazur2@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/31273 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-07-13octeontx2-bphy-netdev: Fix NULL pointer dereferenceNaveen Mamindlapalli
commit b11a7fd0d4ec3bb68eca2591873974b890b1b527 from git@git.assembla.com:cavium/WindRiver.linux.git Checking the return value of platform_get_resource() to avoid NULL pointer dereference. Change-Id: I096230c347286e2676d1132bfc235a98763bdc92 Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/30633 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-07-13octeontx2-af: Debugfs entry to show mapping btw CGX, NIX and a PF.Rakesh Babu
commit 553e1fa27d03b8907fbff81ee8699b49bdfe1b32 from git@git.assembla.com:cavium/WindRiver.linux.git Unlike earlier silicon variants, OcteonTx2 98xx silicon has 2 NIX blocks and each of the CGX is mapped to either of the NIX blocks. Each NIX block supports 100G. Mapping btw NIX blocks and CGX is done by firmware based on CGX speed config to have a maximum possible network bandwidth. Since the mapping is not fixed, it's difficult for a user to figure out. Hence added a debugfs entry which displays mapping between CGX LMAC, NIX block and RVU PF. Sample result of this entry :: ~# cat /sys/kernel/debug/octeontx2/rvu_pf_cgx_map PCI dev RVU PF Func NIX block CGX LMAC 0002:02:00.0 0x400 NIX0 CGX0 LMAC0 Change-Id: Icadea896dbadc39f7886c0fe1e6f66bab1b104eb Signed-off-by: Rakesh Babu <rsaladi2@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/30386 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-07-13octeontx2-bphy-netdev: Enable MSIXEN bit in MSIX CAP HDRNaveen Mamindlapalli
commit cbda7bed39fb1137a2677500b7ce8d85d72b0ee1 from git@git.assembla.com:cavium/WindRiver.linux.git This patch enables MSIXEN bit so that the BPHY device can generate interrupts. Change-Id: I355764115ed48d0c550b5d039c22f265487918b6 Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/30371 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-07-13octeontx2-bphy-netdev: Added PTP BCN offset algorithmNaveen Mamindlapalli
commit 1654986b3146b8040967e9dec93fef9d15fd3922 from git@git.assembla.com:cavium/WindRiver.linux.git PTP clock time operates by adding a constant increment every clock cycle. That increment is expressed (MIO_PTP_CLOCK_COMP) as a Q32.32 number of nanoseconds (32 integer bits and 32 fractional bits). The value must be equal to 1/(PTP clock frequency in Hz). If the PTP clock freq is 1 GHz, there is no issue but for other input clock frequency values for example 950 MHz which is SLCK or 153.6 MHz (bcn_clk/2) the MIO_PTP_CLOCK_COMP register value can't be expressed exactly and there will be error accumulated over the time depending on the direction the PTP_CLOCK_COMP value is rounded. The accumulated error will be around -70ps or +150 ps per second in case of 950 MHz. To solve this issue, the driver calculates the PTP timestamps using BCN clock as reference as per the algorithm proposed as given below. Set PTP tick (= MIO_PTP_CLOCK_COMP) to 1.0 ns Sample once, at exactly the same time, BCN and PTP to (BCN0, PTP0). Calculate (applying BCN-to-PTP epoch difference and an OAM parameter secondaryBcnOffset) PTPbase[ns] = NanoSec(BCN0)+NanoSec(315964819[s])-secondaryBcnOffset[ns] When reading packet timestamp (tick count) PTPn, convert it to nanoseconds. PTP pkt timestamp = PTPbase[ns] + (PTPn - PTP0) / (PTP Clock in GHz) The intermediate values generated need to be of pico-second precision to achieve PTP accuracy < 1ns. The calculations should not overflow 64-bit value at anytime. Added timer to adjust the PTP and BCN base values periodically to fix the overflow issue. Change-Id: I170dc92abc4737b5279b4d3da4a38c1cfa753c62 Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/29821 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-07-13octeontx2-af: Fix REE error handlingSmadar Fuks
commit 5257c04b1ab44c21dc7027322aebfbda2aa6d742 from git@git.assembla.com:cavium/WindRiver.linux.git Fix few cases in which error indication was not propogated to the calling function: - ree_init didn't pass rvu_ree_init_block failure indication, which can be either memory allocation or polling for CSR init completion - rvu_mbox_handler_ree_rule_db_prog didn't pass programming failure - ree_rof_data_enq didn't pass failure to get AF AQ done indication Change-Id: Iaa5c9ca99b89eaba6c0cf565eede937c9709af54 Signed-off-by: Smadar Fuks <smadarf@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/29725 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-06-25octeontx2-af: Fix deadlock between tx_stall->txsch_lock and rvu->rsrc_lockKevin Hao
The patch ("octeontx2-af: wait for tx link idle for credits change") introduces a ABBA deadlock: kworker/u49:1/257 is trying to acquire lock: 000000009c4ce30c (&tx_stall->txsch_lock){+.+.}, at: rvu_nix_update_link_credits+0x50/0x78 but task is already holding lock: 00000000dd73fbc7 (&rvu->rsrc_lock){+.+.}, at: rvu_mbox_handler_nix_set_hw_frs+0x3e8/0x648 which lock already depends on the new lock. the existing dependency chain (in reverse order) is: -> #1 (&rvu->rsrc_lock){+.+.}: __mutex_lock+0x94/0x830 mutex_lock_nested+0x3c/0x50 is_valid_txschq+0x94/0x108 rvu_mbox_handler_nix_txschq_cfg+0x16c/0x628 __rvu_mbox_handler+0x1bcc/0x27d8 rvu_afvf_mbox_handler+0x10/0x18 process_one_work+0x29c/0x6d8 worker_thread+0x50/0x418 kthread+0x108/0x138 ret_from_fork+0x10/0x18 -> #0 (&tx_stall->txsch_lock){+.+.}: lock_acquire+0xfc/0x288 __mutex_lock+0x94/0x830 mutex_lock_nested+0x3c/0x50 rvu_nix_update_link_credits+0x50/0x78 rvu_mbox_handler_nix_set_hw_frs+0x5b4/0x648 __rvu_mbox_handler+0x1fec/0x27d8 rvu_afpf_mbox_handler+0x10/0x18 process_one_work+0x29c/0x6d8 worker_thread+0x50/0x418 kthread+0x108/0x138 ret_from_fork+0x10/0x18 other info that might help us debug this: Possible unsafe locking scenario: CPU0 CPU1 ---- ---- lock(&rvu->rsrc_lock); lock(&tx_stall->txsch_lock); lock(&rvu->rsrc_lock); lock(&tx_stall->txsch_lock); Adjust the lock sequence in nix_config_link_credits() to fix this. Signed-off-by: Kevin Hao <kexin.hao@windriver.com> Signed-off-by: Bruce Ashfield <bruce.ashfield@gmail.com>
2020-06-16octeontx2-bphy-netdev: Added ioctl to access RFOE_RX_IND registersNaveen Mamindlapalli
commit e3f8daef6a9e861f85e0b2d09c02ca53a413c684 from git@git.assembla.com:cavium/WindRiver.linux.git 1. Added ioctl to read/write RFOE()_RX_IND_* registers from ODP application. This will fix the RFOE()_RX_IND_* register access corruption when both driver and ODP application tries to read/write using RFOE_RX_INDIRECT_INDEX register without any synchronization in place. 2. Removed unnecessary spinlock in irq handler. Change-Id: I7ae16f64d6851c234af88fe723783f52c64c3ab0 Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/29368 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2020-06-16octeontx2-af: fix DMAC filter table corruptionSunil Kumar Kori
commit 6c05d2a46a9246b85ed23874fa7a14900648adb1 from git@git.assembla.com:cavium/WindRiver.linux.git DMAC filter table is being corrupted in following 2 scenarios: - If CGXX has more than one lmac connected then default MAC addresses are being written continuosly starting from 0th index. Further if one DMAC filter is added to LMAC0 then entry will be added at index 1 so default MAC address for LMAC1 is corrupted. - If LMAC has DMAC filters confiured and further LMAC is set to promiscious mode then only default MAC address entry is being disabled while remaining are in enable state in conjunction of CGX(0..2)_CMR(0..3)_RX_DMAC_CTL0[CAM_ACCEPT] == 0. Because of this, mathcing traffic is dropped at CGX while they should pass as system is in promiscious mode. Patch fixes both the issues. Change-Id: I85eae1f8b1672e5c0fa3eaf4ffb42940378606e6 Signed-off-by: Sunil Kumar Kori <skori@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/29170 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2020-06-16octeontx2-af: Add new Mbox messages and handlers for new REE blocksSmadar Fuks
commit 49706eeef363a5d492919e91e01489c173dc520b from git@git.assembla.com:cavium/WindRiver.linux.git Mailbox support for REE0 and REE1 blocks in 98xx platform. This patch adds new REE mailbox messages to mbox.h: - Config LF - REE BAR0 registers read and write - REE get Rule database length - REE get Rule database for incremental programming - REE Rule database programming This patch adds the corresponding new mbox handlers to rvu_ree.c The rule database that is passed via mbox contains instruction of address and data and is programmed to REE. For programming REE allocates memory that is accessed by HW: - 128-MB structure containing the complete compiled regular-expression graphs - AF Queue that points to 16KB blocks that hold filtering instructions REE also allocates memory for keeping the rule database that was received via mbox. It is used for immediate programming and future incremental programming Change-Id: I3679b736bafac8ba944f47252dad52fb2fce6506 Signed-off-by: Smadar Fuks <smadarf@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/29294 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2020-06-16octeontx2-af: Introducing REE block for 98xxSmadar Fuks
commit a4d454585655319d82d1e97283a91d356ba1d72d from git@git.assembla.com:cavium/WindRiver.linux.git CN98XX Regular Expression Engine (REE) includes a two-part regular expression search engine consisting of filter engine and graph-walk engines. Input data (job) is searched against the regular expression rule set by first traversing the filter engine and if matched passing full Thompson NFA graph walk. These 2 REE blocks (REE0 and REE1) are introduced in 98xx. REE is provisioned using RVU. REE has up to 36 local functions (queues) A new file rvu_ree.c is added to support the new REE block with the following functions: - Initialization - Free memory - Interrupt registration and handling The following changes were done in rvu.c for ree: - Added calls to ree functions init, free memory, register/unregister interrupts and teardown - Added member struct ree_rsrc in struct rvu_pfvf to hold ree data - Added member struct rvu *rvu in struct rvu_block so that interrupt handler will know the block address Change-Id: I33184efaed9bab2954c8604d462b8945dda892d4 Signed-off-by: Smadar Fuks <smadarf@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/29293 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2020-06-16octeontx2-af: Enable PF BCAST entry for packet replicationSubbaraya Sundeep
commit 17d6f59e6956177ae07b0a13ed42e7ede15d1ec7 from git@git.assembla.com:cavium/WindRiver.linux.git nix_update_bcast_mce_list function used for adding or deleting a PF/VF into replication list disables PF broadcast entry if replication list is empty. Hence it is caller responsibility to enable PF broadcast entry if replication list becomes non-empty. Change-Id: I467ca6647f0b2b92e64c0919aed8213503acccff Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/29173 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-06-29 11:15:04 +0000